KR910000543Y1 - Skip circuit for image tube - Google Patents
Skip circuit for image tube Download PDFInfo
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- KR910000543Y1 KR910000543Y1 KR2019860010922U KR860010922U KR910000543Y1 KR 910000543 Y1 KR910000543 Y1 KR 910000543Y1 KR 2019860010922 U KR2019860010922 U KR 2019860010922U KR 860010922 U KR860010922 U KR 860010922U KR 910000543 Y1 KR910000543 Y1 KR 910000543Y1
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- South Korea
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- transistor
- terminal
- output
- operational amplifier
- pulse width
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- 230000003287 optical effect Effects 0.000 claims description 10
- 239000003990 capacitor Substances 0.000 claims description 9
- 230000001360 synchronised effect Effects 0.000 claims description 5
- 238000003079 width control Methods 0.000 claims description 4
- 238000003384 imaging method Methods 0.000 claims description 2
- 239000011651 chromium Substances 0.000 description 10
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 6
- 101000746134 Homo sapiens DNA endonuclease RBBP8 Proteins 0.000 description 6
- 101000969031 Homo sapiens Nuclear protein 1 Proteins 0.000 description 6
- 102100021133 Nuclear protein 1 Human genes 0.000 description 6
- 229910052804 chromium Inorganic materials 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
- 230000003111 delayed effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K4/00—Generating pulses having essentially a finite slope or stepped portions
- H03K4/06—Generating pulses having essentially a finite slope or stepped portions having triangular shape
- H03K4/08—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N3/00—Scanning details of television systems; Combination thereof with generation of supply voltages
- H04N3/10—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical
- H04N3/16—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by deflecting electron beam in cathode-ray tube, e.g. scanning corrections
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
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- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Details Of Television Scanning (AREA)
Abstract
내용 없음.No content.
Description
제1도는 본 고안의 실시예를 나타내는 상세회로도.1 is a detailed circuit diagram showing an embodiment of the present invention.
제2도는 제1도의 회로 동작을 설명하기 위한 각부분의 입출력 파형도이다.FIG. 2 is an input / output waveform diagram of each part for explaining the circuit operation of FIG.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 톱니파 발생부 2 : 반전부1: Sawtooth wave generating unit 2: Inverting unit
3 : 펄스폭 조절부 4 : 비교출력부3: pulse width control unit 4: comparison output unit
본 고안은 비데오 카메라에서 촬상관의 옵티칼 블랙 인접부위를 스키프(SKIP)하는 회로에 관한 것이다.The present invention relates to a circuit for skipping the optical black adjacent portion of the image pickup tube in the video camera.
일반적으로 비데오 카메라 촬상관에서 신호를 얻는 부분중 일부 시작 지역은 광학적 흑 레벨지역을 만들어서 비데오 신호에서 최저 흑 레벨인 옵티칼 블랙 레벨을 만들어 사용되고 있으나, 이 부분은 크롬(Cr)으로 도포하여서 옵티칼 블랙을 만들 때 인접지역에까지 크롬(Cr)이 번지게 되므로 이곳에서는 좋은 신호가 출력되지 못한 문제점이 있었다.In general, some of the areas where signals are obtained from the video camera imager are used to make an optical black level area, thereby making an optical black level, which is the lowest black level in the video signal, but this part is coated with chromium (Cr) to produce an optical black. When the chromium (Cr) is spread to the adjacent area there was a problem that a good signal was not output.
본 고안은 상기와 같은 종래기술의 문제점을 해결하기 위하여 안출한 것으로써, 옵티칼 블랙 부분에 크롬(Cr)이 도포된 인접부위를 수직동기 신호가 스캔(SCAN)할 때 크롬의 오염지역을 스키프(SKIP)하여 다음의 영역부터 정상적인 편향을 할 수 있는 촬상관의 옵티칼 블랙 인접부위 스키프회로를 제공하는데 그 목적이 있다.The present invention was devised to solve the above problems of the prior art, and when the vertical synchronous signal scans the adjacent portions of chromium (Cr) coated on the optical black portion, the chromium is skipped. It is an object of the present invention to provide an optical black adjacent part skip circuit of an imaging tube that can perform a normal deflection from the following area.
이하, 본 고안의 바람직한 실시예를 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail.
제1도는 본 고안의 실시예를 나타낸 상세회로도로써 수직동기신호를 발생하는 수직구동단(VD)은 저항(R1)을 통해 트랜지스터(Q1)의 베이스에 연결되고, 트랜지스터(Q1)의 에미터는 접지콘덴서(C2)와 접지저항(R2)에 연결되며, 트랜지스터(Q1)의 콜렉터는 가변저항(VR1)과 저항(R3)을 통해 전원(Vcc)에 연결되고, 트랜지스터(Q1)의 에미터와 콜렉터사이에 콘덴서(C1)가 연결되어 구성된 톱니파 발생부(1)와, 수직동기신호를 발생하는 수직 구동단(VD)이 저항(R4)을 통해 에미터가 접지된 트랜지스터(Q2)의 베이스에 연결되어 구성된 반전부(2)와, 상기 반전부(2)의 콜렉터 출력단은 단안정 멀티바이브레이터(MUT)의 ″바″단자에 연결되고, 동시에 저항(R5,R6)과 가변저항(VR2)을 통해 단안정 멀티바이브레이터(MUT)의 ″사″단자와 ″아″단자에 연결되며, 저항(R5,R6)의 접속점은 단안정 멀티바이브레이터(MUT)의 ″가″ 단자와 ″나″단자에 연결되고, 단안정 멀티바이브레이터(MUT)의 ″가″단자에는 비교기(COM1,COM2)의 비반전단자(+)연결되며, 비교기(COM1, COM 2)의 반전단자(-)에는 ″바″단자와 ″사″단자가 연결되고, 비교기(COM1,COM2)의 출력단은 플립플롭(FF)의 세트(S)단자와 리세터(R)단자에 연결되며, 플립플롭(FF)의 출력단은 버퍼(I)를 통해″다″단자에 연결되어 구성된 펄스폭 조절부(3)와, 상기한 톱니파 발생부(1)의 출력단은 연산증폭기(OP1)의 비반전단자(+)에 연결됨과 동시에 제너다이오드(ZD)와 접지저항(R1)을 통해 트랜지스터(Q4)의 콜렉터에 연결되고, 상기한 펄스폭 조절부(3)의 출력단은 가변저항(VR3)을 통해 연산증폭기(OP1)의 반전단자(-)에 연결되며, 연산증폭기(OP1)의 출력단은 트랜지스터(Q4)의 베이스에 연결됨과 동시에 다이오드(D1,D2)를 통하여 콜렉터가 전원에 연결된 트랜지스터(Q3)의 베이스에 연결되고, 트랜지스터(Q3)의 에미터는 저항(R9,R10)을 통해 트랜지스터(Q4)의 에미터에 연결되어구성된 비교출력부(4)로 이루어져 있다.1 is a detailed circuit diagram illustrating an embodiment of the present invention. The vertical driving terminal VD generating a vertical synchronization signal is connected to the base of the transistor Q1 through a resistor R1, and the emitter of the transistor Q1 is grounded. It is connected to the capacitor (C2) and the ground resistor (R2), the collector of the transistor (Q1) is connected to the power supply (Vcc) through the variable resistor (VR1) and the resistor (R3), the emitter and collector of the transistor (Q1) A sawtooth wave generator 1 having a capacitor C1 connected therebetween, and a vertical drive terminal VD for generating a vertical synchronous signal, are connected to the base of the transistor Q2 having the emitter grounded through a resistor R4. The inverter 2 and the collector output terminal of the inverter 2 are connected to the ″ bar ″ terminals of the monostable multivibrator MUT, and at the same time through the resistors R5 and R6 and the variable resistor VR2. It is connected to the ″ a ″ and ″ a ″ terminals of the monostable multivibrator (MUT), and the connection point of the resistors R5 and R6. ″ Of the monostable multivibrator (MUT) is connected to the ″ or ″ terminal, ″ of the monostable multivibrator (MUT) is connected to the non-inverting terminal (+) of the comparators (COM1, COM2). The inverting terminals (-) of the comparators (COM1, COM 2) are connected to the ″ bar ″ and ″ company ″ terminals, and the output terminals of the comparators (COM1, COM2) are the set (S) terminals and the resetters of the flip-flop (FF). (R) terminal, the output terminal of the flip-flop (FF) is connected to the terminal ″ d ″ through the buffer (I) and the pulse width adjusting section 3 and the output terminal of the sawtooth wave generator 1 It is connected to the non-inverting terminal (+) of the operational amplifier (OP1) and is connected to the collector of the transistor (Q4) through the zener diode (ZD) and the ground resistor (R1), the output terminal of the pulse width control unit (3) Is connected to the inverting terminal (-) of the operational amplifier OP1 through the variable resistor VR3, and the output terminal of the operational amplifier OP1 is connected to the base of the transistor Q4. The collector is connected to the base of transistor Q3 connected to the power supply via diodes D1 and D2, and the emitter of transistor Q3 is connected to the emitter of transistor Q4 via resistors R9 and R10. Comparing output section (4).
이와같은 구성을 갖는 동작을 제2도를 참조하여 상세히 설명한다.An operation having such a configuration will be described in detail with reference to FIG.
수직구동단(VD)에서 출력되는 제2a도와 같은 수직동기신호가 저항(R1)을 통하여 트랜지스터(Q1)의 베이스에 인가된다. 이때 제2a도와 같은 수직동기 신호에서 로우레벨이 트랜지스터(Q1)의 베이스에 인가되면 트랜지스서터(Q1)가 ″오프″되므로 트랜지스터(Q1)의 콜렉터와 에미터 사이에 개재된 콘덴서(C1)에는 전압이 충전된다.The vertical synchronous signal shown in FIG. 2a output from the vertical driving terminal VD is applied to the base of the transistor Q1 through the resistor R1. At this time, when the low level is applied to the base of the transistor Q1 in the vertical synchronization signal as shown in FIG. 2a, the transistor C1 is turned off, so that the capacitor C1 interposed between the collector and the emitter of the transistor Q1 is used. The voltage is charged.
여기서, 콘덴서(C1)은 충전된 전압은 Vc=1/C∫idt이다.Here, the charged voltage of the capacitor C1 is Vc = 1 / C∫idt.
반대로 트랜지스터(Q1)의 베이스에 제2a도의 파형중 하이레벨이 인가되면 트랜지스터(Q1)가 ″온″되어 콘덴서(C1)에 충전된 전압이 방전을 하게 되므로 트랜지스터(Q1)의 콜렉터에서는 콘덴서(C1)의 충방전에 따라 제2b도와 같은 톱니파 신호가 수직동기신호의 주기에 따라 발생하여 연산증폭기(OP1)의 비반전단자(+)에 인가된다.On the contrary, when the high level of the waveform of FIG. 2a is applied to the base of the transistor Q1, the transistor Q1 is turned on and the voltage charged in the capacitor C1 is discharged. Therefore, the collector of the transistor Q1 has a capacitor C1. As shown in FIG. 2B, a sawtooth wave signal is generated according to the period of the vertical synchronization signal and applied to the non-inverting terminal (+) of the operational amplifier OP1.
한편, 수직동기신호가 저항(R4)을 통하여 트랜지스터(Q2)의 베이스에 인가되어 반전 증폭된 수직동기신호가 단안정 멀티바이브레이터(MUT)의 ″바″단자를 통해 비교기(COM1)의 반전단자(-)에 인가된다.On the other hand, the vertical synchronizing signal is applied to the base of the transistor Q2 through the resistor R4, and the inverted and amplified vertical synchronizing signal is inverted terminal of the comparator COM1 through the ″ bar ″ terminal of the monostable multivibrator MUT. Is applied to-).
이때, 비교기(COM1)의 반전단자(-)에 인가되는 반전된 수직동기신호가 로우레벨이면 플립플롭(FF)의 세트단(S)에 하이레벨이 되어 인버터(I)를 통해 ″다″단자로 출력된다.At this time, if the inverted vertical synchronizing signal applied to the inverting terminal (-) of the comparator COM1 is at the low level, the set terminal S of the flip-flop FF is at a high level, and is ″ multi ″ terminal through the inverter I. Is output.
단안정 멀티바이브레이터(MUT)의 ″다″단자로 출력되는 하이레벨은 가변저항(VR3)을 통해 연산증폭기(OP1)의 반전단자(-)에 인가되므로 연산증폭기(OP1)의 출력은 로우레벨이 되어 트랜지스터(Q4)를 ″온″시킨다.Since the high level output to the ″ multi ″ terminal of the monostable multivibrator MUT is applied to the inverting terminal (−) of the operational amplifier OP1 through the variable resistor VR3, the output of the operational amplifier OP1 has a low level. The transistor Q4 is turned on.
트랜지스터(Q4)가 ″온″되므로 트랜지스터(Q3)의 에미터로 수직편향요크가 출력된다.Since transistor Q4 is "on", a vertical deflection yoke is output to the emitter of transistor Q3.
비교기(COM1)의 반전단자(-)에 하이레벨이 인가되면 플립플롭(FF)의 세트단자(S)는 로우레벨로 된다.When a high level is applied to the inverting terminal (-) of the comparator COM1, the set terminal S of the flip-flop FF is at a low level.
그러나, 콘덴서(C3)가 충분히 방전되면 단안정 멀티바이브레이터(MUT)의 ″사″단자가 로우레벨이 되므로 플립플롭(FF)의 리세트단자(R)가 하이레벨이 되어 리세트 시킨다.However, if the capacitor C3 is sufficiently discharged, the " four " terminal of the monostable multivibrator MUT is at a low level, and the reset terminal R of the flip-flop FF is at a high level and reset.
플립플롭(FF)이 리세트되면 그 출력(Q)이 로우레벨로 되어 연산증폭기(OP1)의 반전단자(-)에 인가된다.When the flip-flop FF is reset, its output Q is brought low and is applied to the inverting terminal (−) of the operational amplifier OP1.
따라서, 연산증폭기(OP1)의 반전단자(-)에 인가되는 파형이 하이레벨에서로우레벨로 변화되므로 연산증폭기(OP1)의 출력이 급격히 증가되어 트랜지스터(Q4)가 ″오프″된다.Therefore, since the waveform applied to the inverting terminal (-) of the operational amplifier OP1 changes from a high level to a low level, the output of the operational amplifier OP1 is rapidly increased, and the transistor Q4 is ″ off ″.
그러므로, 트랜지스터(Q3)의 에미터로 출력되는 수직편향요크(VDY)가 제2도(C)와 같은 파형이 출력되어 옵티칼 블랙의 인접지역을 스키프(SKIP)하게 된다.Therefore, the vertical deflection yoke VDY output to the emitter of the transistor Q3 outputs a waveform as shown in FIG. 2C to skip the adjacent area of the optical black.
즉, 펄스폭 지연부(3)를 통과하여 지연된 펄스를 수직동기신호 동안 톱니파가 발생되는 펄스와 합성하여 옵티칼 블랙 인접지역을 스키프하도록 한다.That is, the pulses delayed through the pulse width delay unit 3 are combined with pulses in which sawtooth waves are generated during the vertical synchronization signal, so that the optical black adjacent region is skipped.
제2도 ″a″는 수직 귀선지역을 나타낸 것이고, ″b″는 옵티칼 블랙의 스캐닝(Scannong)하는 시간이며, ″c″는 적은 시간에 전류가 급격히 증가하여 크롬의 오염지역을 스키프하는 것이다.Figure 2 ″ a ″ shows the vertical blanking area, ″ b ″ is the time to scan the optical black, and ″ c ″ is the amount of current rapidly increasing in a short time to skip the chromium contaminated area. .
상기한 바와같이 본 고안에 의하면, 크롬(Cr)으로 오염된 지역을 스키프(SKIP)하여 편향함으로써 보다 깨끗한 비데오 신호를 얻을 수 있는 잇점이 있다.As described above, according to the present invention, there is an advantage that a clearer video signal can be obtained by skipping and deflecting an area contaminated with chromium (Cr).
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019860010922U KR910000543Y1 (en) | 1986-07-25 | 1986-07-25 | Skip circuit for image tube |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019860010922U KR910000543Y1 (en) | 1986-07-25 | 1986-07-25 | Skip circuit for image tube |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR880003625U KR880003625U (en) | 1988-04-14 |
| KR910000543Y1 true KR910000543Y1 (en) | 1991-01-25 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019860010922U KR910000543Y1 (en) | 1986-07-25 | 1986-07-25 | Skip circuit for image tube |
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| Country | Link |
|---|---|
| KR (1) | KR910000543Y1 (en) |
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1986
- 1986-07-25 KR KR2019860010922U patent/KR910000543Y1/en not_active IP Right Cessation
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| Publication number | Publication date |
|---|---|
| KR880003625U (en) | 1988-04-14 |
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