KR890015127A - 프로그램 제어장치 - Google Patents
프로그램 제어장치 Download PDFInfo
- Publication number
- KR890015127A KR890015127A KR1019890002740A KR890002740A KR890015127A KR 890015127 A KR890015127 A KR 890015127A KR 1019890002740 A KR1019890002740 A KR 1019890002740A KR 890002740 A KR890002740 A KR 890002740A KR 890015127 A KR890015127 A KR 890015127A
- Authority
- KR
- South Korea
- Prior art keywords
- storage means
- decoding
- program control
- sequence
- storage
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
- G06F11/3636—Software debugging by tracing the execution of the program
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
- G06F11/3466—Performance evaluation by tracing or monitoring
- G06F11/348—Circuit details, i.e. tracer hardware
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
- G06F11/3409—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment
- G06F11/3419—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment by assessing time
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
- G06F2201/88—Monitoring involving counting
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
- Computer And Data Communications (AREA)
Abstract
내용 없음.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명이 적용된 LAN용 프로세서와 그것에 결합되는 단말장치의 1실시예를 도시한 블록도.
제2도는 상기 자기진단회로 STC의 구체적인 구성과 그것에 연관된 중요한 회로를 도시한 블록도.
제3도는 마이크로 프로그램 ROM과 그 어드레스 발생부의 1실시예를 도시한 불럭도.
Claims (5)
- 지시된 설정조건에 따라 그것에 대응한 각종 제어동작을 행하는 시퀀스 제어신호를 형성하는 프로그램기억용 제1의 기억수단과 특정한 동작모드의 지정에 의해 동작상태로 되고 설정조건에 대응한 정보 및 그 동작 시퀀스로 낭비된 시간정보를 순차로 기억하는 제2의 기억수단을 포함하는 프로그램 제어장치.
- 특허청구의 범위 제1항에 있어서, 상기 제1의 기억수단은 지시된 설정조건에 대응한 정보를 디코드하는 드코드수단과 상기 디코드수단의 출력신호에 의해 설정된 설정조건에 대응한 일련의 시퀀스 제어신호를 형성하는 선두 어드레스가 지정되는 마이크로프로그램 기억수단으로 구성되는 프로그램 제어장치.
- 특허청구의 범위 제2항에 있어서, 상기 제2의 기억수단은 FIFO 메모리인 프로그램 제어장치.
- 특허청구의 범위 제2항에 있어서, 상기 디코드수단 및 마이크로프로그램 기억수단은 ROM으로 구성되는 프로그램 제어장치.
- 특허청구의 범위 제2항에 있어서, 상기 디코드수단 및 마이크로프로그램 기억수단 중 적어도 한쪽은 RAM으로 구성되는 프로그램 제어장치.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63-60970 | 1988-03-15 | ||
JP63060970A JP2678283B2 (ja) | 1988-03-15 | 1988-03-15 | データ通信制御装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR890015127A true KR890015127A (ko) | 1989-10-28 |
KR970007764B1 KR970007764B1 (ko) | 1997-05-16 |
Family
ID=13157784
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019890002740A KR970007764B1 (ko) | 1988-03-15 | 1989-03-06 | 프로그램 제어장치 |
Country Status (3)
Country | Link |
---|---|
US (1) | US5058114A (ko) |
JP (1) | JP2678283B2 (ko) |
KR (1) | KR970007764B1 (ko) |
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JP2789900B2 (ja) * | 1991-11-22 | 1998-08-27 | 日本電気株式会社 | 状態履歴記憶装置 |
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JP3210466B2 (ja) * | 1993-02-25 | 2001-09-17 | 株式会社リコー | Cpuコア、該cpuコアを有するasic、及び該asicを備えたエミュレーションシステム |
DE69415600T2 (de) * | 1993-07-28 | 1999-07-15 | Koninklijke Philips Electronics N.V., Eindhoven | Mikrokontroller mit hardwaremässiger Fehlerbeseitigungsunterstützung nach dem Boundary-Scanverfahren |
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US5764885A (en) * | 1994-12-19 | 1998-06-09 | Digital Equipment Corporation | Apparatus and method for tracing data flows in high-speed computer systems |
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KR100367054B1 (ko) * | 2000-04-15 | 2003-01-09 | 인벤테크 베스타 컴퍼니 | 하드웨어에 기초한 순차 마스크롬 어댑터 |
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KR101358750B1 (ko) * | 2007-01-22 | 2014-02-06 | 삼성전자주식회사 | 관계형 데이터베이스를 이용한 프로그램 트레이스 방법 |
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JP5302050B2 (ja) * | 2009-03-04 | 2013-10-02 | 富士通株式会社 | 障害解析のためのトレース装置およびトレース方法 |
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JPH0619742B2 (ja) * | 1986-07-07 | 1994-03-16 | 松下電送株式会社 | プロトコル実行装置 |
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-
1988
- 1988-03-15 JP JP63060970A patent/JP2678283B2/ja not_active Expired - Fee Related
-
1989
- 1989-03-06 KR KR1019890002740A patent/KR970007764B1/ko not_active IP Right Cessation
- 1989-03-14 US US07/324,214 patent/US5058114A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH01233634A (ja) | 1989-09-19 |
US5058114A (en) | 1991-10-15 |
JP2678283B2 (ja) | 1997-11-17 |
KR970007764B1 (ko) | 1997-05-16 |
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