KR890015127A - 프로그램 제어장치 - Google Patents

프로그램 제어장치 Download PDF

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Publication number
KR890015127A
KR890015127A KR1019890002740A KR890002740A KR890015127A KR 890015127 A KR890015127 A KR 890015127A KR 1019890002740 A KR1019890002740 A KR 1019890002740A KR 890002740 A KR890002740 A KR 890002740A KR 890015127 A KR890015127 A KR 890015127A
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KR
South Korea
Prior art keywords
storage means
decoding
program control
sequence
storage
Prior art date
Application number
KR1019890002740A
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English (en)
Other versions
KR970007764B1 (ko
Inventor
시게오 구보끼
노리히꼬 스기모또
슌지 이나다
마사히로 우에노
다께시 하라까와
가즈히사 이나다
도시히꼬 도미나가
야스시 나까무라
Original Assignee
미다 가쓰시게
가부시끼가이샤 히다찌세이사꾸쇼
야마자끼 세이지
히다찌엔지니어링 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 미다 가쓰시게, 가부시끼가이샤 히다찌세이사꾸쇼, 야마자끼 세이지, 히다찌엔지니어링 가부시끼가이샤 filed Critical 미다 가쓰시게
Publication of KR890015127A publication Critical patent/KR890015127A/ko
Application granted granted Critical
Publication of KR970007764B1 publication Critical patent/KR970007764B1/ko

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/362—Software debugging
    • G06F11/3636—Software debugging by tracing the execution of the program
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3466—Performance evaluation by tracing or monitoring
    • G06F11/348—Circuit details, i.e. tracer hardware
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3409—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment
    • G06F11/3419—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment by assessing time
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/88—Monitoring involving counting

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
  • Computer And Data Communications (AREA)

Abstract

내용 없음.

Description

프로그램 제어장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명이 적용된 LAN용 프로세서와 그것에 결합되는 단말장치의 1실시예를 도시한 블록도.
제2도는 상기 자기진단회로 STC의 구체적인 구성과 그것에 연관된 중요한 회로를 도시한 블록도.
제3도는 마이크로 프로그램 ROM과 그 어드레스 발생부의 1실시예를 도시한 불럭도.

Claims (5)

  1. 지시된 설정조건에 따라 그것에 대응한 각종 제어동작을 행하는 시퀀스 제어신호를 형성하는 프로그램기억용 제1의 기억수단과 특정한 동작모드의 지정에 의해 동작상태로 되고 설정조건에 대응한 정보 및 그 동작 시퀀스로 낭비된 시간정보를 순차로 기억하는 제2의 기억수단을 포함하는 프로그램 제어장치.
  2. 특허청구의 범위 제1항에 있어서, 상기 제1의 기억수단은 지시된 설정조건에 대응한 정보를 디코드하는 드코드수단과 상기 디코드수단의 출력신호에 의해 설정된 설정조건에 대응한 일련의 시퀀스 제어신호를 형성하는 선두 어드레스가 지정되는 마이크로프로그램 기억수단으로 구성되는 프로그램 제어장치.
  3. 특허청구의 범위 제2항에 있어서, 상기 제2의 기억수단은 FIFO 메모리인 프로그램 제어장치.
  4. 특허청구의 범위 제2항에 있어서, 상기 디코드수단 및 마이크로프로그램 기억수단은 ROM으로 구성되는 프로그램 제어장치.
  5. 특허청구의 범위 제2항에 있어서, 상기 디코드수단 및 마이크로프로그램 기억수단 중 적어도 한쪽은 RAM으로 구성되는 프로그램 제어장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019890002740A 1988-03-15 1989-03-06 프로그램 제어장치 KR970007764B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP63-60970 1988-03-15
JP63060970A JP2678283B2 (ja) 1988-03-15 1988-03-15 データ通信制御装置

Publications (2)

Publication Number Publication Date
KR890015127A true KR890015127A (ko) 1989-10-28
KR970007764B1 KR970007764B1 (ko) 1997-05-16

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890002740A KR970007764B1 (ko) 1988-03-15 1989-03-06 프로그램 제어장치

Country Status (3)

Country Link
US (1) US5058114A (ko)
JP (1) JP2678283B2 (ko)
KR (1) KR970007764B1 (ko)

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Also Published As

Publication number Publication date
JPH01233634A (ja) 1989-09-19
US5058114A (en) 1991-10-15
JP2678283B2 (ja) 1997-11-17
KR970007764B1 (ko) 1997-05-16

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