KR890011067A - 반도체장치 - Google Patents
반도체장치 Download PDFInfo
- Publication number
- KR890011067A KR890011067A KR1019880011136A KR880011136A KR890011067A KR 890011067 A KR890011067 A KR 890011067A KR 1019880011136 A KR1019880011136 A KR 1019880011136A KR 880011136 A KR880011136 A KR 880011136A KR 890011067 A KR890011067 A KR 890011067A
- Authority
- KR
- South Korea
- Prior art keywords
- semiconductor device
- wider
- end portion
- lead
- insulating sheet
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49572—Lead-frames or other flat leads consisting of thin flexible metallic tape with or without a film carrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1 도는 본 발명에 따른 반도체장치에 사용되는 리드프레임 중앙부의 확대평면도.
제 2 도는 제 1 도에 도시된 리드프레임의 내부리드선 끝부분을 확대하여 나타낸 확대평면도.
제 3 도는 내부리드선의 끝부분에 설치하여 접착강도를 증가시키기 위한 구조를 나타낸 단면도.
* 도면의 주요부분에 대한 부호의 설명
1, 11a, 15a : 내리드 1a : 폭이 넓은 선단부
1b : 선단부 1c:개구부
1d : 부분삭각 부 10 : 반도체장치
11 : 프레임 11b : 외부리드
11c : 베드부 11d : 타이바(tie bar)
12,12' : 펠렛 13 : 와이어
14 : 수지 15 : 리드
16,16' : 절연성 시이트
Claims (4)
- 리드프레임의 펠렛설치부에 방사상으로 배치된 내부리드선단부를 점착고정시키도록 배치되고 반도체펠렛이 그 위에 탑재되도록 된 절연성 시이트를 구비한 반도체장치에 있어서, 적어도 하나 걸러 상기 내부리드의 선단부에 다른 내부리드선단부의 폭보다도 넓은 광폭부(1a)를 형성시키고; 이 광폭부(1a)를 상기 다른 내부리드선단부 보다도 리드프레임의 중심쪽에 위치시키며, 상기 광폭부(1a)내에 개구부(1c)를 형성시켜서 구성된 것을 특징으로 하는 반도체 장치.
- 제 1 항에 있어서, 상기 절연성 시이트가 폴리이미드로 구성된 것을 특징으로 하는 반도체장치.
- 리드프레임의 펠렛설치부에 방사상으로 배치된 내부리드선단부를 점착고정시키도록 배치되고 반도체펠렛이 그위에 탑재되도록 된 절연성 시이트를 구비한 반도체장치에 있어서, 적어도 하나 걸러 상기 내부리드의 선단부에 다른 내부리드선단부의 폭보다도 넓은 광폭부(1a)를 형성시키고, 이 광폭부(1a)를 상기 다른 내부리드 선단부 보다도 리드프레임의 중심쪽에 위치시키며, 상기 광폭부(1a)에 부분식각부(1d)를 형성시켜서 구성된 것을 특징으로 하는 반도체 장치.
- 제 3 항에 있어서, 상기 절연성 시이트가 폴리이미드로 구성된 것을 특징으로 하는 반도체장치.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62-319773 | 1987-12-17 | ||
JP62319773A JPH01161743A (ja) | 1987-12-17 | 1987-12-17 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR890011067A true KR890011067A (ko) | 1989-08-12 |
KR910003543B1 KR910003543B1 (ko) | 1991-06-04 |
Family
ID=18114019
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019880011136A KR910003543B1 (ko) | 1987-12-17 | 1988-08-31 | 반도체장치 |
Country Status (5)
Country | Link |
---|---|
US (1) | US4949160A (ko) |
EP (1) | EP0320997B1 (ko) |
JP (1) | JPH01161743A (ko) |
KR (1) | KR910003543B1 (ko) |
DE (1) | DE3873500T2 (ko) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0405330A3 (en) * | 1989-06-29 | 1992-05-06 | Motorola, Inc. | Flagless leadframe, package and method |
JPH0395661U (ko) * | 1990-01-12 | 1991-09-30 | ||
US5168345A (en) * | 1990-08-15 | 1992-12-01 | Lsi Logic Corporation | Semiconductor device having a universal die size inner lead layout |
US5177032A (en) * | 1990-10-24 | 1993-01-05 | Micron Technology, Inc. | Method for attaching a semiconductor die to a leadframe using a thermoplastic covered carrier tape |
US5140404A (en) * | 1990-10-24 | 1992-08-18 | Micron Technology, Inc. | Semiconductor device manufactured by a method for attaching a semiconductor die to a leadframe using a thermoplastic covered carrier tape |
EP0588481A1 (en) * | 1992-08-17 | 1994-03-23 | American Microsystems, Incorporated | Bond pad layouts for integrated circuit semiconductor dies and forming methods |
TW276357B (ko) * | 1993-03-22 | 1996-05-21 | Motorola Inc | |
US5714792A (en) * | 1994-09-30 | 1998-02-03 | Motorola, Inc. | Semiconductor device having a reduced die support area and method for making the same |
JPH09199549A (ja) * | 1996-01-22 | 1997-07-31 | Denso Corp | ワイヤボンディング方法 |
JPH09260575A (ja) * | 1996-03-22 | 1997-10-03 | Mitsubishi Electric Corp | 半導体装置及びリードフレーム |
US7598599B2 (en) * | 2006-03-09 | 2009-10-06 | Stats Chippac Ltd. | Semiconductor package system with substrate having different bondable heights at lead finger tips |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5640265A (en) * | 1979-09-11 | 1981-04-16 | Nec Corp | Lead frame for semiconductor device |
JPS59129451A (ja) * | 1983-01-14 | 1984-07-25 | Nec Corp | リ−ドフレ−ム |
JPS60106158A (ja) * | 1983-11-14 | 1985-06-11 | Toshiba Corp | 半導体装置 |
JPS621239A (ja) * | 1985-06-26 | 1987-01-07 | Toshiba Corp | 半導体装置 |
US4684975A (en) * | 1985-12-16 | 1987-08-04 | National Semiconductor Corporation | Molded semiconductor package having improved heat dissipation |
US4721993A (en) * | 1986-01-31 | 1988-01-26 | Olin Corporation | Interconnect tape for use in tape automated bonding |
-
1987
- 1987-12-17 JP JP62319773A patent/JPH01161743A/ja active Granted
-
1988
- 1988-08-31 KR KR1019880011136A patent/KR910003543B1/ko not_active IP Right Cessation
- 1988-12-16 US US07/285,021 patent/US4949160A/en not_active Expired - Lifetime
- 1988-12-19 DE DE8888121234T patent/DE3873500T2/de not_active Expired - Fee Related
- 1988-12-19 EP EP88121234A patent/EP0320997B1/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US4949160A (en) | 1990-08-14 |
DE3873500T2 (de) | 1993-02-11 |
JPH01161743A (ja) | 1989-06-26 |
KR910003543B1 (ko) | 1991-06-04 |
EP0320997A3 (en) | 1989-10-18 |
DE3873500D1 (de) | 1992-09-10 |
EP0320997A2 (en) | 1989-06-21 |
EP0320997B1 (en) | 1992-08-05 |
JPH0381308B2 (ko) | 1991-12-27 |
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A201 | Request for examination | ||
G160 | Decision to publish patent application | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20030530 Year of fee payment: 13 |
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LAPS | Lapse due to unpaid annual fee |