KR890007181A - Artbus configuration method of personal computer process control system - Google Patents

Artbus configuration method of personal computer process control system Download PDF

Info

Publication number
KR890007181A
KR890007181A KR870011425A KR870011425A KR890007181A KR 890007181 A KR890007181 A KR 890007181A KR 870011425 A KR870011425 A KR 870011425A KR 870011425 A KR870011425 A KR 870011425A KR 890007181 A KR890007181 A KR 890007181A
Authority
KR
South Korea
Prior art keywords
connector
personal computer
process control
artbus
control system
Prior art date
Application number
KR870011425A
Other languages
Korean (ko)
Other versions
KR900007098B1 (en
Inventor
조삼현
Original Assignee
경상현
재단법인 한국전자통신연구소
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 경상현, 재단법인 한국전자통신연구소 filed Critical 경상현
Priority to KR1019870011425A priority Critical patent/KR900007098B1/en
Publication of KR890007181A publication Critical patent/KR890007181A/en
Application granted granted Critical
Publication of KR900007098B1 publication Critical patent/KR900007098B1/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer And Data Communications (AREA)
  • Control By Computers (AREA)

Abstract

내용 없음No content

Description

퍼스컴 공정제어 시스템의 아트버스 구성방법Artbus configuration method of personal computer process control system

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제 3 도는 본 발명의 퍼스컴 공정제어 시스템의 입출력신호 연결상태를 나타낸 간접외부 블럭도.3 is an indirect external block diagram showing an input / output signal connection state of a personal computer process control system according to the present invention.

Claims (2)

퍼스컴 실장된 확장용슬롯은 입출력 스캔 내장용 제어보드(2)와 입출력카드 (Ⅰ-ocardo~Ⅰ-ocard n-1)접속되는 콘넥터(Connector) 및 입출력카드콘넥터 (Connector o~Connector n-1), PcB(1)로 구성된 아트버스(Art-Bus)와 상기 공정제어용보드(2)로 입출력카드(Ⅰ-ocardo~Ⅰ-ocard n-1)를 제어할 수 있게 함으로써 입출력처리능력을 향상시킬 수 있도록 한 것을 특징으로 하는 퍼스컴의 공정 제어시스템의 아트버스 구성방법.The expansion slot equipped with the personal computer is equipped with a connector (I-ocardo ~ I-ocard n-1) and an I / O card connector (Connector o ~ Connector n-1) connected to the control board (2) for I / O scan built-in. And I / O cards (I-ocardo ~ I-ocard n-1) can be controlled by the Art-Bus composed of PcB (1) and the process control board (2), thereby improving the input / output processing capability. Artbus configuration method of the process control system of the personal computer characterized in that. 제 1 항에 있어서, 상기 아트버스(Art-Bus)에 데이터라인(D0~D7)어드레이라인 (INT0~INT7)제어라인(RD WRRESET)전원단자라인(+5, +15, -15V)를 가진 입출력카드 (I-ocareo~I-ocard n-1)를 PcB(1)상에 병렬로 형성된 입출력카드콘넥터(Connector 0~Connector n-1)에 병렬로 탑재하여 데이타의 처리속도를 향상시킬 수 있도록 한 것을 특징으로 하는 퍼스컴 공정제어 시스템의 아트버스 구성방법.The power supply line (+5, +15,-) of the data line (D 0 ~ D 7 ) address line (INT 0 ~ INT 7 ) control line (RD WRRESET) to the Art-Bus. Input / output card (I-ocareo ~ I-ocard n-1) with 15V) is installed in parallel on the input / output card connector (Connector 0 ~ Connector n-1) formed in parallel on PcB (1) to improve the data processing speed. Artbus configuration method of a personal computer process control system, characterized in that to improve. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019870011425A 1987-10-14 1987-10-14 Art-bus component for sequence control system KR900007098B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019870011425A KR900007098B1 (en) 1987-10-14 1987-10-14 Art-bus component for sequence control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019870011425A KR900007098B1 (en) 1987-10-14 1987-10-14 Art-bus component for sequence control system

Publications (2)

Publication Number Publication Date
KR890007181A true KR890007181A (en) 1989-06-19
KR900007098B1 KR900007098B1 (en) 1990-09-28

Family

ID=19265189

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019870011425A KR900007098B1 (en) 1987-10-14 1987-10-14 Art-bus component for sequence control system

Country Status (1)

Country Link
KR (1) KR900007098B1 (en)

Also Published As

Publication number Publication date
KR900007098B1 (en) 1990-09-28

Similar Documents

Publication Publication Date Title
KR880008228A (en) Display
KR890007181A (en) Artbus configuration method of personal computer process control system
KR920006870A (en) Data processing device
KR860002053A (en) Electronic dictionary circuit
KR890007172A (en) Personal computer input / output scanning device
KR890008673A (en) Data processing device using microcomputer
KR910006829A (en) CPU standby time control method and system to connect external I / O controller to computer
JPS57185574A (en) Character processor
JPS57185559A (en) Small-sized electronic calculator with rpogram
JPS5663631A (en) Chinese character input device
KR920010404A (en) 8-Bit 16-Bit Conversion Bus Interface Logic in PC Systems
KR910014786A (en) Simultaneous 3-channel access method and device of memory PCB
JPS5470735A (en) Electronic computer
KR970049517A (en) Data Transfer Method of ISDN Board in High Speed Medium Computers
KR850005652A (en) Electronic sign board
KR970049332A (en) PC keyboard and mouse connector
KR920006846A (en) Emulation Circuit of CGA Board
KR890005612A (en) Memory bank select circuit
KR920015200A (en) Memory modules
KR910008724A (en) Fast access device in cashew memory
KR910012919A (en) Main CPU Supervisor
KR860009346A (en) Data Transmission Method, Timing Control, and Korean Hard Scroll Method in Computer
KR870011547A (en) Data signal processor using 8-bit and 16-bit central processing unit
JPS6426950A (en) Write protecting system for memory
KR880008177A (en) Control circuit of local area network

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 19970605

Year of fee payment: 8

LAPS Lapse due to unpaid annual fee