KR880010494A - 매스터 슬라이스형 집적회로 - Google Patents

매스터 슬라이스형 집적회로 Download PDF

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Publication number
KR880010494A
KR880010494A KR1019880001326A KR880001326A KR880010494A KR 880010494 A KR880010494 A KR 880010494A KR 1019880001326 A KR1019880001326 A KR 1019880001326A KR 880001326 A KR880001326 A KR 880001326A KR 880010494 A KR880010494 A KR 880010494A
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input
output
integrated circuit
master slice
paired
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KR1019880001326A
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KR910000023B1 (ko
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마사유끼 나가누마
요시유끼 스에히로
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야마모도 다꾸마
후지쓰 가부시끼가이샤
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Publication of KR880010494A publication Critical patent/KR880010494A/ko
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Publication of KR910000023B1 publication Critical patent/KR910000023B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11898—Input and output buffer/driver structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

내용 없음

Description

매스터 슬라이스형 집적회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명에 의한 매스터 슬라이스형 집적회로의 일실시예의 입출력 셀들의 요부 평면도.
제3도는 본 발명에 의한 실시예의 구조 평면도.

Claims (13)

  1. 반도체 칩상의 주변 영역에 배설되고, 외부회로에 각각 연결하기 위한 패드들, 입력신호들을 반송하기 위한 입력결선 라인들을 각각이 수용하고 있는 입력배선 영역들 및 출력버퍼들을 각각이 형성하기 위한 출력회로 영역들을 포함하고 있는 복수의 입출력 셀드롸, 입출력 셀들의 배설에 의하여 둘러쌓인 칩상의 영역내에 배설된 복수의 기본 셀들을 포함하고, 2개의 인접 입출력 셀들은 서로 쌍을 이루고 쌍으로 된 입출력 셀들의 출력회로 영역들은 이 쌍의 경계선 근방에 배설되고 이 쌍의 입력 배선영역들은 다른 쌍들에 대한 경계선 근방에 배설되고 결선루트를 변경함으로써 각족 회로를 제공하는 것을 특징으로 하는 매스터 슬라이스형 집적회로.
  2. 제1항에 있어서, 쌍으로 된 입출력 셀들은 반사관계를 갖고 쌍으로 된 출력회로 영역들과 입력배선영역들이 경계선에 대해서 서로 반대 방향으로 대칭으로 위치되어 있는 것을 특징으로 하는 매스터 슬라이스형 집적회로.
  3. 제1항에 있어서, 각 출력회로 영역이 n-채널 금속산화물 반도체 트랜지스터와 p-채널 금속산화물 반도체 영역을 형성하는 영역을 포함하는 것을 특징으로 하는 매스터 슬라이스형 집적회로.
  4. 제3항에 있어서, 쌍으로 된 입출력 셀들의 n-채널 및 p-채널 금속산화물을 반도체 영역들이 각 전원영역들을 거쳐 서로 가까이 위치되는 것을 특징으로 하는 매스터 슬라이스형 집적회로.
  5. 제1항에 있어서, 신호 전송을 위한 결선라인은 제1금속화층으로 형성되고, 전력을 칩내에 구성된 회로들에 공급하기 위한 전원라인은 제2금속화층으로 형성되는 것을 특징으로 하는 매스터 슬라이스형 집적회로.
  6. 제1항에 있어서, 입출력 셀들의 입정쌍이 서로 가까이 위치되는 것을 특징으로 하는 매스터 슬라이스형 집적회로.
  7. 제1항에 있어서, 입출력 셀들의 인접쌍들은 소정의 거리를 띄워 위치하는 것을 특징으로 하는 매스터 슬라이스형 집적회로.
  8. 제1항에 있어서, 매스터 슬라이스형 집적회로의 각 입출력 셀들이 기본 셀들로 구성된 입력버퍼를 정전방전으로부터 보호하는 기능을 갖는 보호회로를 형성하기 위한 입력보호 회로 영역을 더 포함하는 매스터 슬라이스형 집적회로.
  9. 제8항에 있어서, 쌍으로 된 입출력 셀들이 쌍으로 된 입출력셀의 패드로부터 입력보호 회로 영역과 입력배선 영역을 거쳐서 입력버퍼로 연설되는 제1배선라인과, 쌍으로 된 기타 입출력 셀의 패드를 입출력 셀들의 쌍의 n-채널 및 p-채널 MOS 트랜지스터 영역에 연결하는 제2결선라인을 포함하는 것을 특징으로 하는 매스터 슬라이스형 집적회로.
  10. 제8항에 있어서, 쌍으로 된 입출력 셀들은 쌍으로 된 하나의 입출력 셀의 패드를 입력보호 영역과 입력배선 영역을 거쳐서 입력버퍼로 연결하는 제1결선라인, 상기 쌍으로 된 하나의 입출력 셀의 패드를 쌍으로 된 n-채널 및 p-채널 MOS 트랜지스터에 결합시키는 제2결선라인을 포함하는 것을 특징으로 하는 매스터 슬라이스형 집적회로.
  11. 제3항에 있어서, 출력버퍼가 쌍으로 된 n-채널 및 p-채널 금속산화물 반도체 트랜지스터들을 포함하는 인버터인 것을 특징으로 하는 매스터 슬라이스형 집적회로.
  12. 제3항에 있어서, 출력버퍼가 병렬로 연결되고, 그 각각이 쌍으로 된 n-채널 p-채널 금속산화물 반도체 트랜지스터들인 것을 특징으로 하는 매스터 슬라이스형 집적회로.
  13. 제1항에 있어서, 입력보호 회로 영역이 입력단자, 정의 전원단자에 연결된 캐소드와 부의 전원단자에 연결된 애노드를 갖는 제1다이오드, 입력단자에 연결되 캐소드와 부위 전원단자에 연결되 애노드를 갖는 제2다이오드, 입력단자에 연결된 하나의 단을 갖는 저항 및 저항기의 다른 단에 연결된 출력단자를 포함하는 것을 특징으로 하는 매스터 슬라이스형 집적회로.
    ※참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019880001326A 1987-02-13 1988-02-12 매스터 슬라이스형 집적회로 KR910000023B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP62-031782 1987-02-13
JP62-31782 1987-02-13
JP62031782A JPH06105757B2 (ja) 1987-02-13 1987-02-13 マスタ・スライス型半導体集積回路

Publications (2)

Publication Number Publication Date
KR880010494A true KR880010494A (ko) 1988-10-10
KR910000023B1 KR910000023B1 (ko) 1991-01-19

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KR1019880001326A KR910000023B1 (ko) 1987-02-13 1988-02-12 매스터 슬라이스형 집적회로

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US (1) US4825107A (ko)
EP (1) EP0278857B1 (ko)
JP (1) JPH06105757B2 (ko)
KR (1) KR910000023B1 (ko)
DE (1) DE3851347D1 (ko)

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JP2594988B2 (ja) * 1987-11-27 1997-03-26 株式会社日立製作所 半導体集積回路装置の動作電位供給配線の配線設計方法
JPH01251738A (ja) * 1988-03-31 1989-10-06 Toshiba Corp スタンダードセル
JPH01289138A (ja) * 1988-05-16 1989-11-21 Toshiba Corp マスタースライス型半導体集積回路
US5162893A (en) * 1988-05-23 1992-11-10 Fujitsu Limited Semiconductor integrated circuit device with an enlarged internal logic circuit area
US4990802A (en) * 1988-11-22 1991-02-05 At&T Bell Laboratories ESD protection for output buffers
US4912348A (en) * 1988-12-09 1990-03-27 Idaho Research Foundation Method for designing pass transistor asynchronous sequential circuits
US4975758A (en) * 1989-06-02 1990-12-04 Ncr Corporation Gate isolated I.O cell architecture for diverse pad and drive configurations
JPH0430570A (ja) * 1990-05-28 1992-02-03 Sanyo Electric Co Ltd 半導体集積回路
US5341310A (en) * 1991-12-17 1994-08-23 International Business Machines Corporation Wiring layout design method and system for integrated circuits
US5367187A (en) * 1992-12-22 1994-11-22 Quality Semiconductor, Inc. Master slice gate array integrated circuits with basic cells adaptable for both input/output and logic functions
US5424589A (en) * 1993-02-12 1995-06-13 The Board Of Trustees Of The Leland Stanford Junior University Electrically programmable inter-chip interconnect architecture
JPH06326194A (ja) * 1993-05-17 1994-11-25 Mitsubishi Electric Corp 半導体集積回路装置
US5469473A (en) * 1994-04-15 1995-11-21 Texas Instruments Incorporated Transceiver circuit with transition detection
JP3487989B2 (ja) * 1995-10-31 2004-01-19 富士通株式会社 半導体装置
US5796638A (en) * 1996-06-24 1998-08-18 The Board Of Trustees Of The University Of Illinois Methods, apparatus and computer program products for synthesizing integrated circuits with electrostatic discharge capability and connecting ground rules faults therein
US5757041A (en) * 1996-09-11 1998-05-26 Northrop Grumman Corporation Adaptable MMIC array
US6979908B1 (en) * 2000-01-11 2005-12-27 Texas Instruments Incorporated Input/output architecture for integrated circuits with efficient positioning of integrated circuit elements
US6550047B1 (en) * 2000-10-02 2003-04-15 Artisan Components, Inc. Semiconductor chip input/output cell design and automated generation methods
US7430730B2 (en) * 2004-08-02 2008-09-30 Lsi Corporation Disabling unused IO resources in platform-based integrated circuits
JP2011242541A (ja) * 2010-05-17 2011-12-01 Panasonic Corp 半導体集積回路装置、および標準セルの端子構造
US20140312475A1 (en) * 2013-04-19 2014-10-23 Lsi Corporation Die reuse in electrical circuits

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JPS6012751A (ja) * 1983-07-01 1985-01-23 Hitachi Ltd 半導体集積回路
JPS6027145A (ja) * 1983-07-25 1985-02-12 Hitachi Ltd 半導体集積回路装置
JPS6095935A (ja) * 1983-10-31 1985-05-29 Fujitsu Ltd ゲ−トアレイ集積回路装置
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US4725835A (en) * 1985-09-13 1988-02-16 T-Bar Incorporated Time multiplexed bus matrix switching system
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Also Published As

Publication number Publication date
KR910000023B1 (ko) 1991-01-19
DE3851347D1 (de) 1994-10-13
US4825107B1 (ko) 1992-08-18
EP0278857B1 (en) 1994-09-07
EP0278857A2 (en) 1988-08-17
JPH06105757B2 (ja) 1994-12-21
US4825107A (en) 1989-04-25
JPS63198355A (ja) 1988-08-17
EP0278857A3 (en) 1990-06-13

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