KR870004515A - 상호 접속된 다수의 집적회로 칩으로 구성된 반도체 웨이퍼 규모 집적장치 및 그 제조방법 - Google Patents
상호 접속된 다수의 집적회로 칩으로 구성된 반도체 웨이퍼 규모 집적장치 및 그 제조방법Info
- Publication number
- KR870004515A KR870004515A KR1019860008287A KR860008287A KR870004515A KR 870004515 A KR870004515 A KR 870004515A KR 1019860008287 A KR1019860008287 A KR 1019860008287A KR 860008287 A KR860008287 A KR 860008287A KR 870004515 A KR870004515 A KR 870004515A
- Authority
- KR
- South Korea
- Prior art keywords
- manufacturing
- semiconductor wafer
- circuit chips
- device composed
- wafer scale
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/2413—Connecting within a semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01018—Argon [Ar]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01042—Molybdenum [Mo]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60222593A JPS6281745A (ja) | 1985-10-05 | 1985-10-05 | ウエハ−規模のlsi半導体装置とその製造方法 |
JP60-222593 | 1985-10-05 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR870004515A true KR870004515A (ko) | 1987-05-11 |
KR900008018B1 KR900008018B1 (ko) | 1990-10-29 |
Family
ID=16784898
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019860008287A KR900008018B1 (ko) | 1985-10-05 | 1986-10-02 | 상호 접속된 다수의 집적회로 칩으로 구성된 반도체 웨이퍼 규모 집적장치 및 그 제조방법 |
Country Status (5)
Country | Link |
---|---|
US (1) | US4907062A (ko) |
EP (1) | EP0222144B1 (ko) |
JP (1) | JPS6281745A (ko) |
KR (1) | KR900008018B1 (ko) |
DE (1) | DE3684557D1 (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101329414B1 (ko) * | 2005-12-21 | 2013-11-14 | 제너럴 일렉트릭 캄파니 | 내에칭성 웨이퍼 처리 장치 및 이의 제조 방법 |
Families Citing this family (50)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR890005869A (ko) * | 1987-09-11 | 1989-05-17 | 페어차일드 세미컨덕터 코포레이션 | 회로기판의 공동에 붙박힌 액티브 디바이스를 갖는 반도체 모듈 |
US5008213A (en) * | 1988-12-09 | 1991-04-16 | The United States Of America As Represented By The Secretary Of The Air Force | Hybrid wafer scale microcircuit integration |
US4987295A (en) * | 1989-03-31 | 1991-01-22 | General Electric Company | Multichip imager with improved optical performance near the butt region |
US5075253A (en) * | 1989-04-12 | 1991-12-24 | Advanced Micro Devices, Inc. | Method of coplanar integration of semiconductor IC devices |
US5161093A (en) * | 1990-07-02 | 1992-11-03 | General Electric Company | Multiple lamination high density interconnect process and structure employing a variable crosslinking adhesive |
FR2667443A1 (fr) * | 1990-09-28 | 1992-04-03 | Thomson Csf | Procede de realisation d'un module hybride. |
US5198385A (en) * | 1991-01-11 | 1993-03-30 | Harris Corporation | Photolithographic formation of die-to-package airbridge in a semiconductor device |
JP2960560B2 (ja) | 1991-02-28 | 1999-10-06 | 株式会社日立製作所 | 超小型電子機器 |
JP3027990B2 (ja) * | 1991-03-18 | 2000-04-04 | 富士通株式会社 | 半導体装置の製造方法 |
JPH06502744A (ja) * | 1991-03-27 | 1994-03-24 | インテグレイテッド システム アセンブリース コーポレーション | マルチチップ集積回路パッケージ及びモジュール |
US5091769A (en) * | 1991-03-27 | 1992-02-25 | Eichelberger Charles W | Configuration for testing and burn-in of integrated circuit chips |
US5250843A (en) * | 1991-03-27 | 1993-10-05 | Integrated System Assemblies Corp. | Multichip integrated circuit modules |
US5498990A (en) * | 1991-11-05 | 1996-03-12 | Monolithic System Technology, Inc. | Reduced CMOS-swing clamping circuit for bus lines |
US5831467A (en) * | 1991-11-05 | 1998-11-03 | Monolithic System Technology, Inc. | Termination circuit with power-down mode for use in circuit module architecture |
DE69226150T2 (de) * | 1991-11-05 | 1999-02-18 | Hsu Fu Chieh | Redundanzarchitektur für Schaltungsmodul |
US5291066A (en) * | 1991-11-14 | 1994-03-01 | General Electric Company | Moisture-proof electrical circuit high density interconnect module and method for making same |
US5355577A (en) * | 1992-06-23 | 1994-10-18 | Cohn Michael B | Method and apparatus for the assembly of microfabricated devices |
JPH08500687A (ja) * | 1992-08-10 | 1996-01-23 | モノリシック・システム・テクノロジー・インコーポレイテッド | ウェハ規模の集積化のためのフォルトトレラントな高速度のバス装置及びバスインタフェース |
US5324687A (en) * | 1992-10-16 | 1994-06-28 | General Electric Company | Method for thinning of integrated circuit chips for lightweight packaged electronic systems |
US5366906A (en) * | 1992-10-16 | 1994-11-22 | Martin Marietta Corporation | Wafer level integration and testing |
GB2281659B (en) * | 1993-01-19 | 1996-07-03 | Hughes Aircraft Co | Off-chip conductor structure and fabrication method for large intergrated microcircuits |
US5442225A (en) * | 1993-08-13 | 1995-08-15 | Lsi Logic Corporation | Integrated circuit having interconnects with ringing suppressing elements |
US5500804A (en) * | 1993-12-08 | 1996-03-19 | International Business Machines Corporation | Method to optimize the wiring of multiple wiring media packages |
US6864570B2 (en) * | 1993-12-17 | 2005-03-08 | The Regents Of The University Of California | Method and apparatus for fabricating self-assembling microstructures |
US5904545A (en) * | 1993-12-17 | 1999-05-18 | The Regents Of The University Of California | Apparatus for fabricating self-assembling microstructures |
US5545291A (en) * | 1993-12-17 | 1996-08-13 | The Regents Of The University Of California | Method for fabricating self-assembling microstructures |
US5733175A (en) | 1994-04-25 | 1998-03-31 | Leach; Michael A. | Polishing a workpiece using equal velocity at all points overlapping a polisher |
US5600175A (en) * | 1994-07-27 | 1997-02-04 | Texas Instruments Incorporated | Apparatus and method for flat circuit assembly |
US5607341A (en) | 1994-08-08 | 1997-03-04 | Leach; Michael A. | Method and structure for polishing a wafer during manufacture of integrated circuits |
JP2792532B2 (ja) | 1994-09-30 | 1998-09-03 | 日本電気株式会社 | 半導体装置の製造方法及び半導体ウエハー |
US5841193A (en) * | 1996-05-20 | 1998-11-24 | Epic Technologies, Inc. | Single chip modules, repairable multichip modules, and methods of fabrication thereof |
US6057593A (en) * | 1996-10-10 | 2000-05-02 | Samsung Electronics Co., Ltd. | Hybrid high-power microwave-frequency integrated circuit |
DE10014379A1 (de) * | 2000-03-23 | 2001-10-11 | Infineon Technologies Ag | Verfahren und Vorrichtung zum Verbinden mindestens eines Chips mit einer Umverdrahtungsanordnung |
JP2001313350A (ja) * | 2000-04-28 | 2001-11-09 | Sony Corp | チップ状電子部品及びその製造方法、並びにその製造に用いる疑似ウエーハ及びその製造方法 |
JP2002026280A (ja) * | 2000-06-30 | 2002-01-25 | Seiko Epson Corp | 強誘電体メモリ及びその製造方法 |
US20030173648A1 (en) * | 2002-03-16 | 2003-09-18 | Sniegowski Jeffry Joseph | Multi-die chip and method for making the same |
US6919616B2 (en) * | 2002-03-16 | 2005-07-19 | Memx, Inc. | Chip with passive electrical contacts |
US6706619B2 (en) | 2002-03-16 | 2004-03-16 | Memx, Inc. | Method for tiling unit cells |
US6707077B2 (en) | 2002-03-16 | 2004-03-16 | Memx, Inc. | Chip interconnect bus |
US6791162B2 (en) | 2002-03-16 | 2004-09-14 | Memx, Inc. | Unit cell architecture for electrical interconnects |
DE10317018A1 (de) * | 2003-04-11 | 2004-11-18 | Infineon Technologies Ag | Multichipmodul mit mehreren Halbleiterchips sowie Leiterplatte mit mehreren Komponenten |
US6835262B1 (en) * | 2003-06-19 | 2004-12-28 | Northrop Grumman Corporation | Positive pressure hot bonder |
US7405108B2 (en) | 2004-11-20 | 2008-07-29 | International Business Machines Corporation | Methods for forming co-planar wafer-scale chip packages |
TWI360207B (en) * | 2007-10-22 | 2012-03-11 | Advanced Semiconductor Eng | Chip package structure and method of manufacturing |
US8159247B2 (en) * | 2009-10-06 | 2012-04-17 | International Business Machines Corporation | Yield enhancement for stacked chips through rotationally-connecting-interposer |
US8569894B2 (en) | 2010-01-13 | 2013-10-29 | Advanced Semiconductor Engineering, Inc. | Semiconductor package with single sided substrate design and manufacturing methods thereof |
TWI411075B (zh) | 2010-03-22 | 2013-10-01 | Advanced Semiconductor Eng | 半導體封裝件及其製造方法 |
US9406658B2 (en) | 2010-12-17 | 2016-08-02 | Advanced Semiconductor Engineering, Inc. | Embedded component device and manufacturing methods thereof |
US9722145B2 (en) * | 2015-06-24 | 2017-08-01 | Sharp Laboratories Of America, Inc. | Light emitting device and fluidic manufacture thereof |
CN114041054B (zh) * | 2018-11-28 | 2023-06-27 | 深圳华大智造科技股份有限公司 | 用于集成生物芯片的***和方法 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1206308A (en) * | 1967-11-22 | 1970-09-23 | Sony Corp | Method of making semiconductor wafer |
JPS4912795B1 (ko) * | 1968-12-05 | 1974-03-27 | ||
US3894893A (en) * | 1968-03-30 | 1975-07-15 | Kyodo Denshi Gijyutsu Kk | Method for the production of monocrystal-polycrystal semiconductor devices |
US3588632A (en) * | 1968-11-12 | 1971-06-28 | Josuke Nakata | Structurally reinforced semiconductor device |
US3624467A (en) * | 1969-02-17 | 1971-11-30 | Texas Instruments Inc | Monolithic integrated-circuit structure and method of fabrication |
US3666548A (en) * | 1970-01-06 | 1972-05-30 | Ibm | Monocrystalline semiconductor body having dielectrically isolated regions and method of forming |
US4074342A (en) * | 1974-12-20 | 1978-02-14 | International Business Machines Corporation | Electrical package for lsi devices and assembly process therefor |
JPS5293285A (en) * | 1976-02-02 | 1977-08-05 | Hitachi Ltd | Structure for semiconductor device |
US4057824A (en) * | 1976-04-30 | 1977-11-08 | Rca Corporation | P+ Silicon integrated circuit interconnection lines |
JPS5896760A (ja) * | 1981-12-04 | 1983-06-08 | Clarion Co Ltd | 半導体装置の製法 |
EP0110285A3 (en) * | 1982-11-27 | 1985-11-21 | Prutec Limited | Interconnection of integrated circuits |
JPS59117250A (ja) * | 1982-12-24 | 1984-07-06 | Hitachi Micro Comput Eng Ltd | 半導体装置 |
GB2153144A (en) * | 1984-01-13 | 1985-08-14 | Standard Telephones Cables Ltd | Circuit packaging |
EP0154431B1 (en) * | 1984-02-17 | 1989-08-16 | AT&T Corp. | Integrated circuit chip assembly |
FR2572849B1 (fr) * | 1984-11-06 | 1987-06-19 | Thomson Csf | Module monolithique haute densite comportant des composants electroniques interconnectes et son procede de fabrication |
-
1985
- 1985-10-05 JP JP60222593A patent/JPS6281745A/ja active Pending
-
1986
- 1986-10-02 KR KR1019860008287A patent/KR900008018B1/ko not_active IP Right Cessation
- 1986-10-03 DE DE8686113735T patent/DE3684557D1/de not_active Expired - Fee Related
- 1986-10-03 EP EP86113735A patent/EP0222144B1/en not_active Expired - Lifetime
-
1988
- 1988-10-14 US US07/258,112 patent/US4907062A/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101329414B1 (ko) * | 2005-12-21 | 2013-11-14 | 제너럴 일렉트릭 캄파니 | 내에칭성 웨이퍼 처리 장치 및 이의 제조 방법 |
Also Published As
Publication number | Publication date |
---|---|
KR900008018B1 (ko) | 1990-10-29 |
EP0222144A1 (en) | 1987-05-20 |
EP0222144B1 (en) | 1992-03-25 |
DE3684557D1 (de) | 1992-04-30 |
JPS6281745A (ja) | 1987-04-15 |
US4907062A (en) | 1990-03-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR870004515A (ko) | 상호 접속된 다수의 집적회로 칩으로 구성된 반도체 웨이퍼 규모 집적장치 및 그 제조방법 | |
KR860004457A (ko) | 반도체 집적회로장치 및 그의 제조방법과 제조장치 | |
KR890012373A (ko) | 반도체장치의 제조방법 | |
KR860002862A (ko) | 반도체장치의 제조방법 | |
KR880006786A (ko) | 반도체장치의 제조방법 | |
KR900008660A (ko) | 반도체장치의 제조방법 | |
KR860007741A (ko) | 반도체 기억장치의 제조방법 | |
KR900012335A (ko) | 반도체장치의 제조방법 | |
KR850008057A (ko) | Misfet로 구성되는 반도체 장치의 제조방법 | |
KR900015300A (ko) | 반도체장치의 제조방법 | |
KR860006832A (ko) | 반도체장치의 제조방법 | |
KR860005437A (ko) | 반도체장치의 제조방법 | |
KR900000907A (ko) | 반도체기억장치의 제조방법 | |
KR880008418A (ko) | 반도체장치의 제조방법 | |
KR900019176A (ko) | 반도체장치의 제조방법 | |
KR890004398A (ko) | 반도체장치 및 그의 제조방법 | |
KR870003568A (ko) | 반도체기억장치의 제조방법 | |
KR890015418A (ko) | 반도체 집적회로와 그 제조방법 | |
KR870000758A (ko) | 반도체장치의 제조방법 | |
KR900012331A (ko) | 반도체장치의 제조방법 | |
KR900012342A (ko) | 반도체장치의 제조방법 | |
KR900008697A (ko) | 반도체 웨이퍼 제조방법 | |
KR900013613A (ko) | 반도체장치의 제조방법 | |
KR860005450A (ko) | 반도체 집적 회로장치 및 그의 제조방법 | |
KR900013619A (ko) | 반도체장치의 제조방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
G160 | Decision to publish patent application | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 19930810 Year of fee payment: 4 |
|
LAPS | Lapse due to unpaid annual fee |