KR850006789A - 논리회로 - Google Patents

논리회로

Info

Publication number
KR850006789A
KR850006789A KR1019850001065A KR850001065A KR850006789A KR 850006789 A KR850006789 A KR 850006789A KR 1019850001065 A KR1019850001065 A KR 1019850001065A KR 850001065 A KR850001065 A KR 850001065A KR 850006789 A KR850006789 A KR 850006789A
Authority
KR
South Korea
Prior art keywords
logic circuit
logic
circuit
Prior art date
Application number
KR1019850001065A
Other languages
English (en)
Other versions
KR890004454B1 (ko
Inventor
가쯔히꼬 수야마
Original Assignee
후지쓰가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 후지쓰가부시끼가이샤 filed Critical 후지쓰가부시끼가이샤
Publication of KR850006789A publication Critical patent/KR850006789A/ko
Application granted granted Critical
Publication of KR890004454B1 publication Critical patent/KR890004454B1/ko

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0952Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using Schottky type FET MESFET
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01Modifications for accelerating switching
    • H03K19/017Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356Bistable circuits
    • H03K3/356017Bistable circuits using additional transistors in the input circuit
    • H03K3/356052Bistable circuits using additional transistors in the input circuit using pass gates
    • H03K3/35606Bistable circuits using additional transistors in the input circuit using pass gates with synchronous operation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)
  • Static Random-Access Memory (AREA)
  • Junction Field-Effect Transistors (AREA)
KR1019850001065A 1984-02-29 1985-02-21 논리회로 KR890004454B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP59-037460 1984-02-29
JP59037460A JPS60182759A (ja) 1984-02-29 1984-02-29 論理回路

Publications (2)

Publication Number Publication Date
KR850006789A true KR850006789A (ko) 1985-10-16
KR890004454B1 KR890004454B1 (ko) 1989-11-04

Family

ID=12498133

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019850001065A KR890004454B1 (ko) 1984-02-29 1985-02-21 논리회로

Country Status (6)

Country Link
US (1) US4656611A (ko)
EP (1) EP0153860B1 (ko)
JP (1) JPS60182759A (ko)
KR (1) KR890004454B1 (ko)
CA (1) CA1246694A (ko)
DE (1) DE3580496D1 (ko)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3569859D1 (en) * 1985-12-24 1989-06-01 Fujitsu Ltd Logic circuit
US6127857A (en) * 1997-07-02 2000-10-03 Canon Kabushiki Kaisha Output buffer or voltage hold for analog of multilevel processing

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5080734A (ko) * 1973-11-14 1975-07-01
DE2657561B1 (de) * 1976-12-18 1978-04-13 Ibm Deutschland Nachlade-Referenzschaltungsanordnung fuer einen Halbleiterspeicher
US4355377A (en) * 1980-06-30 1982-10-19 Inmos Corporation Asynchronously equillibrated and pre-charged static ram

Also Published As

Publication number Publication date
KR890004454B1 (ko) 1989-11-04
EP0153860A2 (en) 1985-09-04
DE3580496D1 (de) 1990-12-20
JPH0428179B2 (ko) 1992-05-13
EP0153860B1 (en) 1990-11-14
EP0153860A3 (en) 1987-09-30
JPS60182759A (ja) 1985-09-18
US4656611A (en) 1987-04-07
CA1246694A (en) 1988-12-13

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Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20011024

Year of fee payment: 13

LAPS Lapse due to unpaid annual fee