KR20160149733A

KR20160149733A - Chip embedded printed circuit board and fabrication method thereof

Info

Publication number: KR20160149733A
Application number: KR1020150087291A
Authority: KR
Inventors: 임재성
Original assignee: 하나 마이크론(주)
Priority date: 2015-06-19
Filing date: 2015-06-19
Publication date: 2016-12-28

Abstract

The present invention includes a substrate body part, and a chip package embedded in the substrate body part. The chip package includes a chip die having a first pad, a chip molding part surrounding the chip die to expose the first pad, and a redistribution layer having a second pad electrically connected to the first pad. The substrate body part includes a third pad electrically connected to the second pad of the chip package. According to the present invention, chip damage can be minimized because the chip die is firstly packaged and then embedded in a printed circuit board, and a via hole forming process can be facilitated due to the redistribution layer including a fan-out part.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a printed circuit board having a built-

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a chip-embedded printed circuit board and a manufacturing method thereof, and more particularly, to a chip-embedded printed circuit board and a method of manufacturing the same.

2. Description of the Related Art As electronic products such as mobile terminals have become more sophisticated, multifunctional, and miniaturized, technologies for incorporating chips into printed circuit boards have attracted attention. In the prior art in which chips are mounted on the surface of a printed circuit board, there is a problem that the total module thickness becomes thick due to the chip thickness and the surface area on which the chip is mounted can not be utilized. However, Not only can it be reduced, but also the surface utilization can be improved.

On the other hand, when a chip is embedded in a printed circuit board, if a defect occurs in a subsequent process for manufacturing a printed circuit board, there is a problem that an expensive chip must be discarded. In addition, since the printed circuit board is usually formed of a resin material such as phenol or epoxy and the chip embedded therein is formed of a semiconductor material such as silicon, the thermal expansion coefficient, flexibility, and other mechanical properties Problems such as delamination and cracks are likely to occur. This problem may be more serious in the case of a flexible circuit board that has been used recently.

In addition, a process using a laser is used in a process of forming a via hole in a printed circuit board for electrical connection between an embedded chip and the outside of the chip. In this process, the chip is damaged by laser irradiation There is a concern.

These problems cause a decrease in manufacturing yield and durability of the chip-embedded printed circuit board, which in turn increases the manufacturing cost. Therefore, there is a demand for improvement of the structure and manufacturing method of the chip-embedded printed circuit board.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a chip-embedded printed circuit board having excellent manufacturing yield and durability and a method of manufacturing the same.

It is another object of the present invention to provide a chip-embedded printed circuit board and a method of manufacturing the chip-embedded printed circuit board, which are particularly suitable for application to a chip embedded type flexible circuit board.

According to an aspect of the present invention, there is provided a chip-embedded printed circuit board including a substrate body and a chip package embedded in the substrate body, the chip package including a chip die having a first pad, And a re-wiring layer having a chip molding portion surrounding the chip die and a second pad electrically connected to the first pad to expose the first pad, And a third pad electrically connected thereto. The substrate body may further include vias electrically connected to the second pad and the third pad.

In some embodiments of the present invention, the second pad includes a fan-out portion extending outwardly of the chip die, and a via electrically connecting the second pad and the third pad is electrically connected to the second Pad.

In addition, the chip die may have a thickness of 120 탆 or less.

The chip-embedded printed circuit board according to another embodiment of the present invention includes a chip package in which a molding part is formed such that a first pad of a chip die is exposed, and a substrate body part in which the chip package is embedded, Wherein the chip package is embedded in the substrate body portion such that the first pad is electrically coupled to the second pad and the second pad comprises a fan-out portion extending outwardly of the chip die .

The fan-out portion may further include a third pad extending outside the chip package and electrically connected to the second pad through a via, the via extending outwardly of the chip package of the fan- Portion of the second pad.

In some embodiments of the present invention, the rewiring layer may be a layered structure in which a plurality of layers including a conductive pattern are laminated. The chip package and / or the substrate body portion may be formed of a flexible material, and the chip package may be a flexible package capable of bending to a radius of curvature of 100 mm or less, and the substrate body portion may be flexible Substrate.

According to another aspect of the present invention, there is provided a method of embedding a chip in a printed circuit board, comprising: forming a molding part to expose a first pad of a chip die and performing primary packaging; Forming a re-wiring layer on the exposed surface of the first pad to form a chip package, wherein the re-wiring layer includes a second pad contacting at least a portion of the first pad, Comprising: a fan-out portion extending outwardly of the chip die; Disposing the chip package on a support; Embedding a chip package by covering the cover part on the chip package; Forming a via hole to communicate with a second pad of the embedded chip package; And filling the via hole with a conductive material to form a via and forming a third pad.

Here, the via hole may be formed by a laser and formed on a fan-out portion of the second pad.

A method of embedding a chip according to another embodiment of the present invention in a printed circuit board includes the steps of embedding a chip package having a molding part on a printed circuit board so that a first pad of the chip die is exposed, Forming an included re-wiring layer; Disposing the chip package on the rewiring layer such that the first pad and the second pad are in contact at least in part and the second pad extends outwardly of the chip die step; Embedding a chip package by covering the cover part on the chip package; Forming a via hole to communicate with a second pad of the embedded chip package; And filling the via hole with a conductive material to form a via and forming a third pad.

According to the present invention, it is possible to provide a chip-embedded printed circuit board excellent in manufacturing yield and durability by first packaging a chip and then embedding the chip in a printed circuit board. Specifically, there is an effect of minimizing peeling or cracking due to mismatch of thermal expansion coefficient, flexibility, and other mechanical properties between the material of the printed circuit board and the chip material during the subsequent printed circuit board manufacturing process.

In addition, a redistribution layer (RDL) connected to the bonding pads of the chip is formed in a fan-out shape, so that a built-in chip is electrically connected to the printed circuit board There is an effect that the damage of the chip by the laser irradiation is minimized in the process of forming the via hole.

In addition, the re-wiring layer connected to the bonding pads of the chip has the effect of embedding a chip having a fine pattern into the printed circuit board so that electrical connection with the outside is difficult by a via hole forming technique using a laser.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic cross-sectional view of a chip package according to the present invention which is firstly packaged for embedding in a printed circuit board.
2 is a schematic cross-sectional view of a chip package having a strained rewiring layer;
Figures 3A-3F are exemplary fabrication flowcharts of a chip package according to the present invention.
4 is a schematic cross-sectional view of a chip-embedded printed circuit board according to a first embodiment of the present invention;
5A to 5D are flow charts of manufacturing the chip-embedded printed circuit board of FIG.
6 is a schematic cross-sectional view of a chip-embedded printed circuit board according to a second embodiment of the present invention;
7A to 7D are a manufacturing flowchart of the chip-embedded printed circuit board of FIG. 6;
8 is a schematic cross-sectional view of a chip-embedded printed circuit board according to a third embodiment of the present invention;
9 is a schematic cross-sectional view of a chip-embedded printed circuit board according to a fourth embodiment of the present invention.
10 is a schematic sectional view of a chip-embedded printed circuit board according to a fifth embodiment of the present invention.
11A to 11D are flow charts of manufacturing a chip-embedded printed circuit board according to a fifth embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, but the present invention is not limited to or limited by the embodiments. In describing the various embodiments of the present invention, corresponding elements are denoted by the same names and the same reference numerals. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

The main feature of the present invention is that the chip is firstly packaged and then embedded in a printed circuit board.

1 is a schematic cross-sectional view of a chip package 100 according to an embodiment of the present invention, which is firstly packaged for embedding in a printed circuit board. 1, a chip package 100 according to an exemplary embodiment of the present invention includes a chip die 110 having a first pad 111 formed thereon, a chip molding part 120 surrounding the chip die 110 And a second pad 140 electrically connected to the first pad 111 are formed on the first pad 111. [

The chip die 110 may be a memory or non-memory device fabricated from an integrated circuit (IC) process from a semiconductor wafer such as silicon. A first pad (not shown) for electrical connection to the outside 111 may be formed. The first pad 111 is formed on one surface of the chip die 110, but the present invention is not limited thereto. The first pad 111 may be formed on at least one surface of the chip die 110, As shown in FIG. The chip die 110 may be formed on a flexible substrate or may be a flexible device whose thickness is reduced to such an extent that ductility occurs.

The chip molding part 120 may be formed to surround three surfaces of the chip die 110 except the surface on which the first pad 111 is formed. The chip molding part 120 may be formed of an EMC (Epoxy) Mold Compound) may be used. The chip molding part 120 may be formed by a film molding method or a compression molding method, but is not limited thereto. The chip molding part 120 may be formed of a soft resin so that the chip package 100 has flexibility.

A redistribution layer (RDL) 130 may be formed on one surface of the chip die 110 and the chip molding portion 120 where the first pad 111 is formed. The redistribution layer 130 includes a second pad 140 that is in electrical communication with the first pad 111 of the chip die 110 wherein the second pad 140 extends into the chip die 110 And a fan-in portion 141 that contacts the first pad 111 and a fan-out portion 142 that extends outwardly of the chip die 110. Here, the fan-in portion 141 and the fan-out portion 142 may be formed separately from each other in the second pad 140 formed of one conductive pattern, instead of being formed separately. That is, the second pad 140 is formed as one conductive pattern in the re-distribution layer 130, and the portion of the one conductive pattern that extends to the inside of the chip die 110 and contacts the first pad 111 The fan-in portion 141 and the outwardly extending portion may be the fan-out portion 142.

The re-wiring layer 130 and the second pad portion 140 are not necessarily structured as shown in FIG. 1, but may be formed of a plurality of layers as shown in FIG. 2 shows an example in which the re-distribution layer 130 has a three-layered structure of a first re-distribution layer 131, a second re-distribution layer 132 and a third re-distribution layer 133, The arrangement of the second pads 140 can be freely arranged in a state where the first pads 111 are electrically connected. 2 is an example. It is not necessary that the plurality of layers is necessarily three layers, and it is not required that the wiring structure in the redistribution layer 130 is symmetrical as shown in Fig. The second pad 140 of FIG. 2 does not directly contact the first pad 111, but a portion that does not overlap with the chip die 110 as viewed from above may be the fan-out portion 142.

3A-3F are exemplary manufacturing flow diagrams of a chip package 100 in accordance with the present invention. Referring to FIGS. 3A to 3F, the chip die 110 is first attached to the first carrier 210 via the first release tape 220 (FIG. 3A). The first carrier 210 is a substrate for supporting and fixing the chip die 110 for a subsequent molding process, and various substrates such as a glass substrate, a silicon substrate, and a metal substrate can be used. A plurality of chip dies 110 may be mounted on the first carrier 210 at regular intervals, and the first release tape 220 for attaching the chip die 110 may be a heat- Can be used. The chip die 110 may be attached such that the side on which the first pad 111 is formed faces the first release tape 220.

Next, a molding process is performed to form a chip molding part 120 (FIG. 3B). The molding process may be various molding processes such as film molding or compression molding. In particular, when a film molding process is used, a thin chip package 100 can be easily formed, Do. Three surfaces of the chip die 110 except the surface on which the first pads 111 are formed may be surrounded by the molding resin by the molding process.

After the molding process, the second carrier 310 is attached to the upper surface of the chip molding part via the second release tape 320 (FIG. 3C). The second carrier 310 is a substrate for supporting the chip dies 110 in the subsequent rewiring layer formation process and the second release tape 320 is a substrate for attaching the molded chip dies 110 to the second carrier 310 . The second carrier 310 and the second release tape 320 may be the same as the first carrier 210 and the first release tape 220.

Next, a process of separating the first carrier substrate 210 and the first release tape 220 is performed (FIG. 3D). The separation process may be different depending on the type of the first release tape 220. For example, if the first release tape 220 is a thermally detachable tape, the separation process may be a process of applying heat to separate the first release tape 220, It may be a step of irradiating and separating light.

When the first carrier substrate 210 and the first release tape 220 are separated from each other, the first pads 111 of the chip die 110 are exposed to the surface, and a re- (Fig. 3E). The redistribution layer 130 may include a plurality of second pads 140 wherein the second pads 140 may include a fan-out portion 142 extending outwardly of each chip die 110 have. In FIG. 3E, the rewiring layer 130 is formed as one layer. However, the rewiring layer 130 is an example, and the plurality of layers may be formed in a stacked form as shown in FIG.

Next, the second carrier 310 and the second release tape 320 may be separated and cut into individual chip packages 100 (FIG. 3F). The separation process of the second carrier 310 and the second release tape 320 may be the same as the separation process of the first carrier 210 and the first release tape 220. The separation process of the second carrier 310 and the second release tape 320 may be performed after the cutting process.

1 to 3, the structure of the chip package 100 according to the present invention and the manufacturing process thereof have been described. However, the present invention is not limited to the main feature of incorporating the chip package 100 on the printed circuit board .

4 is a schematic cross-sectional view of a printed circuit board 400 according to a first embodiment of the present invention in which a chip package 100 is embedded. 4, the chip-embedded printed circuit board 400 according to the first embodiment of the present invention includes a substrate body 410, a chip package 100 embedded in the substrate body 410, The third pad 430 electrically connected to the second pad 140 of the chip package and electrically connected to the third pad 430 and the third pad 430 electrically formed on the surface of the substrate body portion 410, And a via 420. 4, the substrate body 410 may include a plurality of layers, and other circuit patterns may be formed in addition to the vias 420 and the third pads 430. Referring to FIG. In addition, passive or active devices other than the chip package 100 may be embedded or may be mounted on the surface.

The third pad 430 is electrically connected to the second pad 140 via the via 420 and supplies power to the chip die 110 through the first pad 111 . At this time, the via 420 may be formed to contact the fan-out portion 142 of the second pad 140.

Figs. 5A to 5D are flowcharts of manufacturing the chip-embedded printed circuit board of Fig. 5A is a plan view of a chip package 100 according to the present invention. Referring to FIG. 5A, the chip package 100 is covered with a cover 412, (Fig. 5B). The material of the support portion 411 and the cover portion 412 is not particularly limited, but may include a phenol resin or an epoxy resin, and may be a flexible material. The forming process of the supporting portion 411 and the cover portion 412 may be performed according to a general printed circuit board manufacturing process.

Next, a via hole 421 is formed in the cover portion 412 so as to communicate with the second pad 140 of the embedded chip package 100 (FIG. 5C). The via hole 421 may be formed using a laser, and may be formed on the fan-out portion 142 of the second pad 140 as shown in FIG. 5C. In the chip-embedded printed circuit board, the chip die 110 may be damaged by laser irradiation in the process of forming a via hole. By forming a via hole on the fan-out portion 142 as shown in FIG. 5C, It can be prevented from being damaged by laser irradiation. In the case of a via hole formed by laser, it is difficult to cope with a chip having a fine pattern because the diameter is about 50 mu m and the minimum pitch (Pitch) is about 150 mu m. However, The chip having the fine pattern can be effectively embedded in the printed circuit board by forming the via-hole after forming the fan-out portion 142 extending to the printed circuit board.

5D is a step of filling the via hole 421 with a conductive material to form the via 420 and the third pad 430. The material and the forming process can be performed according to a general printed circuit board manufacturing process.

6 is a schematic cross-sectional view of a chip-embedded printed circuit board 500 according to a second embodiment of the present invention. Fig. 6 can be the same in structure and manufacturing process as Fig. 4 except that the chip die 100 is disposed in an inverted manner.

A manufacturing flow chart of the chip-embedded printed circuit board 500 of Fig. 6 is shown in Figs. 7A to 7D. The chip package 100 according to the present invention is disposed on the supporting portion 411 such that the rewiring layer 130 is in contact with the supporting portion 411 (Fig. 7A) (FIG. 7B). At this time, at least the surface of the supporting portion 411, which is in contact with the chip package 100, may be formed of an insulating material.

Next, a via hole 421 is formed in the cover portion 412 and the chip molding portion 120 so as to communicate with the second pad 140 of the embedded chip package 100 (FIG. 7C). The via hole 421 may be formed using a laser, and may be formed on the fan-out portion 142 of the second pad 140 as shown in FIG. 7C.

7D is a step of filling the via hole 421 with a conductive material to form the via 420 and the third pad 430. The material and the forming process can be performed according to a general printed circuit board manufacturing process.

4 and 6 illustrate a structure in which the chip package 100 is completely embedded in the substrate body 410 composed of the support portion 411 and the cover portion 412. However, as shown in FIG. 8 or 9, 100 may be exposed to the substrate main body 410. 8 is a schematic cross-sectional view of a chip-embedded printed circuit board 600 according to a third embodiment of the present invention in which the surface of the chip package 100 on which the second pad 140 is formed is covered with the substrate body portion 410 . In this structure, since there is no need to form a via hole for electrically connecting the second pad 140 and the third pad 430, chip damage by laser irradiation can be basically eliminated. Although the third pad 430 is illustrated in FIG. 8, the second pad 140 is exposed in the structure of FIG. 8, so that the third pad 430 may be omitted.

9, the chip package 100 is inverted from that of FIG. 8, and the other surface of the second pad 140 formed on the chip package 100 is exposed without being covered with the substrate body portion 410. In the structure of FIG. 9, since the via hole is formed only in the chip molding portion 120 without passing through the substrate body portion 410, the via hole forming process can be easily performed.

On the other hand, the re-wiring layer can be formed in the substrate body portion without being formed in the chip package 100. 10 is a schematic cross-sectional view of a chip-embedded printed circuit board according to a fifth embodiment of the present invention, in which the re-wiring layer is not included in the chip package 100 but is included in the substrate body portion.

10, a chip-embedded printed circuit board 800 according to a fifth embodiment of the present invention includes a chip package 110 in which a chip package 110, which is firstly packaged with a chip molding part 120, And may be built in the body portion 810. At this time, the chip molding part 120 may be formed so as to surround the remaining three surfaces except the surface on which the first pad 111 is formed so that the first pad 111 of the chip die 110 is exposed. In contrast to the above- The package 900 does not include a re-wiring layer. The chip package 900 may be formed by the same manufacturing method except for FIG. 3E for rewiring layer formation in the fabrication flowchart shown in FIGS. 3A to 3F, and the first carrier 220 and the first release tape The chip die 110 is attached to the first carrier 220 and the first carrier 220 and the first release tape 220 are separated after the molding step of FIG. It is possible.

The substrate main body portion 810 may include a support portion 811, a cover portion 812, and a re-wiring layer 813. The re-distribution layer 813 includes a second pad 840 and the second pad 840 extends into the chip die 110 when the chip package 900 is disposed on the re-distribution layer 813 And may include a fan-in portion 841 and an outwardly extending fan-out portion 842.

The via 420 electrically connects the third pad 430 formed on the upper surface of the cover portion 812 and the second pad 840 of the rewiring layer 813 and electrically connects the second pad 840 of the second pad 840 to the fan- 842 to the second pad 840.

11A to 11D are a manufacturing flowchart of the chip-embedded printed circuit board 800 of FIG. 11A, a re-wiring layer 813 is formed on the supporting portion 811 and a second pad 840 is formed on the re-wiring layer 813. [ Although the second pad 840 is illustrated as being embedded in a predetermined insulating layer, the second pad 840 may be formed on the supporting portion 811 only. Also, the re-distribution layer 813 may be a layered structure in which a plurality of layers including a conductive pattern are laminated like the re-distribution layer 130 in FIG.

Next, the chip package 900 is disposed on the re-wiring layer 813 such that the first pad 111 is in electrical contact with the second pad 840 (FIG. 11B). At this time, a portion of the second pad 840 extending to the outside of the chip die 110 forms the fan-out portion 842.

A cover portion 812 is formed to cover the chip package 900 and a via hole 421 is formed in the cover portion 812 and the chip molding portion 120 so as to communicate with the second pad 840 11c). The via hole 421 may be formed using a laser, and may be formed on the fan-out portion 842 of the second pad 840 as shown in FIG. 11C. 11C shows that the via hole 421 penetrates both the cover portion 421 and the chip molding portion 120. The second pad 840 of the rewiring layer 813 is formed on the outer side of the chip package 900 The via hole 421 may be formed so as to penetrate only the cover portion 812. In this case, This can be achieved by forming the re-distribution layer 813 on the substrate body portion 810 without forming the re-distribution layer 813 on the chip package 900.

11D is a step of filling the via hole 421 with a conductive material to form a via 420 and a third pad 430. The material and the forming process may be performed according to a general printed circuit board manufacturing process.

10 and 11, a rewiring layer 813 is formed on the supporting portion 811 and the chip package 900 is inverted so that the first pad 111 is brought into contact with the second pad 840 of the rewiring layer 813 However, it is also possible to arrange the chip package 900 on the supporting part so that the first pad 111 is positioned on the upper part, and then the re-wiring layer 813 is formed thereon.

According to the above-described chip-embedded printed circuit board according to the present invention, since chips are firstly packaged and then embedded in a printed circuit board, the subsequent printed circuit board manufacturing process, such as the process of forming the cover portion of the substrate main body, It is possible to suppress the occurrence of chip damage, interface delamination, cracking, and the like due to mechanical stress between the substrate main body portion and the chip. In the case of flexible printed circuit boards, the problem due to such mechanical stresses can be particularly serious, and the present invention is particularly suitable for flexible printed circuit boards.

The present invention can be usefully applied to the manufacture of chip-embedded flexible printed circuit boards having conformal bending properties. Conformal bending characteristics refer to bending characteristics with substantially the same radius of curvature. In order to be able to have such characteristics, both the embedded chip and the substrate body should not only have excellent bending characteristics, but also cause damage to the chip due to mechanical stress between the two, It should be able to prevent interface delamination and cracking. In this respect, it may be helpful to package the chip first and then embed it in the substrate body portion. For conformal bending characteristics, the chip die used in the present invention may have a thickness of 120 탆 or less, and the chip package may be a flexible package capable of bending to a radius of curvature of 100 mm or less, and the substrate body portion may have a radius of curvature Which is a flexible substrate.

The present invention also relates to a method of manufacturing a printed circuit board by forming a re-wiring layer in a fan-out shape and forming a via hole of a printed circuit board on a fan-out portion, Can be minimized. According to some embodiments of the present invention, the rewiring layer may be formed on the substrate body portion instead of the chip package. In this case, since the fan-out portion can be extended to the outside of the chip package, there is a process in which the via hole forming process becomes easier.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. For example, in the embodiments of the present invention, the third pad and the second pad are connected through a single via. However, a multi-layered rewiring layer may be formed between the second pad and the third pad, Can be formed. Also, the re-wiring layer is described as being formed on either the chip package or the substrate body portion, but it may be formed on both. Accordingly, the scope of protection of the present invention should be determined by the description of the claims and their equivalents.

100, 900: Chip package
110: chip die
111: first pad
120: chip molding part
130, 813: rewiring layer
140, 840: the second pad
141, 841: Fan-
142, 842: a fan-out section
210: first carrier
220: First release tape
310: second carrier
320: second release tape
400, 500, 600, 700, 800: embedded printed circuit board
410, and 810:
411, 811:
412 and 812:
420: Via
421:
430: Third pad

Claims

A substrate main body portion;
A chip package embedded in the substrate main body portion;
Lt; / RTI >
The chip package includes:
A re-wiring layer having a chip die on which a first pad is formed, a chip molding portion surrounding the chip die to expose the first pad, and a second pad electrically connected to the first pad,
Wherein the substrate body portion includes a third pad electrically connected to the second pad of the chip package.

The method according to claim 1,
Wherein the substrate body portion further comprises a via,
And the second pad and the third pad are electrically connected through the via.

3. The method of claim 2,
Wherein the second pad comprises a fan-out portion extending outwardly of the chip die,
Wherein the via is connected to the second pad in the fan-out portion.

The method according to claim 1,
Wherein the chip die has a thickness of 120 占 퐉 or less.

A chip package in which a molding portion is formed such that a first pad of the chip die is exposed;
A substrate main body portion in which the chip package is embedded;
A printed circuit board comprising:
Wherein the substrate body portion includes a rewiring layer having a second pad formed thereon,
Wherein the chip package is embedded in the substrate main body portion such that the first pad is electrically connected to the second pad,
Wherein the second pad comprises a fan-out portion extending outwardly of the chip die.

6. The method of claim 5,
Wherein the fan-out portion extends outside the chip package.

The method according to claim 6,
Further comprising a third pad electrically connected to the second pad via a via,
Wherein the via is in contact with the second pad through a portion extending outwardly of the chip package of the fan-out portion.

The method according to claim 1 or 5,
Wherein the re-wiring layer is a layered structure in which a plurality of layers including a conductive pattern are laminated.

6. The method according to claim 1 or 5,
Wherein the chip package is a flexible package.

10. The method of claim 9,
Wherein the substrate body portion is a flexible substrate.

10. The method of claim 9,
The chip package is a flexible package that can be bent to a radius of curvature of less than 100 mm,
Wherein the substrate main body portion is a flexible substrate that can be bent to a radius of curvature of 300 mm or less.

A method of embedding a chip in a printed circuit board,
Forming a molding part to expose a first pad of the chip die and performing primary packaging;
Forming a re-wiring layer on the exposed surface of the first pad to form a chip package, wherein the re-wiring layer includes a second pad contacting at least a portion of the first pad, Comprising: a fan-out portion extending outwardly of the chip die;
Disposing the chip package on a support;
Embedding a chip package by covering the cover part on the chip package;
Forming a via hole to communicate with a second pad of the embedded chip package; And
Filling the via hole with a conductive material to form a via and forming a third pad;
&Lt; / RTI >

13. The method of claim 12,
Wherein the via hole is formed by a laser.

13. The method of claim 12,
And the via hole is formed on the fan-out portion of the second pad.

CLAIMS 1. A method of embedding a chip package on a printed circuit board on which a molding portion is formed such that a first pad of the chip die is exposed,
Forming a redistribution layer including a second pad on the support;
Disposing the chip package on the redistribution layer such that the first pad and the second pad are in contact at least in part and the second pad extends outwardly of the chip die step;
Embedding a chip package by covering the cover part on the chip package;
Forming a via hole to communicate with a second pad of the embedded chip package; And
Filling the via hole with a conductive material to form a via and forming a third pad;
&Lt; / RTI >

16. The method according to claim 12 or 15,
Wherein the molding part is formed by film molding.