JP2005033141A - Semiconductor device, its manufacturing method, false wafer, its manufacturing method, and packaging structure of semiconductor device - Google Patents

Semiconductor device, its manufacturing method, false wafer, its manufacturing method, and packaging structure of semiconductor device Download PDF

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JP2005033141A
JP2005033141A JP2003273706A JP2003273706A JP2005033141A JP 2005033141 A JP2005033141 A JP 2005033141A JP 2003273706 A JP2003273706 A JP 2003273706A JP 2003273706 A JP2003273706 A JP 2003273706A JP 2005033141 A JP2005033141 A JP 2005033141A
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chip
chip component
material layer
conductive material
semiconductor device
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Masaki Hatano
正喜 波多野
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Sony Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method conducting the electrode of a chip component to the rear face side easily and securely and allowing external terminals to be formed on the surface and rear face sides at a low cost, a false wafer, its manufacturing method, and a packaging structure of the semiconductor device. <P>SOLUTION: There has a void portion for arranging a chip component in such a manner that it corresponds to the electrodes 5 of the chip component 3 to be arranged in its vicinity. A substrate 20 with a via hole provided with plugs 19 beforehand is attached onto a supporting substrate 21 together with the chip component 3. On a false wafer 29 that is integrated by covering these with a resin 4, the electrode 5 is connected with the plug 19 by wiring 24. A part of the wiring 24 is exposed to form the external terminal 25 on the surface 41. After that, the resin 4 on the rear face 42 of the chip component 3 is ground to expose the plugs 19. By this exposed part, the external terminal 26 on this surface is formed. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、半導体装置及びその製造方法、疑似ウェーハ及びその製造方法、並びに半導体装置の実装構造に関するものである。   The present invention relates to a semiconductor device and a manufacturing method thereof, a pseudo wafer and a manufacturing method thereof, and a semiconductor device mounting structure.

従来、携帯用電子機器の小型・軽量化、高速化の要求に対し、一つの方法として、ＩＣ（Integrated Circuit）の高集積化、微細化を図って複数の機能をワンチップ（システムＬＳＩ）化しているが、歩留低下等による製造コストの増大等の問題でシステムＬＳＩを低コストで実現することが難しくなっている。一方で、複数の半導体チップをワンパッケージ化したＭＣＭ（Multi Chip Module）が提案されている。   Conventionally, in response to the demands for miniaturization, weight reduction, and high speed of portable electronic devices, one method is to increase the integration and miniaturization of IC (Integrated Circuit) to make multiple functions into one chip (system LSI). However, it is difficult to realize a system LSI at a low cost due to problems such as an increase in manufacturing cost due to a decrease in yield and the like. On the other hand, an MCM (Multi Chip Module) in which a plurality of semiconductor chips are packaged has been proposed.

ＭＣＭは多層配線基板に半導体チップを配置しているが、搭載する半導体チップの接続端子ピッチが狭くなると配線基板の製造が難しくなり、基板のコストアップとなる。また、バンプやワイヤボンディング、タブ等で接続するため、接続端子数に制限がある上、その平面視面積は搭載半導体チップの平面視面積の総和より大きくなってしまう。更に、信号伝達が遅くなり、性能低下等の問題がある。   In the MCM, a semiconductor chip is arranged on a multilayer wiring board. However, if the connection terminal pitch of the semiconductor chip to be mounted becomes narrow, it becomes difficult to manufacture the wiring board, and the cost of the board increases. In addition, since the connection is made by bumps, wire bonding, tabs, etc., the number of connection terminals is limited, and the plan view area is larger than the sum of the plan view areas of the mounted semiconductor chip. In addition, signal transmission is delayed, causing problems such as performance degradation.

ＭＣＭの製造技術については、複数のベアチップをその表面が平坦になるように支持基板上に貼り付けて配線することにより、生産性よく配線することが開示されている（後述の特許文献１参照）。また、機能別に作製した複数個の半導体チップを互いに隣接して接着することにより、四辺形に形成した合成チップをウェーハ上に貼り付け、このチップのアクティブ面を平坦化して露出させたチップの外部接続端子から配線することにより、小面積化した合成チップを小さいパッケージに形成することが開示されている（後述の特許文献２参照）。更に、支持基板に良品チップを貼り付けた後に、保護物質を被着して剥離することで疑似ウェーハを作製し、その上に半導体プロセスにより配線することが開示されている（後述の特許文献３参照）。   As for the manufacturing technology of MCM, it is disclosed that wiring is performed with high productivity by attaching a plurality of bare chips on a support substrate so that the surface thereof is flat (see Patent Document 1 described later). . In addition, by adhering a plurality of semiconductor chips manufactured by function adjacent to each other, a composite chip formed in a quadrilateral shape is attached onto the wafer, and the active surface of this chip is flattened and exposed outside the chip. It is disclosed that a synthetic chip with a reduced area is formed in a small package by wiring from a connection terminal (see Patent Document 2 described later). Further, it is disclosed that after attaching a non-defective chip to a support substrate, a protective substance is applied and peeled off to produce a pseudo wafer, and wiring is performed thereon by a semiconductor process (Patent Document 3 described later). reference).

このうち、本出願人が提起した特許文献３（以下、先願発明と称する。）は、自社製又は他社製の区別なく、ウェーハより半導体チップを切り出した後、オープン／ショート或いはＤＣ（直流）電圧測定により良品と確認された半導体ベアチップのみを疑似ウェーハ上に再配置し、これに所定の製造工程を施してチップ状電子部品を作製するものであるが、その製造プロセスを図３６に示す。   Among these, Patent Document 3 (hereinafter referred to as the prior invention) proposed by the present applicant is based on whether the semiconductor chip is cut out from the wafer, whether it is made in-house or made by another company, and then open / short or DC (direct current). Only the semiconductor bare chip confirmed to be non-defective by voltage measurement is rearranged on the pseudo wafer, and a predetermined manufacturing process is performed on the semiconductor bare chip to produce a chip-shaped electronic component. The manufacturing process is shown in FIG.

即ち、図３６（ａ）は、仮の支持基板として用いた石英基板１を示す。但し、基板への加熱プロセスは４００℃以下であるため、安価なガラス基板も使用でき、また、この石英基板１は繰り返し使用可能である。   That is, FIG. 36A shows the quartz substrate 1 used as a temporary support substrate. However, since the heating process for the substrate is 400 ° C. or lower, an inexpensive glass substrate can be used, and the quartz substrate 1 can be used repeatedly.

次に、図３６（ｂ）のように、石英基板１上に、紫外線を照射されると粘着力が低下する例えばアクリル系の粘着シート２を貼り付ける。   Next, as shown in FIG. 36B, for example, an acrylic pressure-sensitive adhesive sheet 2 whose adhesive strength is lowered when irradiated with ultraviolet rays is attached to the quartz substrate 1.

次に、図３６（ｃ）のように、良品と確認された複数の良品ベアチップ３をチップ表面（デバイス面）２８を下向きに配列して粘着シート２に貼り付ける。なお、良品ベアチップ３は、通常のウェーハ工程でダイシングして、使用したダイシングシート（図示せず）の延伸状態から取り出してもよく、チップトレイから移載してもよい。   Next, as shown in FIG. 36C, a plurality of non-defective bare chips 3 confirmed as non-defective products are attached to the adhesive sheet 2 with the chip surface (device surface) 28 arranged downward. The non-defective bare chip 3 may be diced in a normal wafer process, taken out from the stretched state of a used dicing sheet (not shown), or transferred from a chip tray.

次に、図３６（ｄ）のように、良品ベアチップ３上から有機系絶縁性樹脂、例えばエポキシ系等の樹脂４をスピンコート法か印刷法により、均一に塗布する。   Next, as shown in FIG. 36 (d), an organic insulating resin, for example, an epoxy resin 4 is applied uniformly on the non-defective bare chip 3 by spin coating or printing.

次に、図３６（ｅ）のように、石英基板１の裏側１ａから紫外線を照射して、粘着シート２の粘着力を弱め、樹脂４で側面及び裏面が連続して固められた複数の良品ベアチップ（以下、半導体チップ、チップ又はチップ部品と称することがある。）３を配した疑似ウェーハ２９を石英基板１から接着面１４で剥離する。   Next, as shown in FIG. 36E, ultraviolet rays are irradiated from the back side 1a of the quartz substrate 1 to weaken the adhesive strength of the pressure-sensitive adhesive sheet 2, and a plurality of non-defective products whose side surfaces and back surface are continuously hardened by the resin 4 The pseudo wafer 29 on which the bare chip (hereinafter sometimes referred to as a semiconductor chip, a chip or a chip component) 3 is disposed is peeled off from the quartz substrate 1 by the bonding surface 14.

次に図３６（ｆ）のように、良品ベアチップ表面２８（デバイス面）が上になるように疑似ウェーハ２９をひっくり返す。下図は疑似ウェーハ２９の一部を拡大図示したものであり、図示の如く、Ｓｉ基板上にＳｉＯ２膜７を介してＡ１電極パッド５及びパッシベーション膜８が形成されている。 Next, as shown in FIG. 36 (f), the pseudo wafer 29 is turned over so that the non-defective bare chip surface 28 (device surface) faces upward. The lower figure is an enlarged view of a part of the pseudo wafer 29. As shown in the figure, the A1 electrode pad 5 and the passivation film 8 are formed on the Si substrate via the SiO 2 film 7.

その後、無電解めっき法により、開口されたＡｌ電極パッド５の上面のみに、選択的にＮｉめっき層を形成し、この上に配したはんだペーストを加熱溶融してはんだバンプをウェーハ一括で形成後に、再度プローブ検査により電気的特性を測定することにより、更により確実に良品チップのみを選別する。   After that, an Ni plating layer is selectively formed only on the upper surface of the opened Al electrode pad 5 by electroless plating, and the solder paste disposed thereon is heated and melted to form solder bumps in a batch of wafers. Then, by measuring the electrical characteristics again by probe inspection, it is possible to select only non-defective chips even more reliably.

上記のように形成した半導体チップ３は、ワンチップに個片化後、例えば図３９に示すようにはんだバンプ３３を介して回路基板３９の電極４０にマウントしたり、例えば図４０に示すようにチップ３を並列に配し、この複数のチップ３間の再配置配線１２（半導体チップ内の配線をチップ上の任意の位置に引き出して行う配線）を行うことにより、回路構成をしてＭＣＭを構成することができる。また、図示しないが半導体チップ３の電極パッド５から接続孔を介して絶縁層上に配線を導出し、更にこのような構造を積み上げて多層構造化することにより、回路基板へのマウント時に任意の位置に再配置配線を行って多ピン化に対応することもでき、これらを疑似ウェーハ２９上で一括して行うことができる。   The semiconductor chip 3 formed as described above is singulated into one chip and then mounted on the electrode 40 of the circuit board 39 via the solder bumps 33 as shown in FIG. 39, for example, or as shown in FIG. The chip 3 is arranged in parallel, and the rearrangement wiring 12 (wiring performed by drawing the wiring in the semiconductor chip to an arbitrary position on the chip) between the plurality of chips 3 is performed, so that the MCM is configured with the circuit configuration. Can be configured. Although not shown, wiring is led out from the electrode pad 5 of the semiconductor chip 3 onto the insulating layer through the connection hole, and further, such a structure is stacked to form a multi-layer structure, so that an arbitrary structure can be obtained when mounting on the circuit board. It is possible to cope with the increase in the number of pins by performing rearrangement wiring at the position, and these can be performed collectively on the pseudo wafer 29.

このように、先願発明によれば、半導体チップの電極面以外（即ち、チップの側面及び裏面）が連続した保護物質によって保護されるので、チップ化後のハンドリングにおいてチップが保護され、ハンドリングが容易となる。   Thus, according to the invention of the prior application, since the surface other than the electrode surface of the semiconductor chip (that is, the side surface and the back surface of the chip) is protected by the continuous protective substance, the chip is protected in handling after chip formation, It becomes easy.

また、半導体ウェーハから切出した良品のみを選択して再配置しているので、あたかも全品が良品チップからなる疑似ウェーハが得られ、配置した良品チップに対してウェーハ一括でのバンプ処理等が可能となり、低コストのバンプチップを形成できると共に、半導体チップを疑似ウェーハから切り出す際に、チップ間の保護物質の部分を切断することになるので、半導体チップ本体への悪影響（歪みやばり、亀裂等のダメージ）を抑えて容易に切断することができる。   In addition, since only the non-defective products cut out from the semiconductor wafer are selected and rearranged, it is possible to obtain a pseudo wafer in which all the products are composed of non-defective chips, and it is possible to perform bump processing on the arranged good chips in a batch of wafers. In addition to being able to form low-cost bump chips, when the semiconductor chip is cut out from the pseudo wafer, the portion of the protective material between the chips will be cut, so adverse effects on the semiconductor chip body (distortion, flash, cracks, etc.) It can be cut easily with reduced damage.

しかも、保護物質によってチップの側面及び裏面が覆われているため、Ｎｉ無電解めっき処理も可能である。そして、自社製ウェーハのみならず、他社から購入したベアチップでも容易にはんだバンプ処理等が可能になる。   In addition, since the side surface and the back surface of the chip are covered with a protective substance, Ni electroless plating can be performed. And solder bump processing etc. become possible not only with the wafer made in-house but with the bare chip purchased from other companies.

また、ＭＣＭに搭載される異種ＬＳＩチップを全て同一半導体メーカーから供給されるケースは少なく、ＳＲＡＭ、フラッシュメモリーやマイコン、更にＣＰＵ（中央演算処理ユニット）を、それぞれ得意とする半導体メーカーから別々にチップで供給してもらい、これらをＭＣＭ化することもできる等の優れた特徴を有している。   In addition, there are few cases where heterogeneous LSI chips mounted on the MCM are all supplied from the same semiconductor manufacturer, and SRAM, flash memory, microcomputer, and CPU (central processing unit) are separately chipped from semiconductor manufacturers that are good at each. It has excellent characteristics such as being able to be supplied in the form of MCM.

上記した先願発明の半導体チップ３の再配置配線を疑似ウェーハ２９上で行う場合、例えば図３７〜図３８のような方法で行うことができる。   When the rearrangement wiring of the semiconductor chip 3 according to the invention of the prior application is performed on the pseudo wafer 29, it can be performed, for example, by a method as shown in FIGS.

図３７（ａ）は、上記した図３６（ｆ）の下図（一部の拡大図）を示す。即ち、疑似ウェーハ２９を構成する保護物質としての樹脂４により、側面及び裏面を覆われて一体化された半導体チップ３上に、Ａｌからなる電極パッド５（以下、電極と称する。）が配され、この電極５が露出するようにパッシベーション膜８が形成されている。   Fig.37 (a) shows the lower figure (partially enlarged view) of said FIG.36 (f). That is, an electrode pad 5 (hereinafter referred to as an electrode) made of Al is disposed on the semiconductor chip 3 that is integrated with the side surface and the back surface thereof being covered with the resin 4 as a protective substance constituting the pseudo wafer 29. A passivation film 8 is formed so that the electrode 5 is exposed.

この後に形成する配線はセミアディティブ法により形成されるが、簡略して図示する。まず、図３７（ｂ）に示すように、パッシベーション膜８を被覆するように層間絶縁膜９を形成後に、図３７（ｃ）に示すように、上面の全面にめっき用の電極となるシードメタルとして、Ａｌと密着性の良いＴｉのスパッタ膜１０を形成する。   The wiring to be formed thereafter is formed by a semi-additive method, but is simply illustrated. First, as shown in FIG. 37 (b), after forming an interlayer insulating film 9 so as to cover the passivation film 8, as shown in FIG. 37 (c), a seed metal serving as an electrode for plating is formed on the entire upper surface. Then, a sputtered film 10 of Ti having good adhesion with Al is formed.

次に、図３７（ｄ）に示すように、スパッタ膜１０上にフォトリソグラフィ技術によってフォトレジスト膜１１を形成後に、図３８（ｅ）に示すように、Ｃｕを用いて配線となる電解めっき膜１２Ａを形成する。これにより、Ａｌと密着性の良いＴｉをシードメタルとすることにより、Ｔｉのスパッタ膜１０上にＣｕを容易にめっきすることができる。   Next, as shown in FIG. 37 (d), after forming a photoresist film 11 on the sputtered film 10 by a photolithography technique, as shown in FIG. 38 (e), an electrolytic plating film that becomes wiring using Cu, as shown in FIG. 12A is formed. Thereby, Cu can be easily plated on the Ti sputtered film 10 by using Ti having good adhesion to Al as the seed metal.

次に、図３８（ｆ）に示すように、フォトレジスト膜１１を除去し、このフォトレジスト膜１１下のスパッタ膜１０をウェットエッチング等で除去することにより、再配置した配線１２が形成される。   Next, as shown in FIG. 38F, the photoresist film 11 is removed, and the sputtered film 10 under the photoresist film 11 is removed by wet etching or the like, whereby the rearranged wiring 12 is formed. .

次に、図３８（ｇ）に示すように、上部の全面を保護膜１３で被覆後に、図３８（ｈ）に示すように、保護膜１３に配線１２との接続孔６を形成し、外部端子１５を露出させる。   Next, as shown in FIG. 38 (g), the entire upper surface is covered with the protective film 13, and then, as shown in FIG. The terminal 15 is exposed.

上記の方法により、同一の疑似ウェーハ２９上に複数個又は複数種のチップ部品を並列に配し、ＭＣＭの回路を形成するための再配置配線をウェーハレベルで一度に行うことができる。しかも、先願発明は、半導体ウェーハから切り出した良品チップのみを選んで再配置し、その側面及び裏面を樹脂で覆って一体化し、更に特性検査を行って、１００％良品チップが配された疑似ウェーハ上で、これらのチップに対して一括してチップ間の再配置配線を行うことができ、ＭＣＭを疑似ウェーハ段階で形成することができる等の優れた特長を有している。   By the above method, a plurality of or a plurality of types of chip parts can be arranged in parallel on the same pseudo-wafer 29, and rearrangement wiring for forming an MCM circuit can be performed at a wafer level at a time. In addition, the invention of the prior application selects only the non-defective chips cut out from the semiconductor wafer, rearranges them, covers and integrates the side and back surfaces with a resin, and further conducts a characteristic inspection, and the pseudo chip in which 100% non-defective chips are arranged. On the wafer, it is possible to perform rearrangement wiring between the chips collectively on these chips, and to have an excellent feature such that the MCM can be formed at the pseudo wafer stage.

特開平７−２０２１１５号（第５頁左欄、図１及び図３）Japanese Patent Laid-Open No. 7-202115 (left column of page 5, FIGS. 1 and 3) 特開平１１−３３０３５０号（第６頁右欄、図５及び図６）Japanese Patent Laid-Open No. 11-330350 (right column on page 6, FIGS. 5 and 6) 特開２００１−３０８１１６号（第５頁左欄、第７頁右欄及び図２）JP 2001-308116 (Left column on page 5, left column on page 7, and FIG. 2)

しかしながら、従来は先願発明においても、チップ部品の外部端子が半導体装置の表面側にしか形成されていないため、裏面側で外部機器等との接続ができないという問題や、積層構造のＭＣＭを形成できないという問題があることから、本発明者はこれらの問題を解決すべく、出願番号２００３−１３８１３６号（平成１５年５月１６日出願）により提案したところである。   However, in the prior invention as well, since the external terminals of the chip component are formed only on the front surface side of the semiconductor device, there is a problem that the back surface cannot be connected to an external device or the like, and the MCM having the laminated structure is formed. Since there is a problem that it cannot be performed, the present inventor has proposed by the application number 2003-138136 (filed on May 16, 2003) to solve these problems.

しかし、なおも改良の余地があることに気付き、本発明者は鋭意検討を重ねた結果、更に前進的な方策を見出し本発明に到達したものである。   However, the present inventor has found that there is still room for improvement, and as a result of intensive studies, the present inventor has found a further forward measure and has reached the present invention.

そこで本発明の目的は、チップ部品の電極が精度の良い接続構造にて簡単かつ確実に裏面に導通でき、複数のチップ部品間及び外部機器との接続が容易な外部端子を有する半導体装置及びその製造方法、疑似ウェーハ及びその製造方法、並びに半導体装置の実装構造を低コストにて提供することにある。   SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having external terminals in which the electrodes of chip components can be easily and surely connected to the back surface with a precise connection structure, and can be easily connected between a plurality of chip components and external devices, and A manufacturing method, a pseudo wafer, a manufacturing method thereof, and a semiconductor device mounting structure are provided at a low cost.

即ち、本発明は、一方の面側に電極が設けられ、この電極面以外の少なくとも側面が保護物質層で覆われているチップ部品を有する半導体装置において、
前記チップ部品の少なくとも側方に絶縁物質層が被着され,
前記絶縁物質層をこの両面に貫通して形成された貫通孔に、第１の導電材が設けられ 、
前記電極と前記第一の導電材とが別の導電材を介して接続され、
前記電極が少なくとも、前記一方の面とは反対側の他方の面側に電気的に取り出され ている
ことを特徴とする、半導体装置（以下、本発明の半導体装置と称する。）に係るものである。 That is, the present invention provides a semiconductor device having a chip component in which an electrode is provided on one surface side and at least a side surface other than the electrode surface is covered with a protective material layer.
An insulating material layer is deposited on at least the sides of the chip component;
A first conductive material is provided in a through hole formed through the insulating material layer on both sides,
The electrode and the first conductive material are connected via another conductive material,
The electrode is electrically taken out to at least the other surface side opposite to the one surface, and relates to a semiconductor device (hereinafter referred to as a semiconductor device of the present invention). is there.

また、本発明は、一方の面側に電極が設けられ、この電極面以外の少なくとも側面が保護物質層で覆われているチップ部品を有する半導体装置を製造する方法において、
前記チップ部品を配するための欠除部を有し、かつ両面間に形成した貫通孔に第１の 導電材を設けた絶縁物質層を作製する工程と、
前記絶縁物質層を支持体上に固定する工程と、
前記電極面の側にて前記チップ部品を前記欠除部内にて支持体上に固定する工程と、
前記チップ部品及び前記絶縁物質層の少なくとも側面を前記保護物質層によって覆う 工程と、
前記保護物質層によって前記チップ部品と前記絶縁物質層とが一体化されてなる疑似 ウェーハを前記支持体から分離して疑似ウェーハを作製する工程と、
前記疑似ウェーハにおいて、前記チップ部品の前記電極を前記第１の導電材とは別の 導電材によって前記第１の導電材に接続する工程と、
前記一方の面とは反対側の他方の面とのうち、少なくとも前記他方の面に前記電極を 電気的に取り出す工程と、
複数の前記チップ部品間で、前記絶縁物質層又は前記保護物質層を切断して各半導体 装置に個片化する工程と
を有することを特徴とする、半導体装置の製造方法（以下、本発明の半導体装置の第１の製造方法と称する。）に係るものである。 Further, the present invention provides a method of manufacturing a semiconductor device having a chip component in which an electrode is provided on one surface side and at least a side surface other than the electrode surface is covered with a protective material layer.
A step of producing an insulating material layer having a first conductive material in a through-hole formed between both surfaces and having a notch for arranging the chip component;
Fixing the insulating material layer on a support;
Fixing the chip component on the support on the electrode surface side in the notch, and
Covering at least side surfaces of the chip component and the insulating material layer with the protective material layer;
Separating a pseudo wafer in which the chip component and the insulating material layer are integrated by the protective substance layer from the support, and producing a pseudo wafer;
In the pseudo-wafer, connecting the electrode of the chip component to the first conductive material by a conductive material different from the first conductive material;
Electrically extracting the electrode from at least the other surface of the other surface opposite to the one surface;
A step of cutting the insulating material layer or the protective material layer into a plurality of individual semiconductor devices between the plurality of chip parts, and a method for manufacturing a semiconductor device (hereinafter referred to as the present invention). This is referred to as a first manufacturing method of a semiconductor device.

また、本発明は、一方の面側に電極が設けられ、この電極面以外の少なくとも側面が保護物質層で覆われているチップ部品の複数個が、前記保護物質層を介して互いに一体化されてなる疑似ウェーハにおいて、
前記チップ部品の少なくとも側方に絶縁物質層が被着され、
前記絶縁物質層をこの両面に貫通して形成された貫通孔に、第１の導電材が設けられ 、
前記電極と前記第一の導電材とが別の導電材を介して接続され、
前記電極が少なくとも、前記一方の面とは反対側の他方の面側に電気的に取り出され ている
ことを特徴とする、疑似ウェーハ（以下、本発明の疑似ウェーハと称する。）に係るものである。 In the present invention, a plurality of chip parts each having an electrode provided on one surface side and covered with a protective material layer at least other side surfaces than the electrode surface are integrated with each other via the protective material layer. In the pseudo wafer
An insulating material layer is deposited on at least the sides of the chip component;
A first conductive material is provided in a through hole formed through the insulating material layer on both sides,
The electrode and the first conductive material are connected via another conductive material,
The electrode is electrically taken out at least on the other surface side opposite to the one surface, and is related to a pseudo wafer (hereinafter referred to as a pseudo wafer of the present invention). is there.

また、本発明は、一方の面側に電極が設けられ、この電極面以外の少なくとも側面が保護物質層で覆われているチップ部品の複数個が、前記保護物質層を介して互いに一体化されてなる疑似ウェーハを製造する方法において、
前記チップ部品を配するための欠除部を有し、かつ両面間に形成した貫通孔に第１の 導電材を設けた絶縁物質層を作製する工程と、
前記絶縁物質層を支持体上に固定する工程と、
前記電極面の側にて前記チップ部品を前記欠除部内にて支持体上に固定する工程と、
前記チップ部品及び前記絶縁物質層の少なくとも側面を前記保護物質層によって覆う 工程と、
前記保護物質層によって前記チップ部品と前記絶縁物質層とが一体化されてなる疑似 ウェーハを前記支持体から分離する工程と、
前記チップ部品の前記電極を前記第１の導電材とは別の導電材によって前記第１の導 電材に接続する工程と、
前記一方の面とは反対側の他方の面とのうち、少なくとも前記他方の面に前記電極を 電気的に取り出す工程と
を有することを特徴とする、疑似ウェーハの製造方法（以下、本発明の疑似ウェーハの第１の製造方法と称する。）に係るものである。 In the present invention, a plurality of chip parts each having an electrode provided on one surface side and covered with a protective material layer at least other side surfaces than the electrode surface are integrated with each other via the protective material layer. In the method of manufacturing the pseudo wafer,
A step of producing an insulating material layer having a first conductive material in a through-hole formed between both surfaces and having a notch for arranging the chip component;
Fixing the insulating material layer on a support;
Fixing the chip component on the support on the electrode surface side in the notch, and
Covering at least side surfaces of the chip component and the insulating material layer with the protective material layer;
Separating the pseudo wafer in which the chip component and the insulating material layer are integrated by the protective material layer from the support;
Connecting the electrode of the chip component to the first conductive material by a conductive material different from the first conductive material;
And a step of electrically extracting the electrode from at least the other surface of the other surface opposite to the one surface. This is referred to as a first pseudo wafer manufacturing method).

また、本発明は、一方の面側に電極が設けられ、この電極面以外の少なくとも側面が保護物質層で覆われているチップ部品を有する半導体装置を製造する方法において、
支持体上に前記チップ部品を固定する工程と、
前記チップ部品の側方にて第１の導電材を前記支持体上に固定する工程と、
前記第１の導電材を保護物質材料に埋設する工程と、
前記保護物質材料を前記チップ部品の側面に被着して前記保護物質層を形成する工程 と、
前記保護物質層によって前記チップ部品が一体化されてなる疑似ウェーハを前記支持 体から分離する工程と、
前記疑似ウェーハにおいて、前記チップ部品の前記電極を前記第１の導電材とは別の 導電材によって前記第１の導電材に接続する工程と、
前記一方の面とこれとは反対側の他方の面とのうち、少なくとも前記他方の面に前記 電極を電気的に取り出す工程と、
複数の前記チップ部品間で、前記保護物質層を切断して各半導体装置に個片化する工 程と
を有することを特徴とする、半導体装置の製造方法（以下、本発明の半導体装置の第２の製造方法と称する。）に係るものである。 Further, the present invention provides a method of manufacturing a semiconductor device having a chip component in which an electrode is provided on one surface side and at least a side surface other than the electrode surface is covered with a protective material layer.
Fixing the chip component on a support;
Fixing the first conductive material on the support at the side of the chip component;
Embedding the first conductive material in a protective material;
Depositing the protective substance material on the side surface of the chip component to form the protective substance layer;
Separating the pseudo wafer in which the chip parts are integrated by the protective substance layer from the support;
In the pseudo-wafer, connecting the electrode of the chip component to the first conductive material by a conductive material different from the first conductive material;
A step of electrically taking out the electrode to at least the other surface of the one surface and the other surface on the opposite side;
A method of manufacturing a semiconductor device (hereinafter referred to as a semiconductor device manufacturing method according to the present invention), comprising: a step of cutting the protective material layer into a plurality of individual semiconductor devices between the plurality of chip components. 2).

また、本発明は、一方の面側に電極が設けられ、この電極面以外の少なくとも側面が保護物質層で覆われているチップ部品の複数個が、前記保護物質層を介して互いに一体化されてなる疑似ウェーハを製造する方法において、
支持体上に前記チップ部品を固定する工程と、
前記チップ部品の側方にて第１の導電材を前記支持体上に固定する工程と、
前記第１の導電材を保護物質材料に埋設する工程と、
前記保護物質材料を前記チップ部品の側面に被着して前記保護物質層を形成する工程 と、
前記保護物質層によって前記チップ部品が一体化されてなる疑似ウェーハを前記支持 体から分離する工程と、
前記疑似ウェーハにおいて、前記チップ部品の前記電極を前記第１の導電材とは別の 導電材によって前記第１の導電材に接続する工程と、
前記一方の面とこれとは反対側の他方の面とのうち、少なくとも前記他方の面に前記 電極を電気的に取り出す工程と
を有することを特徴とする、疑似ウェーハの製造方法（以下、本発明の疑似ウェーハの第２の製造方法と称する。）に係るものである。 In the present invention, a plurality of chip parts each having an electrode provided on one surface side and covered with a protective material layer at least other side surfaces than the electrode surface are integrated with each other via the protective material layer. In the method of manufacturing the pseudo wafer,
Fixing the chip component on a support;
Fixing the first conductive material on the support at the side of the chip component;
Embedding the first conductive material in a protective material;
Depositing the protective substance material on the side surface of the chip component to form the protective substance layer;
Separating the pseudo wafer in which the chip parts are integrated by the protective substance layer from the support;
In the pseudo-wafer, connecting the electrode of the chip component to the first conductive material by a conductive material different from the first conductive material;
A method of manufacturing a pseudo wafer (hereinafter referred to as a book), comprising: a step of electrically extracting the electrode from at least one of the one surface and the other surface opposite to the one surface. This is referred to as a second method for manufacturing a pseudo wafer of the invention.

また、本発明は、上記した本発明の半導体装置が、少なくとも前記他方の面側にてプリント配線板に接続されている、半導体装置の実装構造（以下、本発明の実装構造と称する。）に係るものである。   Also, the present invention provides a semiconductor device mounting structure (hereinafter referred to as a mounting structure of the present invention) in which the semiconductor device of the present invention is connected to a printed wiring board at least on the other surface side. It is concerned.

本発明によれば、一方の面側に電極が設けられたチップ部品の複数個が疑似ウェーハ上で一括処理され、少なくともその側方に絶縁物質層が被着されているので、チップ化後のハンドリング時にはチップ部品が保護され、ハンドリングが容易となると共に、少なくとも絶縁物質層の位置で切断して個片化できるため、切断時にチップ部品が亀裂や歪みの如きダメージを受けることがない。   According to the present invention, since a plurality of chip parts having electrodes provided on one surface side are collectively processed on the pseudo wafer, and an insulating material layer is deposited on at least the side thereof, The chip component is protected during handling, and handling becomes easy. At the same time, the chip component can be cut and separated into pieces at least at the position of the insulating material layer, so that the chip component is not damaged such as cracks or distortion during cutting.

そしてこの構造において、絶縁物質層に第１の導電材を位置精度良く設けることができ、この第１の導電材を介して電極が少なくとも一方の面とは反対側の他方の面に電気的に取り出されているので、この第１の導電材に対して別の導電材を介して電極を接続するだけで、簡単かつ確実に電極を他方の面側に導通させることができ、このチップ部品を外部機器等へ実装する際には、他方の面側へ第１の導電材を介しての接続も可能であると共に、第１の導電材から別の導電材を介して再配置し、任意の位置でプリント配線板等に接続して実装できるため、設計の自由度が大きくなると共に、積層構造の半導体装置も可能になる。   In this structure, the insulating material layer can be provided with the first conductive material with high positional accuracy, and the electrode is electrically connected to at least the other surface opposite to the one surface via the first conductive material. Since it is taken out, it is possible to easily and reliably conduct the electrode to the other surface side simply by connecting the electrode to the first conductive material via another conductive material. When mounting on an external device or the like, it is possible to connect to the other surface side via the first conductive material, and to re-arrange from the first conductive material via another conductive material. Since it can be mounted and connected to a printed wiring board or the like at a position, the degree of freedom in design is increased and a semiconductor device having a laminated structure is also possible.

上記した本発明における半導体装置及びその第１と第２の製造方法、疑似ウェーハ及びその第１と第２の製造方法、実装構造においては、前記チップ部品の側方において、前記保護物質層とは別の前記絶縁物質層の前記貫通孔に、前記第１の導電材が設けられていることが、電極との接続が簡単に行え、電極とは反対側の面に電極を確実に導通できる点で望ましい。   In the semiconductor device and the first and second manufacturing methods thereof, the pseudo wafer and the first and second manufacturing methods, and the mounting structure in the present invention described above, the side of the chip component is the protective material layer. The fact that the first conductive material is provided in the through hole of another insulating material layer can be easily connected to the electrode, and can reliably conduct the electrode to the surface opposite to the electrode. Is desirable.

この場合、前記チップ部品の側方において、前記絶縁物質層を兼ねる前記保護物質層に設けられた前記貫通孔に前記第１の導電材が設けられるようにしてもよい。   In this case, on the side of the chip component, the first conductive material may be provided in the through hole provided in the protective material layer that also serves as the insulating material layer.

即ち、保護物質層が絶縁物質層を兼ねる場合には、熱可塑性の如き材料を用い、前記チップ部品を配するための欠除部を有し、かつ両面間に形成した貫通孔に前記第１の導電材を設けた前記保護物質材料層を作製する工程と、前記保護物質材料層を支持体上に固定する工程と、前記電極面の側にて前記チップ部品を前記欠除部内にて支持体上に固定する工程と、前記保護物質材料層を加熱により流動化させ、前記チップ部品の少なくとも側面を前記保護物質層によって覆う工程とを有することにより、前記と同様な機能の半導体装置を形成することができる。   That is, when the protective substance layer also serves as the insulating substance layer, a material such as thermoplastic is used, and the first hole is formed in the through-hole formed between both surfaces having a notch for arranging the chip component. A step of producing the protective substance material layer provided with the conductive material, a step of fixing the protective substance material layer on the support, and supporting the chip component in the notch portion on the electrode surface side. Forming a semiconductor device having the same function as described above by having a step of fixing on the body and a step of fluidizing the protective substance material layer by heating and covering at least a side surface of the chip component with the protective substance layer can do.

また、前記他方の面側において前記疑似ウェーハの前記保護物質層を部分的に除去して、前記第１の導電材を露出させ、更に前記他方の面側又は／及び前記一方の面側に形成された外部端子に取り出すことが望ましい。   Further, the protective material layer of the pseudo wafer is partially removed on the other surface side to expose the first conductive material, and further formed on the other surface side and / or the one surface side. It is desirable to take out to the external terminal.

この場合、前記第１の導電材が、これとは別の配線を介して前記外部端子に取り出されていることが、外部端子を任意の位置に形成し易い点で望ましい。   In this case, it is desirable that the first conductive material is taken out to the external terminal via a different wiring from the viewpoint that the external terminal can be easily formed at an arbitrary position.

また、前記チップ部品の前記他方の面側の少なくとも一部を露出させることにより、チップ部品が放熱し易くなり、実装基板等への実装時等にチップ部品が熱ストレスを緩和される点で望ましい。   In addition, by exposing at least a part of the other surface side of the chip component, the chip component is easy to dissipate heat, which is desirable in that the chip component can reduce thermal stress when mounted on a mounting substrate or the like. .

そして、特性測定により良品と判定された前記チップ部品を有する前記疑似ウェーハを作製し、更に前記疑似ウェーハの状態において前記チップ部品の特性測定を行い、良品のチップ部品又はチップ状電子部品を選択することが、歩留りを高める点で望ましい。   Then, the pseudo-wafer having the chip part determined to be non-defective by characteristic measurement is manufactured, and the characteristic of the chip part is measured in the state of the pseudo wafer, and the non-defective chip part or chip-shaped electronic part is selected. This is desirable in terms of increasing the yield.

これにより、上記した半導体装置を製造するための疑似ウェーハを得て、これを個片化した前記半導体装置の複数個が、前記一方の面側及び前記他方の面側間での接続下で積層された、ＭＣＭの如きモジュールを構成することができる。   Thus, a pseudo wafer for manufacturing the semiconductor device described above is obtained, and a plurality of the semiconductor devices obtained by dividing the pseudo wafer are stacked under the connection between the one surface side and the other surface side. A module such as MCM can be configured.

次に、上記した本発明の好ましい実施の形態を図面参照下で具体的に説明する。   Next, the preferred embodiments of the present invention will be described in detail with reference to the drawings.

実施の形態１
図１は、本実施の形態の半導体装置５０の概略断面図を示す。図示の如く、チップ３が、その側面を保護物質層としての樹脂４及び、この樹脂４の外側に隣接した有機系絶縁性樹脂からなるビア付き基板２０に囲まれている（図８参照）。そして、ビア付き基板２０には、その上下面に対してほぼ垂直に配された導電プラグ１９が予設されており、チップ３の電極５が、導出された配線２４を介してプラグ１９の上端に接続され、電極５の反対側へ導通されている。 Embodiment 1
FIG. 1 is a schematic cross-sectional view of a semiconductor device 50 according to the present embodiment. As shown in the drawing, the chip 3 is surrounded by a substrate 4 with vias made of a resin 4 as a protective material layer and an organic insulating resin adjacent to the outside of the resin 4 (see FIG. 8). The via-attached substrate 20 is preliminarily provided with a conductive plug 19 arranged substantially perpendicular to the upper and lower surfaces thereof, and the electrode 5 of the chip 3 is connected to the upper end of the plug 19 via the derived wiring 24. To the opposite side of the electrode 5.

チップ３の裏面４２は全体が露出しており、これと同一面上にビア付き基板２０のプラグ１９の下端面が露出し、この露出部が裏面側４２の外部端子２６となり、これと対向する上方位置で配線２４に対する接続孔１６が開口されて表面側４１の外部端子２５が形成され、電極５の外部端子２５、２６が、プラグ１９を介して接続され、半導体装置５０の両面に形成されている。   The entire back surface 42 of the chip 3 is exposed, and the lower end surface of the plug 19 of the substrate 20 with vias is exposed on the same surface, and this exposed portion becomes the external terminal 26 on the back surface side 42 and faces this. The connection hole 16 for the wiring 24 is opened at the upper position to form the external terminal 25 on the surface side 41, and the external terminals 25 and 26 of the electrode 5 are connected via the plug 19 and formed on both surfaces of the semiconductor device 50. ing.

この構造により、チップ３の裏面４２が剥き出しになるので放熱性が良いため、実装時にチップ３が熱ストレスなしで、裏面側４２の外部端子２６を外部機器の外部端子にはんだバンプ等を介して容易に接続が可能であり、例えばプリント基板等へフェイスアップで実装できる等のメリットを有している。   With this structure, since the back surface 42 of the chip 3 is exposed, heat dissipation is good. Therefore, the chip 3 is not subjected to thermal stress during mounting, and the external terminals 26 on the back surface side 42 are connected to external terminals of the external device via solder bumps or the like. It can be easily connected and has an advantage that it can be mounted face-up on, for example, a printed circuit board.

図２〜図８により、本実施の形態の半導体装置５０の作製プロセスを説明する。なお、以下のプロセス及び後述する他の実施の形態等においては、例えば、接続孔にＣｕの埋め込みに際してはＴａ等によるバリア膜が形成され、また埋め込み後はＣＭＰによる表面研磨が行われ、またレジストマスクはフォトリソグラフィ技術等の工程を経て形成され、またエッチングは必要なエッチングガス等を用いて行われるが単にエッチングと称し、これらの処理がなされることを前提とし、各プロセスにおいてはこの説明を省略することがある。   A manufacturing process of the semiconductor device 50 of the present embodiment will be described with reference to FIGS. In the following processes and other embodiments to be described later, for example, a barrier film made of Ta or the like is formed in the connection hole when Cu is buried, and after the filling, surface polishing is performed by CMP, and the resist is resisted. The mask is formed through a process such as a photolithography technique, and etching is performed using a necessary etching gas or the like. However, it is simply referred to as etching, and it is assumed that these processes are performed. May be omitted.

まず図２（ａ）に示すように、支持体（例えば、石英又はガラスからなる基板）１７上に、例えば紫外線照射により粘着力が低下する粘着シートからなる固定材２２を貼り付け、この上に後述するチップ配置場所として欠除部２３を形成可能な成形型５５を載せ、その空洞部５５ａに液状の有機絶縁樹脂材料（以下、絶縁物質層と称する。）を射出し、冷却して固化する。   First, as shown in FIG. 2 (a), a fixing material 22 made of an adhesive sheet whose adhesive strength is reduced by ultraviolet irradiation, for example, is pasted on a support (for example, a substrate made of quartz or glass) 17, and on this, A molding die 55 capable of forming the notch 23 is placed as a chip placement location, which will be described later, and a liquid organic insulating resin material (hereinafter referred to as an insulating material layer) is injected into the cavity 55a, and then cooled and solidified. .

これにより、図２（ｂ）に示すように成形型５５を除去後に、欠除部２３部及びチップ間領域２０ａが所定間隔で形成された絶縁物質層からなるビア付き基板２０の原型（図３参照）が形成される。   Thus, as shown in FIG. 2B, after removing the molding die 55, the prototype of the substrate 20 with vias (FIG. 3) made of an insulating material layer in which the notch portion 23 and the inter-chip region 20a are formed at predetermined intervals. Reference) is formed.

次に図２（ｃ）に示すように、チップ間領域２０ａにビアホール３８を形成する。このビアホール３８は、例えば全部を一度に形成可能な突起付きの押し型、又はレーザ加工やドリル等により形成できる。   Next, as shown in FIG. 2C, a via hole 38 is formed in the inter-chip region 20a. The via hole 38 can be formed by, for example, a pressing die with a protrusion that can be formed all at once, laser processing, drilling, or the like.

次に図２（ｄ）に示すように、例えばスキージ５６を用いて銀ペースト１８をビアホール３８内に充填することにより、プラグ１９が形成され、絶縁物質層間をこの両面に貫通した第１の導電材としてのプラグ１９を有するビア付き基板２０が形成される。   Next, as shown in FIG. 2D, the plug 19 is formed by filling the via hole 38 with the silver paste 18 using, for example, a squeegee 56, and the first conductive material penetrating the both sides of the insulating material layer. A substrate 20 with a via having a plug 19 as a material is formed.

次に図２（ｅ）に示すように、支持体１７の裏面側に紫外線Ｌを照射して固定材２２の粘着力を弱め、ビア付き基板２０を剥離することにより、この平面図として示した図３のような表面を有するビア付き基板２０が完成する。   Next, as shown in FIG. 2 (e), the back surface side of the support 17 is irradiated with ultraviolet rays L to weaken the adhesive strength of the fixing material 22, and the via-attached substrate 20 is peeled off to show this as a plan view. A substrate 20 with vias having a surface as shown in FIG. 3 is completed.

図４〜図８は、上記のように形成したビア付き基板２０の欠除部２３の位置にチップ３を配置し、半導体装置５０を形成するプロセスを示す図である。 4 to 8 are diagrams showing a process of forming the semiconductor device 50 by disposing the chip 3 at the position of the notch portion 23 of the via-formed substrate 20 formed as described above.

まず、図４（ａ）に示すように、例えば石英からなる支持基板２１上に、紫外線照射により粘着力が低下する例えばアクリル系の粘着シートを固定材２２として貼り付ける。   First, as shown in FIG. 4A, for example, an acrylic pressure-sensitive adhesive sheet whose adhesive strength is reduced by ultraviolet irradiation is attached as a fixing material 22 on a support substrate 21 made of, for example, quartz.

次に図４（ｂ）に示すように、固定材２２上の所定位置に、電極５を下向きにしてチップ３を貼り付ける。このチップ３は先願発明（図３６参照）と同様に、特性測定により良品ベアチップと判定されたものを用いる。   Next, as shown in FIG. 4B, the chip 3 is attached to a predetermined position on the fixing member 22 with the electrode 5 facing downward. As the chip 3, a chip determined to be a good bare chip by characteristic measurement is used as in the prior invention (see FIG. 36).

次に図４（ｃ）に示すように、先に別途形成したビア付き基板２０を貼り付ける。ビア付き基板２０の欠除部２３はチップ３の外側寸法よりも大きく形成されており、図示のようにチップ３の周囲にすき間２３ａが形成される。この場合、支持基板２１への貼り付けは、上記とは逆に、ビア付き基板２０を貼り付けた後にチップ３を貼り付けてもよい。   Next, as shown in FIG. 4C, a substrate 20 with a via formed separately is attached. The notched portion 23 of the substrate 20 with vias is formed larger than the outer dimension of the chip 3, and a gap 23 a is formed around the chip 3 as shown in the figure. In this case, the chip 3 may be pasted on the support substrate 21 after the via-attached substrate 20 is pasted, contrary to the above.

次に図４（ｄ）に示すように、チップ３及びビア付き基板２０上の全面に、保護物質層として有機系絶縁性樹脂（例えばエポキシ系の樹脂、以下、単に樹脂と称する。）４をスピンコート法又は印刷法により、均一に塗布する。これにより上記したすき間２３ａ内にも樹脂４が充填され、チップ３とビア付き基板２０とが樹脂４を介して一体化される。   Next, as shown in FIG. 4D, an organic insulating resin (for example, an epoxy resin, hereinafter simply referred to as a resin) 4 is used as a protective material layer on the entire surface of the chip 3 and the substrate 20 with vias. Apply uniformly by spin coating or printing. As a result, the resin 4 is also filled in the gaps 23 a described above, and the chip 3 and the substrate 20 with vias are integrated via the resin 4.

次に図４（ｅ）に示すように、支持基板２１の裏面側から紫外線Ｌを照射して固定材２２の粘着力を弱め、樹脂４で裏面を覆われた状態のチップ３及びビア付き基板２０を剥離する。これにより、チップ３の周辺にビア付き基板２０が配置された状態の疑似ウェーハ２９を形成できる。   Next, as shown in FIG. 4 (e), the chip 3 and the substrate with vias in a state where the back surface of the support substrate 21 is irradiated with ultraviolet rays L to weaken the adhesive force of the fixing material 22 and the back surface is covered with the resin 4. 20 is peeled off. Thereby, the pseudo wafer 29 in a state where the substrate 20 with vias is arranged around the chip 3 can be formed.

図５（ｆ）は、剥離後の疑似ウェーハ２９をひっくり返した状態であり、図示の如く、チップ３とビア付き基板２０とが裏面を樹脂４で覆われ、一体化されている。   FIG. 5F shows a state in which the peeled pseudo wafer 29 is turned over. As shown in the figure, the chip 3 and the substrate with via 20 are covered with the resin 4 and integrated.

次に図５（ｇ）に示すように、層間膜９をチップ３の電極５を開口するように所定のパターンで形成する。層間膜９は感光性絶縁樹脂等を使用し、液状のものをスピンコートして塗布するか、又はドライフィルムをラミネーターで貼り付ける等により形成する。   Next, as shown in FIG. 5G, the interlayer film 9 is formed in a predetermined pattern so as to open the electrode 5 of the chip 3. The interlayer film 9 is formed by using a photosensitive insulating resin or the like and spin-coating a liquid material or applying a dry film with a laminator.

次にチップ３の電極５をプラグ１９に接続するための引き出し配線を形成するが、この配線は、例えば次の如きプロセスで行うセミアディティブ法（スパッタ膜形成→めっきレジスト形成→めっき→めっきレジスト剥離→スパッタ膜エッチング）等で形成する。   Next, a lead-out wiring for connecting the electrode 5 of the chip 3 to the plug 19 is formed. This wiring is, for example, a semi-additive method (sputtered film formation → plating resist formation → plating → plating resist peeling) performed by the following process. → Sputtered film etching).

まず図５（ｈ）に示すように、層間膜９上にめっきの電極となるシードメタルとして、Ａｌ電極５との密着性の良いＴｉ等によりスパッタ膜１０を形成後、図５（ｉ）に示すように、この上の全面に、例えばポジ型のフォトレジスト膜１１Ａを形成する。   First, as shown in FIG. 5H, a sputtered film 10 is formed on the interlayer film 9 as a seed metal to be a plating electrode by using Ti or the like having good adhesion to the Al electrode 5, and then in FIG. 5I. As shown, a positive photoresist film 11A, for example, is formed on the entire surface.

次に、図５（ｊ）に示すように、フォトレジスト膜１１Ａ上にパターン開口部３６を有する露光マスク３５を配置し、フォトレジスト膜１１Ａを露光する。この露光光３７によってマスク３５のパターン開口部３６下のレジスト膜１１Ａが硬化される。   Next, as shown in FIG. 5J, an exposure mask 35 having a pattern opening 36 is disposed on the photoresist film 11A, and the photoresist film 11A is exposed. The resist film 11A under the pattern opening 36 of the mask 35 is cured by the exposure light 37.

次に図６（ｋ）に示すように、露光後のフォトレジスト膜１１Ａを現像することにより、硬化部がレジストマスク１１として形成される。   Next, as illustrated in FIG. 6K, the exposed photoresist film 11 </ b> A is developed to form a cured portion as the resist mask 11.

次に図６（ｌ）に示すように、Ｃｕの電解めっきを行うことにより、レジストマスク１１以外の領域にめっき膜１２Ａを形成する。   Next, as shown in FIG. 6L, a plated film 12A is formed in a region other than the resist mask 11 by performing electrolytic plating of Cu.

次に図６（ｍ）に示すように、レジストマスク１１を剥離除去後に、レジストマスク１１下のスパッタ膜１０をウェットエッチング等で除去することにより、再配置した別の導電材としての配線２４が形成される。図８はこの状態を簡略図示した平面図であり、図８に示すように、ビア付き基板２０に予設したプラグ１９に対し、チップ３の電極５が配線２４によって接続される。   Next, as shown in FIG. 6M, after the resist mask 11 is peeled and removed, the sputtered film 10 under the resist mask 11 is removed by wet etching or the like, so that the wiring 24 as another conductive material rearranged is obtained. It is formed. FIG. 8 is a plan view schematically showing this state. As shown in FIG. 8, the electrode 5 of the chip 3 is connected to the plug 19 preliminarily provided on the substrate 20 with vias by wiring 24.

次に図７（ｎ）に示すように、配線２４を含む上部の全面に保護膜３０を形成し、プラグ１９上方の保護膜３０に、配線２４との接続孔１６を開口してこの面の外部端子２５を形成する。   Next, as shown in FIG. 7 (n), a protective film 30 is formed on the entire upper surface including the wiring 24, and a connection hole 16 to the wiring 24 is opened in the protective film 30 above the plug 19, and this surface is formed. External terminals 25 are formed.

次に図７（ｏ）に示すように、樹脂４を裏面から研削し、ビア付き基板２０に設けてあるプラグ１９を露出させることにより、この露出部が裏面側の外部端子２６として形成される。樹脂４の研削はＳｉウェーハの裏面研削用のグラインダー等で行うことができる。   Next, as shown in FIG. 7 (o), the resin 4 is ground from the back surface to expose the plug 19 provided on the substrate 20 with vias, whereby this exposed portion is formed as an external terminal 26 on the back surface side. . The resin 4 can be ground with a grinder for grinding the back surface of the Si wafer.

図７（ｏ）及び図８における切断線４５をダイサー等で個片にカット分割することにより、図１に示したように、表面４１及び裏面４２の両面に外部端子２５、２６が配置されたモジュールが疑似ウェーハ２９段階で容易に形成できる。なお、図８では、配線２４を１つのチップ３についてのみ図示したが、他のチップについても同様である（但し、図示省略）。   By cutting and dividing the cutting line 45 in FIG. 7 (o) and FIG. 8 into individual pieces with a dicer or the like, the external terminals 25 and 26 are arranged on both the front surface 41 and the back surface 42 as shown in FIG. Modules can be easily formed in 29 pseudo wafers. In FIG. 8, the wiring 24 is shown only for one chip 3, but the same applies to other chips (however, illustration is omitted).

しかも、良品チップのみを選択して再配置しているので、あたかも全てが良品チップからなる疑似ウェーハ２９に自社製、他社製の区別なく配置し、ウェーハレベルで一括処理が可能であり、低コストにて外部端子を形成できると共に、チップ３を疑似ウェーハから切り出す際に、絶縁物質からなるビア付き基板２０の位置で切断するので、チップ３にダメージ（亀裂、歪み等）を与えることなしで個片化でき、個片化後のハンドリングにおいてもチップが樹脂で保護され、ハンドリングが容易である。   Moreover, since only non-defective chips are selected and rearranged, it is possible to arrange them on the pseudo-wafer 29 made of non-defective chips regardless of whether they are manufactured in-house or from other companies, and batch processing is possible at the wafer level. In addition to forming the external terminals, the chip 3 is cut at the position of the substrate with vias 20 made of an insulating material when the chip 3 is cut out from the pseudo wafer, so that the chip 3 can be individually manufactured without damaging the chip 3 (crack, distortion, etc.). The chip can be singulated, and the chip is protected with resin even in handling after singulation, and handling is easy.

図９〜図１１は、上記のように形成した半導体装置５０の代表的な実装例を示す図であり、上記のようにして疑似ウェーハ段階で外部端子を形成した後に、これを個片化した半導体装置５０をプリント基板３９に搭載した実装例である。   FIGS. 9 to 11 are diagrams showing typical mounting examples of the semiconductor device 50 formed as described above. After forming the external terminals at the pseudo wafer stage as described above, they are separated into pieces. This is an example of mounting the semiconductor device 50 on the printed circuit board 39.

図９はその一例を示す。本実施の形態による半導体装置５０は、表面４１側に外部端子２５を有し、裏面４２側にも外部端子２６を有するので、プリント基板３９の端子４０に対して、ワイヤボンディングの如き配線を要せず、はんだバンプ３３等を介してフェイスアップにて接続することができると共に、フェイスダウンにて接続することもできる。後述する他の実装例も同様である。   FIG. 9 shows an example. Since the semiconductor device 50 according to the present embodiment has the external terminals 25 on the front surface 41 side and the external terminals 26 on the back surface 42 side, wiring such as wire bonding is required for the terminals 40 of the printed circuit board 39. Instead, it can be connected face-up through the solder bumps 33 and the like, and can also be connected face-down. The same applies to other mounting examples described later.

図１０は、他の実装例（ＭＣＭ）を示すものであり、図示の如く、半導体装置５０を並列に配し、隣接する半導体装置５０との間の配線は、裏面４２側の一方の外部端子２６をプリント基板３９の端子４０を介して接続してもよく、また図１１のように、再配置配線２４で接続することもできる。また、並列に配置する半導体装置の数はこれに限らず、２個以上を配置することができる。また、図示省略したが積層構造にすることもできる。   FIG. 10 shows another mounting example (MCM). As shown in the figure, semiconductor devices 50 are arranged in parallel, and wiring between adjacent semiconductor devices 50 is one external terminal on the back surface 42 side. 26 may be connected via the terminal 40 of the printed circuit board 39, or may be connected by the rearrangement wiring 24 as shown in FIG. The number of semiconductor devices arranged in parallel is not limited to this, and two or more semiconductor devices can be arranged. Although not shown, a laminated structure can also be used.

本実施の形態によれば、半導体装置５０を作製するための疑似ウェーハ２９の形成時に、チップ３の周辺にプラグ１９が位置するように、プラグ１９を予設したビア付き基板２０を別途形成し、これをチップ３と共に支持基板２１上に貼り付けるので、プラグ１９を位置精度良く設けることができ、その後の配線工程においてチップ３の電極５から導出した配線２４をプラグ１９に接続するだけで、簡単かつ確実にチップ３の裏面４２側へ電極５を導通させることができ、表面４１側の外部端子２５と、裏面４２側に露出されたプラグ１９の露出部をこの面の外部端子２６として形成することができる。   According to the present embodiment, when the pseudo wafer 29 for manufacturing the semiconductor device 50 is formed, the via-attached substrate 20 in which the plug 19 is preliminarily formed is separately formed so that the plug 19 is positioned around the chip 3. Since this is affixed to the support substrate 21 together with the chip 3, the plug 19 can be provided with high positional accuracy. In the subsequent wiring process, the wiring 24 led out from the electrode 5 of the chip 3 is simply connected to the plug 19, The electrode 5 can be easily and reliably connected to the back surface 42 side of the chip 3, and the external terminal 25 on the front surface 41 side and the exposed portion of the plug 19 exposed on the back surface 42 side are formed as the external terminals 26 on this surface. can do.

しかも、チップ３の裏面全体が露出しているので、放熱性が良く、実装時に熱ストレスによるチップ３への影響を緩和できる利点があると共に、チップ３が側面を樹脂で保護されているので、この樹脂部で切断して個片化できることにより、切断時にチップ３がダメージを受けることがなく、チップ化後のハンドリングが容易であり、このような構造の半導体装置５０を疑似ウェーハ２９上で一括に形成することにより、両面に外部端子を有する装置を低コストで形成でき、この半導体装置５０により積層構造のＭＣＭを構成することもできる。   Moreover, since the entire back surface of the chip 3 is exposed, heat dissipation is good, and there is an advantage that the influence of the thermal stress on the chip 3 can be reduced during mounting, and the side surface of the chip 3 is protected with a resin. Since the resin portion can be cut into individual pieces, the chip 3 is not damaged at the time of cutting, and handling after the chip formation is easy. The semiconductor device 50 having such a structure is collectively formed on the pseudo wafer 29. Thus, a device having external terminals on both sides can be formed at low cost, and the semiconductor device 50 can constitute an MCM having a laminated structure.

実施の形態２
図１２は、本実施の形態の半導体装置５１の概略断面図を示す。図示の如く、上記した実施の形態１の半導体装置５０に更に加工を施し、裏面４２側に露出させたプラグ１９の露出部１９ａに再配置配線を行い、この配線３４の一部を露出させてこの面の外部端子２７を形成したものである。従って、これ以前の作製プロセスは実施の形態１と同じであるので、そのプロセスの説明等は省略する。 Embodiment 2
FIG. 12 is a schematic cross-sectional view of the semiconductor device 51 of the present embodiment. As shown in the figure, the semiconductor device 50 of the first embodiment described above is further processed, rearranged wiring is performed on the exposed portion 19a of the plug 19 exposed on the back surface 42 side, and a part of the wiring 34 is exposed. The external terminals 27 on this surface are formed. Therefore, since the previous manufacturing process is the same as that of Embodiment Mode 1, description of the process is omitted.

即ち、図１３（ａ）に示すように、既述した図７（ｏ）に対し、チップ３の裏面４２にプラグ１９の露出部１９ａを開口するように層間膜３１を形成する。   That is, as shown in FIG. 13A, the interlayer film 31 is formed on the back surface 42 of the chip 3 so as to open the exposed portion 19a of the plug 19 as compared with FIG.

次に図１３（ｂ）に示すように、プラグ１９に接続した再配置配線３４を形成する。この配線３４も既述したセミアディティブ法（図５（ｈ）〜図６（ｍ）参照）で形成する。   Next, as shown in FIG. 13B, a rearrangement wiring 34 connected to the plug 19 is formed. The wiring 34 is also formed by the above-described semi-additive method (see FIGS. 5H to 6M).

次に図１３（ｃ）に示すように、配線３４を含む裏面４２の全面に保護膜４３を形成し、プラグ１９から導出した配線３４との接続孔３２を開口してこの面の外部端子２７を形成後に、切断線４５位置で切断して個片化することにより、図１２に示した半導体装置５１を形成することができる。   Next, as shown in FIG. 13C, a protective film 43 is formed on the entire back surface 42 including the wiring 34, and a connection hole 32 with the wiring 34 led out from the plug 19 is opened to provide an external terminal 27 on this surface. After forming, the semiconductor device 51 shown in FIG. 12 can be formed by cutting at the cutting line 45 position into pieces.

この半導体装置５１は、裏面４２の外部端子２７が表面４１の外部端子２５と対向する位置に形成されているが、裏面４２の外部端子２７は配線３４が存在する場所で、図１２とは異なる別の位置に形成することもでき、例えば実装するプリント基板の外部端子に合せて設けることもでき、設計の自由度が大きい利点も有している。   In the semiconductor device 51, the external terminal 27 on the back surface 42 is formed at a position facing the external terminal 25 on the front surface 41. However, the external terminal 27 on the back surface 42 is different from FIG. It can be formed at another position, for example, can be provided in accordance with an external terminal of a printed circuit board to be mounted, and has an advantage of a large degree of freedom in design.

しかも、良品チップ３のみを選択して再配置しているので、あたかも全てが良品チップからなる疑似ウェーハ２９に自社製、他社製の区別なく配置し、ウェーハレベルで一括処理が可能であり、低コストにて外部端子を形成できると共に、チップ３を疑似ウェーハから切り出す際に、絶縁物質からなるビア付き基板２０の位置で切断するので、チップ３にダメージ（亀裂、歪み等）を与えることなしで個片化でき、個片化後のハンドリングにおいてもチップが樹脂で保護され、ハンドリングが容易である。   Moreover, since only the non-defective chip 3 is selected and rearranged, it can be arranged on the pseudo-wafer 29 made of non-defective chips regardless of whether it is made by the company or by another company, and can be processed at the wafer level. External terminals can be formed at a low cost, and when the chip 3 is cut out from the pseudo wafer, the chip 3 is cut at the position of the substrate 20 with a via made of an insulating material, so that the chip 3 is not damaged (crack, distortion, etc.). The chip can be singulated, and the chip is protected with resin even in handling after singulation, and handling is easy.

図１４〜１６は、上記のように形成した半導体装置５１の代表的な実装例を示す図であり、疑似ウェーハ２９上で一括処理後に個片化した半導体装置５１をプリント基板３９に実装した例である。   FIGS. 14 to 16 are diagrams showing typical mounting examples of the semiconductor device 51 formed as described above, and an example in which the semiconductor device 51 separated after batch processing on the pseudo wafer 29 is mounted on the printed circuit board 39. It is.

図１４は積層構造の実装例であるが、２層以上に積層することもできる。この半導体装置５１も両面に対向配置した外部端子２５、２７を有しているので、はんだバンプ３３等を介して、それぞれの外部端子同士を接続して積層することができ、プリント基板３９上へフェイスアップで実装することができると共に、フェイスダウンにて接続してもよい。後述する他の実装例も同様である。   FIG. 14 shows a mounting example of a laminated structure, but it can be laminated in two or more layers. Since the semiconductor device 51 also has the external terminals 25 and 27 arranged opposite to each other, the respective external terminals can be connected and laminated via the solder bumps 33 and the like, onto the printed circuit board 39. It can be mounted face up and connected face down. The same applies to other mounting examples described later.

図１５は他の実装例（ＭＣＭ）を示し、半導体装置５１を並列に配し、隣接する半導体装置間の配線は、裏面４２側の外部端子２７をプリント基板３９の端子４０を介して接続してもよく、また、図１６に示すように、表面４１の配線２４の一方を連結（裏面４２側の配線３４を連結してもよい。）することもできる。また、並列配置する半導体装置５１の数は２個以上であってもよい。   FIG. 15 shows another mounting example (MCM), in which the semiconductor devices 51 are arranged in parallel, and the wiring between adjacent semiconductor devices is connected to the external terminals 27 on the back surface 42 side via the terminals 40 of the printed circuit board 39. Alternatively, as shown in FIG. 16, one of the wirings 24 on the front surface 41 may be connected (the wiring 34 on the back surface 42 side may be connected). The number of semiconductor devices 51 arranged in parallel may be two or more.

本実施の形態によれば、この半導体装置５１も、プラグ１９が予設されたビア付き基板２０を別途形成し、これをチップ３と共に支持基盤２１上に貼り付けて疑似ウェーハ段階で形成するので、プラグを位置精度良く設けることができ、予設したプラグ１９に対し、チップ３の電極５から導出した配線２４を接続するだけで、簡単かつ確実に電極５をチップ３の裏面４２側へ導通させることができ、表面４１に外部端子２５を形成し、裏面４２側の外部端子２７は、裏面４２に露出したプラグ１９に再配置配線３４を接続し、この配線３４に対する接続孔を任意の位置に設けることにより、任意の位置にこの面の外部端子２７を形成することもできる。   According to the present embodiment, the semiconductor device 51 is also formed at the pseudo wafer stage by separately forming the via-attached substrate 20 in which the plug 19 is preliminarily attached and pasting it on the support base 21 together with the chip 3. The plug can be provided with high positional accuracy, and by simply connecting the wiring 24 led out from the electrode 5 of the chip 3 to the pre-installed plug 19, the electrode 5 is easily and reliably connected to the back surface 42 side of the chip 3. The external terminal 25 is formed on the front surface 41, and the external terminal 27 on the back surface 42 side connects the rearrangement wiring 34 to the plug 19 exposed on the back surface 42, and the connection hole for the wiring 34 is located at an arbitrary position. By providing in, the external terminal 27 of this surface can also be formed in arbitrary positions.

しかも、チップ３がその側面を樹脂で保護されているので、この樹脂部で切断して個片化できることにより、切断時にチップ３がダメージを受けることがなく、チップ化後のハンドリングが容易であり、このような構造の半導体装置５１を疑似ウェーハ２９上で一括して形成することにより、両面に外部端子を有する装置を低コストで形成できる。   In addition, since the side surface of the chip 3 is protected with resin, it can be cut into individual pieces by cutting with the resin portion, so that the chip 3 is not damaged at the time of cutting, and handling after chip formation is easy. By collectively forming the semiconductor device 51 having such a structure on the pseudo wafer 29, a device having external terminals on both sides can be formed at low cost.

そして、このチップ３を外部機器へ実装する際には、裏面４２の外部端子２７を介して接続してもよく、またこの外部端子２７の位置はプリント配線板等の外部端子の位置に合せて形成することもできるので、設計の自由度が大きく、このような半導体装置５１により積層構造のＭＣＭを構成することもできる。   When the chip 3 is mounted on an external device, the chip 3 may be connected via the external terminal 27 on the back surface 42, and the position of the external terminal 27 is matched with the position of the external terminal such as a printed wiring board. Since it can be formed, the degree of freedom in design is great, and such a semiconductor device 51 can also constitute an MCM having a stacked structure.

実施の形態３
図１７は本実施の形態の半導体装置５２Ａ、図１８は本実施の形態の半導体装置５２Ｂを示す。図示の如く、いずれも外部端子を裏面のみに設けたものであり、図１７に示す半導体装置５２Ａは、既述した実施の形態１において表面側の外部端子がないものであり、図１８に示す半導体装置５２Ｂは、同じく実施の形態２において表面側の外部端子がないものである。 Embodiment 3
FIG. 17 shows a semiconductor device 52A of the present embodiment, and FIG. 18 shows a semiconductor device 52B of the present embodiment. As shown in the figure, the external terminals are provided only on the back surface, and the semiconductor device 52A shown in FIG. 17 has no external terminals on the front surface side in the first embodiment described above, and is shown in FIG. Similarly, the semiconductor device 52B has no external terminal on the surface side in the second embodiment.

従って、実施の形態１及び２と同様の作製プロセスにおいて、一部のプロセスを省略して形成できる。即ち、図１７の半導体装置５２Ａは、実施の形態１において表面側の外部端子形成プロセスを省略したものであり、図１８の半導体装置５２Ｂは、実施の形態２において表面側の外部端子形成プロセスを省略したものであるため、いずれも構成及び作製プロセスの説明は省略する。   Therefore, part of the manufacturing process similar to that in Embodiments 1 and 2 can be omitted. That is, the semiconductor device 52A in FIG. 17 is obtained by omitting the surface side external terminal forming process in the first embodiment, and the semiconductor device 52B in FIG. Since they are omitted, description of the structure and the manufacturing process is omitted.

そしてこの場合も、良品チップ３のみを選択して再配置しているので、あたかも全てが良品チップからなる疑似ウェーハ２９に自社製、他社製の区別なく配置し、ウェーハレベルで一括処理が可能であり、低コストにて外部端子を形成できると共に、チップ３を疑似ウェーハから切り出す際に、絶縁物質からなるビア付き基板２０の位置で切断するので、チップ３にダメージ（亀裂、歪み等）を与えることなしで個片化でき、個片化後のハンドリングにおいてもチップが樹脂で保護され、ハンドリングが容易である。   In this case as well, only the non-defective chip 3 is selected and rearranged, so that it is possible to arrange the pseudo wafers 29 made of non-defective chips regardless of whether they are manufactured in-house or from other companies and perform batch processing at the wafer level. In addition, external terminals can be formed at low cost, and when the chip 3 is cut out from the pseudo wafer, the chip 3 is cut at the position of the substrate 20 with vias made of an insulating material, so that the chip 3 is damaged (cracked, distorted, etc.). The chip can be divided into pieces without any problem, and the chip is protected with resin even in the handling after the separation, and the handling is easy.

しかも、図１７の半導体装置５２Ａはチップ３の裏面全体が露出しているので、放熱性が良く、実装時に熱ストレスによるチップ３への影響を少なくすることができ、図１８の半導体装置５２Ｂは、裏面側の再配置配線３４が存在する位置で、実施の形態２と同様に図１８とは異なる位置に形成でき、設計の自由度が大きい利点を有しており、いずれも疑似ウェーハ２９上で一括して低コストにて作製することができる。   In addition, since the entire back surface of the chip 3 is exposed in the semiconductor device 52A in FIG. 17, the heat dissipation is good, and the influence of the thermal stress on the chip 3 during mounting can be reduced. The semiconductor device 52B in FIG. In the same manner as in the second embodiment, the rear-side rearrangement wiring 34 can be formed at a position different from that shown in FIG. 18 and has a great design freedom. Can be manufactured at a low cost.

図１９及び図２０に半導体装置５２Ａの実装例を示す。いずれも疑似ウェーハ上で一括して形成後に個片化してプリント基板に実装したものである。   19 and 20 show a mounting example of the semiconductor device 52A. All of them are formed on a pseudo wafer at once and then separated into individual pieces and mounted on a printed circuit board.

まず図１９の例のように、半導体装置５２Ａの外部端子２６をプリント基板３９の端子４０にはんだバンプ３３を介して接続し、フェイスアップにて実装することができる。   First, as in the example of FIG. 19, the external terminals 26 of the semiconductor device 52A can be connected to the terminals 40 of the printed circuit board 39 via the solder bumps 33, and can be mounted face up.

また、図２０のように、半導体装置５２Ａを並列に配し、隣接する半導体装置間の接続は、一方の外部端子２６同士をプリント基板３９の長尺の端子４０にはんだバンプ３３を介して接続し、フェイスアップにて実装できる。   Further, as shown in FIG. 20, the semiconductor devices 52A are arranged in parallel, and the connection between the adjacent semiconductor devices is performed by connecting one external terminal 26 to the long terminal 40 of the printed circuit board 39 via the solder bumps 33. However, it can be mounted face up.

図２１及び図２２に半導体装置５２Ｂの実装例を示す。いずれも疑似ウェーハ上で一括して形成後に個片化してプリント基板に実装した例である。   21 and 22 show a mounting example of the semiconductor device 52B. In either case, they are formed on a pseudo wafer in a lump and then separated into individual pieces and mounted on a printed circuit board.

まず図２１の例のように、半導体装置５２Ｂの外部端子２７をプリント基板３９の端子４０にはんだバンプ３３を介して接続し、フェイスアップにて実装することができる。   First, as in the example of FIG. 21, the external terminals 27 of the semiconductor device 52B can be connected to the terminals 40 of the printed circuit board 39 via the solder bumps 33, and can be mounted face up.

また、図２２の例のように、半導体装置５２Ｂ並列に配し、隣接する半導体装置間の接続は、一方の外部端子２７同士をプリント基板３９の長尺の端子４０にはんだバンプ３３を介して接続し、フェイスアップにて実装することができる。また、図示しないが隣接する半導体装置間の接続は、疑似ウェーハ上において表面４１側の再配置配線２４同士を予め接続しておいてもよく、裏面４２側の再配置配線３４同士を予め接続しておくこともでき、外部端子２７の設置位置はプリント基板３９の端子４０の位置にあわせて配置することもできる。また、２個以上の半導体装置５２Ｂを並列配置してもよい。   Further, as in the example of FIG. 22, the semiconductor devices 52B are arranged in parallel, and the connection between adjacent semiconductor devices is performed by connecting one external terminal 27 to the long terminal 40 of the printed circuit board 39 via the solder bumps 33. It can be connected and mounted face up. Although not shown, adjacent semiconductor devices may be connected in advance by connecting the rearrangement wirings 24 on the front surface 41 side on the pseudo wafer, or by connecting the rearrangement wirings 34 on the rear surface 42 side in advance. The installation position of the external terminal 27 can also be arranged according to the position of the terminal 40 of the printed circuit board 39. Two or more semiconductor devices 52B may be arranged in parallel.

本実施の形態によれば、半導体装置５２Ａ及び半導体装置５２Ｂも、プラグ１９が予設されたビア付き基板２０を別途形成し、これをチップ３と共に支持基板２１上に貼り付けて疑似ウェーハ段階で形成するので、プラグを位置精度良く設けることができ、予設したプラグ１９に対し、チップ３の電極５から導出した配線２４を接続するだけで、簡単かつ確実に電極５をチップ３の裏面４２側へ導通させることができる。   According to the present embodiment, the semiconductor device 52A and the semiconductor device 52B also separately form the via-attached substrate 20 in which the plug 19 is preliminarily formed, and paste it on the support substrate 21 together with the chip 3 at the pseudo wafer stage. Thus, the plug can be provided with high positional accuracy, and the electrode 5 can be easily and reliably connected to the back surface 42 of the chip 3 simply by connecting the wiring 24 led out from the electrode 5 of the chip 3 to the pre-installed plug 19. Can be conducted to the side.

そして、半導体装置５２Ａの場合は、裏面４２に露出したプラグ１９の露出部をこの面の外部端子２６とし、半導体装置５２Ｂの場合は、裏面４２に露出したプラグ１９に配線３４を接続し、この配線上に外部端子２７を形成することもでき、いずれも、チップ３がその側面を樹脂で保護されているので、この樹脂部で切断して個片化できることにより、切断時にチップ３がダメージを受けることがなく、チップ化後のハンドリングが容易であり、この構造を疑似ウェーハ２９上で一括して形成することにより、半導体装置を低コストにて形成することができる。   In the case of the semiconductor device 52A, the exposed portion of the plug 19 exposed on the back surface 42 is used as the external terminal 26 on this surface, and in the case of the semiconductor device 52B, the wiring 34 is connected to the plug 19 exposed on the back surface 42. External terminals 27 can also be formed on the wiring. In both cases, the chip 3 is protected on its side by a resin, so that the chip 3 can be cut into pieces by being cut at the resin portion, so that the chip 3 is damaged at the time of cutting. The semiconductor device can be formed at a low cost by forming the structure on the pseudo-wafer 29 all at once.

そして、このチップ３を外部機器等へ実装する際には、半導体装置５２Ａの場合は外部端子２６を介して接続でき、また、半導体装置５２Ｂの場合は、外部端子２７を介して接続してもよく、プリント配線板等の端子の位置に合せて外部端子２７を形成できるので設計の自由度が大きい。   When the chip 3 is mounted on an external device or the like, the semiconductor device 52A can be connected via the external terminal 26, and the semiconductor device 52B can be connected via the external terminal 27. Since the external terminals 27 can be formed in accordance with the positions of terminals such as a printed wiring board, the degree of freedom in design is great.

以下、上記した各実施の形態の変形例を示すが、基本構造及び基本的な作製プロセスは対応する実施の形態の場合と同じであるので、プロセスの詳細は省略して説明する。   Hereinafter, modifications of each embodiment described above will be described. However, the basic structure and the basic manufacturing process are the same as those in the corresponding embodiment, and thus the details of the process will be omitted.

図２３は、実施の形態１の変形例を示し、図２３（ａ）は図７（ｎ）に対応する図である。図示の如く、ビア付き基板２０Ａに予設されたプラグ１９が実施の形態１に比べて長く、チップ３の厚みよりも裏面側に突出しており、従って、ビア付き基板２０Ａ自体も実施の形態１よりも厚い。   FIG. 23 shows a modification of the first embodiment, and FIG. 23 (a) corresponds to FIG. 7 (n). As shown in the figure, the plug 19 preliminarily provided on the via-attached substrate 20A is longer than that in the first embodiment and protrudes to the back side rather than the thickness of the chip 3. Therefore, the via-equipped substrate 20A itself is also in the first embodiment. Thicker than.

このビア付き基板２０Ａも実施の形態１の場合と同様に、図２に示したプロセスを経て別途形成し、図４〜図６と同様のプロセスを経て図２３の形状に作製する。   Similarly to the case of the first embodiment, the via-attached substrate 20A is separately formed through the process shown in FIG. 2, and is formed into the shape of FIG. 23 through the same process as in FIGS.

次に、裏面を研削して図２３（ｂ）に示すようにプラグ１９を露出させ、この露出部がこの面の外部端子２６となる。これにより、プラグ１９が長いため、チップ３の裏面４２側が樹脂４によって被覆された状態に形成され、しかる後、切断線４５の位置で切断して個片化することにより、図２３（ｃ）に示す半導体装置５０Ａを形成することができる。   Next, the back surface is ground to expose the plug 19 as shown in FIG. 23B, and this exposed portion becomes the external terminal 26 on this surface. Thereby, since the plug 19 is long, the back surface 42 side of the chip 3 is formed to be covered with the resin 4, and then cut at the position of the cutting line 45 to be separated into individual pieces, so that FIG. The semiconductor device 50A shown in FIG.

個片化後は、実施の形態１と同様にしてプリント基板等に実装することができる（図９〜図１１参照。）これにより、チップ３の側面及び裏面が樹脂４によって被覆されるため、チップ３を衝撃等から保護しハンドリングが更に容易になる。   After singulation, it can be mounted on a printed circuit board or the like in the same manner as in the first embodiment (see FIGS. 9 to 11). As a result, the side surface and the back surface of the chip 3 are covered with the resin 4, The chip 3 is protected from impact and the handling becomes easier.

図２４は、実施の形態２の変形例を示し、図２４（ａ）は図１３（ａ）に対応する図である。図示の如く、裏面４２に設けた層間膜３１がチップ３の裏面領域において、チップ３の中央部に露出部４４が形成されるように欠除されている。この露出部４４は層間膜３１の成膜時に形成できる。   FIG. 24 shows a modification of the second embodiment, and FIG. 24 (a) corresponds to FIG. 13 (a). As shown in the figure, the interlayer film 31 provided on the back surface 42 is omitted so that an exposed portion 44 is formed at the center of the chip 3 in the back surface region of the chip 3. The exposed portion 44 can be formed when the interlayer film 31 is formed.

以後は、実施の形態２におけるプロセス（図１３（ｂ）〜図１３（ｃ））と同様に、図２４（ｂ）〜図２４（ｃ）のプロセスを行い、切断線４５の位置で切断して個片化することにより、図２４（ｄ）に示す半導体装置５１Ａを形成できる。   Thereafter, similarly to the process in the second embodiment (FIGS. 13B to 13C), the processes in FIGS. 24B to 24C are performed to cut at the position of the cutting line 45. Thus, the semiconductor device 51A shown in FIG. 24D can be formed.

個片化後は、実施の形態２と同様にプリント基板等に実装することができる（図１４〜図１６参照）。これにより、チップ３の裏面が露出しているため放熱性が良く、実装時の熱ストレスによるチップ３への影響を緩和することができる。   After separation, it can be mounted on a printed circuit board or the like as in Embodiment 2 (see FIGS. 14 to 16). Thereby, since the back surface of the chip 3 is exposed, heat dissipation is good, and the influence on the chip 3 due to thermal stress during mounting can be reduced.

図２５は、実施の形態１〜３に共通の変形例を示し、図２に対応する図である。即ち、既述した如く、図２においてはビア付き基板２０の作製を、成形型５５を用いた液状材料の射出成形及びスキージによる銀ペースト１８の充填によりプラグ１９を形成したが、この例は、フォトリソグラフィ技術によるビア付き基板２０の形成とめっきによりプラグ１９を形成するものであり、ビア付き基板２０はこの方法で形成することもできる。   FIG. 25 shows a modification common to the first to third embodiments, and corresponds to FIG. That is, as described above, in FIG. 2, the plug 20 is formed by manufacturing the substrate 20 with vias by injection molding of a liquid material using the molding die 55 and filling the silver paste 18 with a squeegee. The plug 19 is formed by forming and plating the substrate 20 with vias by photolithography and plating, and the substrate 20 with vias can also be formed by this method.

即ち、まず図２５（ａ）に示すように、例えば石英等を用いた基板１７上に紫外線照射により粘着力が低下する粘着シートを固定材２２として貼り付け、この上に感光性の絶縁物質層２０Ａを貼り付ける。   That is, first, as shown in FIG. 25A, an adhesive sheet whose adhesive strength is reduced by ultraviolet irradiation is attached as a fixing material 22 on a substrate 17 using, for example, quartz or the like, and a photosensitive insulating material layer is formed thereon. Paste 20A.

次に図２５（ｂ）に示すように、フォトリソグラフィ技術を用いて絶縁物質層２０Ａにチップ配置のための欠除部２３と、プラグを形成するためのビアホール３８を形成する。これらの欠除部２３及びビアホール３８は、図３に示した平面図と同様に形成する。   Next, as shown in FIG. 25B, a notch 23 for chip placement and a via hole 38 for forming a plug are formed in the insulating material layer 20A by using a photolithography technique. These notched portions 23 and via holes 38 are formed in the same manner as in the plan view shown in FIG.

次に図２５（ｃ）に示すように、ビアホール３８に対応する部分が開口されたマスク４６を掛け、金属めっきのためのシードメタルとして、Ｔａ等を用いてスパッタ膜をビアホール３８の内壁面に形成した後に、図２５（ｄ）に示すように、ビアホール３８に銅めっき等を埋め込む。   Next, as shown in FIG. 25 (c), a mask 46 having an opening corresponding to the via hole 38 is put on, and Ta or the like is used as a seed metal for metal plating to deposit a sputtered film on the inner wall surface of the via hole 38. After the formation, copper plating or the like is embedded in the via hole 38 as shown in FIG.

次に図２５（ｅ）に示すように、基板１７の裏面側から紫外線Ｌを照射して固定材２２の粘着力を弱め、絶縁物質層２２を剥離することにより、図３と同様に、欠除部２３及びプラグ１９が所定位置に配されたビア付き基板２０を作製することができる。以後はこれを用いて実施の形態１同様のプロセスに適用することができる。   Next, as shown in FIG. 25 (e), the ultraviolet light L is irradiated from the back side of the substrate 17 to weaken the adhesive strength of the fixing material 22, and the insulating material layer 22 is peeled off. The via-attached substrate 20 in which the removal portion 23 and the plug 19 are arranged at predetermined positions can be manufactured. Thereafter, it can be applied to the same process as in the first embodiment using this.

図２６は、実施の形態１〜３に共通の変形例を示し、図２６（ａ）は図２（ｂ）に対応する図である。実施の形態１においては、別途作製したビア付き基板２０を図４に示すように、固定材を貼り付けた別の基板２１上に移し替えてその後のプロセスに移行したが、この例は最初の支持基板１７上で全てのプロセスを実施するものである。   FIG. 26 shows a modification common to the first to third embodiments, and FIG. 26 (a) corresponds to FIG. 2 (b). In the first embodiment, as shown in FIG. 4, the substrate 20 with vias separately manufactured is transferred onto another substrate 21 to which a fixing material is attached, and the subsequent process is performed. All processes are performed on the support substrate 17.

即ち、図２６（ａ）は図２（ｂ）と同様に、液状の絶縁物質層２０を射出成形後に成形型を除去し、絶縁物質層２０が固化して欠除部２３が形成された状態である。   That is, FIG. 26A shows a state in which, as in FIG. 2B, the molding die is removed after the liquid insulating material layer 20 is injection-molded, and the insulating material layer 20 is solidified to form the notch 23. It is.

次に図２６（ｂ）に示すように、チップ間領域２０ａにビアホール３８を形成後、欠除部２３にチップ３を貼り付ける。ビアホール３８は実施の形態１と同様に押し型又はレーザ加工等で形成することができ、支持基板１７上には固定材２２が設けてあるので貼り付けることができる。また、欠除部２３はチップ３の寸法よりも大きいので、チップ３の周囲にはすき間２３ａが形成される。   Next, as shown in FIG. 26B, after the via hole 38 is formed in the inter-chip region 20a, the chip 3 is attached to the notch 23. The via hole 38 can be formed by a pressing die or laser processing as in the first embodiment, and can be attached because the fixing material 22 is provided on the support substrate 17. Further, since the notch 23 is larger than the size of the chip 3, a gap 23 a is formed around the chip 3.

次に図２６（ｃ）に示すように、ビアホール３８に導電材を埋め込みプラグ１９を形成する。この導電材の埋め込みは、図２と同様に銀ペーストをスキージ印刷によって行ってもよく、図２５と同様に銅めっきによって埋め込んでもよい。   Next, as shown in FIG. 26C, a conductive material is embedded in the via hole 38 to form a plug 19. The conductive material may be embedded by squeegee printing using a silver paste as in FIG. 2 or by copper plating as in FIG.

次に図２６（ｄ）に示すように、チップ３及びビア付き基板２０上の全面に、樹脂４をスピンコート法又は印刷法により均一に塗布する。これにより実施の形態１と同様（図４（ｄ）参照）に、チップ３及びビア付き基板２０が樹脂４からなる疑似ウェーハ２９上にて一体化された状態を形成できる。   Next, as shown in FIG. 26D, the resin 4 is uniformly applied to the entire surface of the chip 3 and the substrate 20 with vias by a spin coating method or a printing method. As a result, as in the first embodiment (see FIG. 4D), it is possible to form a state in which the chip 3 and the substrate 20 with vias are integrated on the pseudo wafer 29 made of the resin 4.

次に図２６（ｄ）に示すように、支持基板１７の裏面側から紫外線Ｌを照射して固定材２２の粘着力を弱め、疑似ウェーハ２９を支持基板１７から剥離する。これにより、製造工程を大幅に簡素化することができる。   Next, as shown in FIG. 26 (d), ultraviolet light L is irradiated from the back side of the support substrate 17 to weaken the adhesive force of the fixing material 22, and the pseudo wafer 29 is peeled off from the support substrate 17. Thereby, a manufacturing process can be simplified greatly.

即ち、この状態は実施の形態１における図４（ｅ）とは、支持基板が異なるのみで同じ状態であるので、以後は実施の形態１における図５以降のプロセスを実施すればよい。従って、これまでのプロセスが共通な実施の形態２及び実施の形態３にも適用することができる。   That is, this state is the same as that of FIG. 4E in the first embodiment except that the supporting substrate is different, and hence the processes in FIG. 5 and subsequent steps in the first embodiment may be performed. Therefore, the present invention can be applied to the second and third embodiments that share the same processes.

図２７及び図２８は、請求項２７及び請求項２９〜３３、請求項３５〜３８の実施の形態に係るものであり、実施の形態１〜３に共通の変形例であるが、上記した各例がプラグ１９を予設したビア付き基板２０を用いるのとは異なり、この例の特徴は、第１の導電材として入れ子４７をチップ３と同時に埋設し、予設するものである。   FIGS. 27 and 28 relate to the embodiments of claims 27, 29 to 33, and 35 to 38, and are modifications common to the first to third embodiments. Unlike the example in which the substrate 20 with vias in which the plug 19 is preliminarily used, the feature of this example is that the nest 47 is embedded as the first conductive material at the same time as the chip 3 and is preliminarily provided.

即ち、まず図２７（ａ）は、表面に固定材２２を設けた支持基板２１の上に、チップ３を所定位置で貼り付ける。   That is, first, in FIG. 27A, the chip 3 is stuck at a predetermined position on the support substrate 21 provided with the fixing material 22 on the surface.

次に図２７（ｂ）に示すように、チップ間領域となる場所に導電性の入れ子４７を貼り付ける。この入れ子４７は２個の突起部４７ａが連結部４７ｂにて連結されている。そして各突起部４７ａはチップ３の電極５に対応する位置で、チップ３の周辺に配置する。   Next, as shown in FIG. 27 (b), a conductive insert 47 is pasted in a place to be an inter-chip region. The nest 47 has two projecting portions 47a connected by a connecting portion 47b. Each protrusion 47 a is arranged around the chip 3 at a position corresponding to the electrode 5 of the chip 3.

次に図２７（ｃ）に示すように、チップ３及び各入れ子４７上の全面を樹脂４で被覆する。この樹脂４は後に疑似ウェーハとなるものであり、上記した樹脂４と同じ材料を用い、スピンコート法又は印刷法により均一に塗布する。これにより、チップ３及び入れ子４７が樹脂で一体化された疑似ウェーハ２９が形成される。   Next, as shown in FIG. 27C, the entire surface of the chip 3 and each insert 47 is covered with the resin 4. This resin 4 will become a pseudo wafer later, and is applied uniformly by spin coating or printing using the same material as the resin 4 described above. Thereby, the pseudo wafer 29 in which the chip 3 and the insert 47 are integrated with the resin is formed.

次に図２７（ｄ）に示すように、支持基板２１の裏面から紫外線Ｌを照射して固定材２２の粘着力を弱め、疑似ウェーハ２９を支持基板２１から剥離する。   Next, as shown in FIG. 27 (d), ultraviolet rays L are irradiated from the back surface of the support substrate 21 to weaken the adhesive force of the fixing material 22, and the pseudo wafer 29 is peeled from the support substrate 21.

次に図２８（ｅ）に示すように、疑似ウェーハ２９をひっくり返すことにより、実施の形態１における図５（ｆ）に対応する状態になるが、この例ではチップ３の側面が樹脂４からなる単一部材によって覆われ、基板内にはチップ３との界面のみが存在する強度の高いビア付き基板２０Ｂを形成できる。   Next, as shown in FIG. 28E, by turning the pseudo wafer 29 upside down, the state corresponding to FIG. 5F in the first embodiment is obtained. In this example, the side surface of the chip 3 is made of the resin 4. A high-strength via substrate 20B that is covered with a single member and has only an interface with the chip 3 in the substrate can be formed.

以後は、実施の形態１における図５（ｇ）〜図７（ｎ）と同様のプロセスを経ることにより、図２８（ｆ）（図７（ｏ）に対応する）の状態が形成され、切断線４５の位置で切断して個片化することにより、図２８（ｇ）に示すように、裏面４２側に入れ子４７の露出部がこの面の外部端子２６として形成された半導体装置５３を形成することができる。なお、この例は実施の形態２及び実施の形態３にも適用できる。   Thereafter, the process shown in FIG. 28F (corresponding to FIG. 7O) is formed by performing the same processes as in FIGS. By cutting and cutting into pieces at the position of the line 45, as shown in FIG. 28G, a semiconductor device 53 is formed in which the exposed portion of the insert 47 is formed as the external terminal 26 on this surface on the back surface 42 side. can do. This example can also be applied to the second and third embodiments.

図２９は、この例における図２８（ｆ）の平面図を示し、入れ子４７との関係を明示するために配線２４を実線で示した。   FIG. 29 is a plan view of FIG. 28 (f) in this example, and the wiring 24 is shown by a solid line in order to clearly show the relationship with the nesting 47.

上記したようにこの半導体装置５３は、既述した各例がプラグを予設したビア付き基板２０を用いるのとは異なり、チップ３の配置と同時にプラグとして入れ子４７を配設してプラグを予設することと、チップ３及び入れ子４７を保護物質材料である樹脂４によって一体化させていることが異なっている。またこの場合、樹脂４を塗布する際に、配置した入れ子４７が若干移動して位置が変化することも考えられるが、設計の許容誤差の範囲内に配置することができる。また入れ子４７の突起部４７ａを連続部４７ｂで連結していることと、入れ子４７の形状が梯形であることは、変位を制御するためのものである。   As described above, the semiconductor device 53 is different from the above-described example in which the via-attached substrate 20 in which the plug is preliminarily used is used. The difference is that the chip 3 and the insert 47 are integrated with the resin 4 which is a protective material. Further, in this case, when the resin 4 is applied, it is conceivable that the arranged nest 47 is slightly moved and the position is changed. However, the resin 4 can be arranged within a design tolerance. Further, the fact that the protrusion 47a of the insert 47 is connected by the continuous portion 47b and the shape of the insert 47 is a trapezoid is for controlling the displacement.

図３０〜図３２は、請求項２８及び請求項３４に係るものであり、実施の形態１〜３に共通の変形例である。この例の特徴は、ビア付き基板が保護物質材料としての熱可塑性の材料からなり、チップの厚みより厚いビア付き基板を加熱圧着して、チップ３がビア付き基板に一体化され、このビア付き基板が保護物質層を兼ねていることである。   30 to 32 relate to claims 28 and 34, and are modifications common to the first to third embodiments. The feature of this example is that the substrate with vias is made of a thermoplastic material as a protective material, the substrate with vias thicker than the thickness of the chip is thermocompression bonded, and the chip 3 is integrated with the substrate with vias. The substrate also serves as a protective material layer.

即ち、まず図３０（ａ）は実施の形態１における図４（ａ）に対応する図であり、図３０（ａ）〜図３０（ｃ）のプロセスは図４（ａ）〜図４（ｃ）と同様に行われ、プラグを予設したビア付き基板２０Ｃを別途作製して用いる。   That is, FIG. 30 (a) is a diagram corresponding to FIG. 4 (a) in the first embodiment, and the processes of FIGS. 30 (a) to 30 (c) are illustrated in FIGS. 4 (a) to 4 (c). The substrate 20C with vias in which the plug is preliminarily prepared is separately prepared and used.

しかし、図３０（ｃ）に示すように、本例のビア付き基板２０Ｃは、熱可塑性の樹脂を材料とし、チップ３の設置領域となる欠除部２３の大きさが、既述した実施の形態１の場合よりも小さいため、チップ３との間隔が小さく、しかもビア付き基板２０Ｃの厚さがチップ３の厚さよりも厚く形成されている。   However, as shown in FIG. 30C, the substrate with via 20C of this example is made of a thermoplastic resin, and the size of the notch 23 serving as the chip 3 installation region is the same as that of the implementation described above. Since the distance is smaller than that in the first mode, the distance from the chip 3 is small, and the thickness of the via-attached substrate 20C is larger than the thickness of the chip 3.

次に図３１（ｄ）に示すように、加熱圧着プレス４８で加圧することにより、ビア付き基板２０Ｃが軟性となって流動するため、チップ３との間のすき間２３ａが埋めつくされると共に、チップ３がビア付き基板２０Ｃに圧着されて一体化され、双方の厚みも均一となる。この場合、プラグとなる材料としては銀ペースト１８等を用い、加圧により厚みが減少する量を考慮して、銀ペースト１８の充填量は、ビア付き基板２０Ｃの厚みよりも少な目にしておくのが良い。   Next, as shown in FIG. 31 (d), by pressurizing with a thermocompression press 48, the via-attached substrate 20C flows softly, so that the gap 23a between the chip 3 and the chip 3 is buried, The chip 3 is pressure-bonded and integrated with the via-attached substrate 20 </ b> C, and both thicknesses are uniform. In this case, silver paste 18 or the like is used as a material for the plug, and the amount of filling of the silver paste 18 is set to be smaller than the thickness of the substrate with via 20C in consideration of the amount of thickness reduction due to pressurization. Is good.

次に、図３１（ｅ）に示すように、支持基板２１側と同じ固定材２２を設けた支持体１７をチップ３の裏面側に貼り付け、チップ３及びビア付き基板２０Ｃを仮固定する。これにより支持体１７が疑似ウェーハと同様に機能する。   Next, as shown in FIG. 31 (e), the support 17 provided with the same fixing material 22 as that of the support substrate 21 is attached to the back side of the chip 3, and the chip 3 and the substrate with via 20C are temporarily fixed. Thereby, the support body 17 functions similarly to a pseudo wafer.

次に図３１（ｆ）に示すように、支持基板２１の裏面に紫外線Ｌを照射して固定材２２の粘着力を弱め、チップ３及びビア付き基板２０Ｃを支持体１７に固定状態で剥離する。   Next, as shown in FIG. 31 (f), the back surface of the support substrate 21 is irradiated with ultraviolet rays L to weaken the adhesive force of the fixing material 22, and the chip 3 and the substrate 20 </ b> C with vias are peeled off in a fixed state. .

図３２（ｇ）は、剥離後の支持体１７をひっくり返した状態の図であり、あたかも疑似ウェーハのように支持体１７に支持された状態でこれ以降のプロセスを実施できる。   FIG. 32 (g) is a diagram of the state where the support 17 after peeling is turned over, and the subsequent processes can be carried out in a state where the support 17 is supported by the support 17 like a pseudo wafer.

図３２（ｈ）は、実施の形態１と同様のプロセス（図５（ｇ）〜図７（ｎ））を経て、表面４１側の配線２４を形成し、この一部分を開口して表面４１の外部端子２５を形成した状態である。   In FIG. 32 (h), the wiring 24 on the surface 41 side is formed through the same process (FIG. 5 (g) to FIG. 7 (n)) as in the first embodiment. The external terminal 25 is formed.

次に図３２（ｉ）に示すように、支持体１７の裏面に紫外線Ｌを照射して固定材２２の粘着力を弱め、支持体１７から上部を剥離する。しかる後、切断線４５の位置で切断して個片化することにより、図３２（ｊ）の半導体装置５４Ａを形成できる。   Next, as shown in FIG. 32 (i), the back surface of the support 17 is irradiated with ultraviolet light L to weaken the adhesive force of the fixing material 22, and the upper part is peeled off from the support 17. Thereafter, the semiconductor device 54A shown in FIG. 32 (j) can be formed by cutting at the position of the cutting line 45 into pieces.

この構造により、チップ部品３の側面を覆う保護物質層が単一材料からなるビア付き基板２０Ｃのみであるため、この物質層間にはチップ３との界面のみが存在することになり、しかも加熱圧着されているため接着性が良く、界面での剥離を抑制することができる。なお、この例は実施の形態２及び実施の形態３にも適用できる。   With this structure, since the protective substance layer covering the side surface of the chip component 3 is only the substrate with via 20C made of a single material, only the interface with the chip 3 exists between the substance layers, and thermocompression bonding is performed. Therefore, the adhesiveness is good, and peeling at the interface can be suppressed. This example can also be applied to the second and third embodiments.

図３３〜図３５は、さらに請求項２８及び請求項３４の実施の形態に係るものであり、実施の形態１〜３に共通の変形例である。この例は、上記した変形例（図３０）と同様にビア付き基板が保護物質層を兼ねており、熱可塑性の材料を用いて上記変形例よりもビア付き基板の厚みを厚くすることにより、支持体なしでビア付き基板が疑似ウェーハ的に機能する。   FIGS. 33 to 35 further relate to the embodiments of claims 28 and 34, and are modifications common to the first to third embodiments. In this example, the via-attached substrate also serves as a protective substance layer as in the above-described modification (FIG. 30), and by using a thermoplastic material, the via-attached substrate is made thicker than the above-described modification, A substrate with vias functions like a pseudo wafer without a support.

まず、図３３（ａ）〜（ｂ）は、上記した変形例における図３０と同様であるが、図３３（ｃ）において、別途作製したビア付き基板２０Ｄが図３０の場合に比べて更に厚く形成され、ビアホール３８内には銀ペースト１８がほぼチップ３の厚さ相当に充填されている。   First, FIGS. 33A to 33B are the same as FIG. 30 in the above-described modified example. However, in FIG. 33C, a via-made substrate 20D separately manufactured is thicker than the case of FIG. The via hole 38 is filled with a silver paste 18 approximately equivalent to the thickness of the chip 3.

次に図３４（ｄ）に示すように、加熱圧着プレス４８で加圧することにより、ビア付き基板２０Ｄが流動化し、チップ３とのすき間２３ａを埋めつくすと共に、ビアホール３８の空域部も埋め、チップ３の裏面も一定の厚みで覆い、チップ３が側面及び裏面を保護物質層を兼ねた単一材料によって一体化され、ビア付き基板２０Ｄが疑似ウェーハとして機能する。   Next, as shown in FIG. 34 (d), the substrate 20D with vias is fluidized by pressurizing with a thermocompression press 48, filling the gap 23a with the chip 3 and also filling the air space portion of the via hole 38. The back surface of 3 is also covered with a constant thickness, the chip 3 is integrated with a single material that also serves as a protective substance layer on the side surface and the back surface, and the substrate with via 20D functions as a pseudo wafer.

次に図３４（ｅ）に示すように、加熱圧着プレス４８を除去した後は、ビア付き基板２０Ｄからなる疑似ウェーハ２９Ｂ内にチップ３が埋設された状態となる。   Next, as shown in FIG. 34 (e), after the thermocompression press 48 is removed, the chip 3 is embedded in the pseudo wafer 29B formed of the via-attached substrate 20D.

次に図３４（ｆ）に示すように、支持基板２１の裏面に紫外線Ｌを照射して固定材２２の粘着力を弱め、疑似ウェーハ２９Ｂを剥離する。   Next, as shown in FIG. 34 (f), the back surface of the support substrate 21 is irradiated with ultraviolet rays L to weaken the adhesive force of the fixing material 22, and the pseudo wafer 29B is peeled off.

図３５（ｇ）は、剥離後の疑似ウェーハ２９Ｂをひっくり返した状態の図であり、これ以降は実施の形態１における図５以降のプロセスを経て、図３５（ｈ）に示すように、チップ３の裏面側全体を研削してプラグ１９を露出させ、切断線４５の位置で切断して個片化することにより、図３５（ｉ）に示す半導体装置を形成することができる。   FIG. 35 (g) is a diagram showing a state in which the pseudo wafer 29B after peeling is turned over, and thereafter, after the process of FIG. 5 and subsequent steps in the first embodiment, as shown in FIG. 35 (h). 3 is ground to expose the plug 19 and cut at the position of the cutting line 45 to obtain individual pieces, whereby the semiconductor device shown in FIG. 35I can be formed.

この構造により、チップ３の側面を覆う保護物質層が単一材料からなるビア付き基板２０Ｄのみであるため、この物質層間にはチップ３との界面のみが存在し、しかも加熱圧着されているため接着力が良く、上記と同様に界面剥離を抑制することができる。なお、この例は実施の形態２及び実施の形態３にも適用できる。   With this structure, since the protective substance layer covering the side surface of the chip 3 is only the substrate with via 20D made of a single material, only the interface with the chip 3 exists between the substance layers, and is thermocompression bonded. Adhesive strength is good, and interface peeling can be suppressed as described above. This example can also be applied to the second and third embodiments.

上記した各実施の形態等は、本発明の技術的思想に基づいて種々に変形が可能である。   Each of the above-described embodiments and the like can be variously modified based on the technical idea of the present invention.

例えば、予設するプラグ１９の形状や形成方法は、実施の形態に限らず、別の適宜な方法であってもよく、使用材料も銅や銀ペースト以外を用いてもよい。   For example, the shape and the forming method of the pre-installed plug 19 are not limited to the embodiment, and may be another appropriate method, and the material used may be other than copper or silver paste.

また、再配置配線の形成方法も、電気めっきに限らず、物理蒸着、又はスクリーン印刷により形成してもよい。また、積層構造の外部端子間の接続やプリント基板等への実装時の外部端子の接続は、はんだバンプに限らずＡＣＦ（異方性導電フィルム）を用いてもよい。   The method for forming the rearrangement wiring is not limited to electroplating, and may be formed by physical vapor deposition or screen printing. The connection between the external terminals of the laminated structure and the connection of the external terminals when mounted on a printed circuit board or the like are not limited to solder bumps, and ACF (anisotropic conductive film) may be used.

また、チップ３の外部端子をチップの表面及び裏面のうち少なくとも裏面に形成することは、半導体チップ以外の例えば発光ダイオード又はフォトダイオード等のチップ部品にも適用できる。   In addition, forming the external terminals of the chip 3 on at least the back surface of the front surface and the back surface of the chip can also be applied to chip components such as light emitting diodes or photodiodes other than the semiconductor chip.

本発明の実施の形態１による半導体装置を示す概略断面図である。It is a schematic sectional drawing which shows the semiconductor device by Embodiment 1 of this invention. 同、ビア付き基板作製プロセスを示す概略断面図である。It is a schematic sectional drawing which shows the board | substrate preparation process with a via | veer in the same. 同、ビア付き基板の一部分を示す概略平面図である。It is a schematic plan view which shows a part of board | substrate with a via in the same. 同、半導体装置の作製プロセスを示す概略断面図である。It is a schematic sectional drawing which shows the manufacturing process of a semiconductor device equally. 同、半導体装置の作製プロセスを示す概略断面図である。It is a schematic sectional drawing which shows the manufacturing process of a semiconductor device equally. 同、半導体装置の作製プロセスを示す概略断面図である。It is a schematic sectional drawing which shows the manufacturing process of a semiconductor device equally. 同、半導体装置の作製プロセスを示す概略断面図である。It is a schematic sectional drawing which shows the manufacturing process of a semiconductor device equally. 同、半導体装置の作製プロセスにおける一部分を示す概略平面図である。FIG. 6 is a schematic plan view showing a part in the manufacturing process of the semiconductor device. 同、半導体装置の実装例を示す概略断面図である。It is a schematic sectional drawing which shows the mounting example of a semiconductor device equally. 同、半導体装置の実装例を示す概略断面図である。It is a schematic sectional drawing which shows the mounting example of a semiconductor device equally. 同、半導体装置の実装例を示す概略断面図である。It is a schematic sectional drawing which shows the mounting example of a semiconductor device equally. 同、実施の形態２による半導体装置を示す概略断面図である。FIG. 6 is a schematic cross-sectional view showing the semiconductor device according to the second embodiment. 同、半導体装置の作製プロセスを示す概略断面図である。It is a schematic sectional drawing which shows the manufacturing process of a semiconductor device equally. 同、半導体装置の実装例を示す概略断面図である。It is a schematic sectional drawing which shows the mounting example of a semiconductor device equally. 同、半導体装置の実装例を示す概略断面図である。It is a schematic sectional drawing which shows the mounting example of a semiconductor device equally. 同、半導体装置の実装例を示す概略断面図である。It is a schematic sectional drawing which shows the mounting example of a semiconductor device equally. 同、実施の形態３による一方の半導体装置を示す概略断面図である。FIG. 5 is a schematic cross-sectional view showing one semiconductor device according to the third embodiment. 同、実施の形態による他方の半導体装置を示す概略断面図である。It is a schematic sectional drawing which shows the other semiconductor device by embodiment similarly. 同、実施の形態による一方の半導体装置の実装例を示す概略断面図である。It is a schematic sectional drawing which shows the example of mounting of one semiconductor device by embodiment similarly. 同、半導体装置の実装例を示す概略断面図である。It is a schematic sectional drawing which shows the mounting example of a semiconductor device equally. 同、実施の形態による他方の半導体装置の実装例を示す概略断面図である。It is a schematic sectional drawing which shows the example of mounting of the other semiconductor device by embodiment similarly. 同、半導体装置の実装例を示す概略断面図である。It is a schematic sectional drawing which shows the mounting example of a semiconductor device equally. 同、実施の形態１による半導体装置の変形例の作製プロセスを示す概略断面図である。FIG. 6 is a schematic cross-sectional view showing a manufacturing process of a variation of the semiconductor device according to the first embodiment. 同、実施の形態２による半導体装置の変形例の作製プロセスを示す概略断面図である。FIG. 10 is a schematic cross-sectional view showing a manufacturing process of a modification of the semiconductor device according to the second embodiment. 同、ビア付き基板の変形例の作製プロセスを示す概略断面図である。It is a schematic sectional drawing which shows the preparation process of the modification of a board | substrate with a via same as the above. 同、実施の形態１の構造で示した変形例の作製プロセスの概略断面図である。FIG. 6 is a schematic cross-sectional view of a manufacturing process of a modification example shown in the structure of the first embodiment. 同、実施の形態１の構造で示した他の変形例の作製プロセスの概略断面図である。FIG. 10 is a schematic cross-sectional view of a manufacturing process of another modification example shown in the structure of the first embodiment. 同、変形例の作製プロセスの概略断面図である。It is a schematic sectional drawing of the manufacturing process of a modification similarly. 同、変形例の作製プロセスにおける一部分を示す概略平面図である。It is a schematic plan view which shows a part in the manufacturing process of a modification. 同、実施の形態１の構造で示した他の変形例の作製プロセスの概略断面図である。FIG. 10 is a schematic cross-sectional view of a manufacturing process of another modification example shown in the structure of the first embodiment. 同、変形例の作製プロセスを示す概略断面図である。It is a schematic sectional drawing which shows the manufacturing process of a modification similarly. 同、変形例の作製プロセスを示す概略断面図である。It is a schematic sectional drawing which shows the manufacturing process of a modification similarly. 同、実施の形態１の構造で示した他の変形例の作製プロセスの概略断面図である。FIG. 10 is a schematic cross-sectional view of a manufacturing process of another modification example shown in the structure of the first embodiment. 同、変形例の作製プロセスを示す概略断面図である。It is a schematic sectional drawing which shows the manufacturing process of a modification similarly. 同、変形例の作製プロセスを示す概略断面図である。It is a schematic sectional drawing which shows the manufacturing process of a modification similarly. 従来例による半導体装置の作製プロセスを示す概略断面図である。It is a schematic sectional drawing which shows the manufacturing process of the semiconductor device by a prior art example. 同、半導体装置の作製プロセスを示す概略断面図である。It is a schematic sectional drawing which shows the manufacturing process of a semiconductor device equally. 同、半導体装置の作製プロセスを示す概略断面図である。It is a schematic sectional drawing which shows the manufacturing process of a semiconductor device equally. 同、半導体装置の実装例を示す概略断面図である。It is a schematic sectional drawing which shows the mounting example of a semiconductor device equally. 同、半導体装置の実装例を示す概略断面図である。It is a schematic sectional drawing which shows the mounting example of a semiconductor device equally.

符号の説明Explanation of symbols

３…半導体チップ、４…樹脂、５…電極、１６、３２…接続孔、
９、１３、３１…層間膜、１０…スパッタ膜、１１、１１Ａ…レジスト膜、
２４、３４…配線、１２Ａ…めっき膜、２５、２６、２７、４０…外部端子、
１７…支持体、１８…銀ペースト、１９…プラグ、１９ａ…露出部、
２０、２０Ａ、２０Ｂ、２０Ｃ、２０Ｄ…ビア付き基板、２０ａ…チップ間領域、
２１…支持基板、２２…固定材、２３…欠除部、２３ａ…すき間、
２９、２９Ｂ…疑似ウェーハ、３０、４３…保護膜、３３…はんだバンプ、
３５、４６…マスク、３６…開口部、３７…露光光、３８…ビアホール、
３９…プリント基板、４１…表面、４２…裏面、４５…切断線、４７…入れ子、
４７ａ…突起部、４７ｂ…連結部、４８…加熱圧着プレス、
５０、５０Ａ、５１、５１Ａ、５２Ａ、５２Ｂ、５３、５４Ａ、５４Ｂ…半導体装置、
５５…成形型、５５ａ…空洞部、５６…スキージ、Ｌ…紫外線 3 ... Semiconductor chip, 4 ... Resin, 5 ... Electrode, 16, 32 ... Connection hole,
9, 13, 31 ... interlayer film, 10 ... sputtered film, 11, 11A ... resist film,
24, 34 ... wiring, 12A ... plating film, 25, 26, 27, 40 ... external terminals,
17 ... Support, 18 ... Silver paste, 19 ... Plug, 19a ... Exposed part,
20, 20A, 20B, 20C, 20D ... substrate with via, 20a ... inter-chip region,
21 ... Support substrate, 22 ... Fixing material, 23 ... Deletion part, 23a ... Clearance,
29, 29B ... pseudo wafer, 30, 43 ... protective film, 33 ... solder bump,
35, 46 ... Mask, 36 ... Opening, 37 ... Exposure light, 38 ... Via hole,
39 ... Printed circuit board, 41 ... Front surface, 42 ... Back surface, 45 ... Cutting line, 47 ... Nesting,
47a ... projecting portion, 47b ... connecting portion, 48 ... thermocompression bonding press,
50, 50A, 51, 51A, 52A, 52B, 53, 54A, 54B ... Semiconductor device,
55 ... Mold, 55a ... Cavity, 56 ... Squeegee, L ... UV

Claims (38)

一方の面側に電極が設けられ、この電極面以外の少なくとも側面が保護物質層で覆われているチップ部品を有する半導体装置において、
前記チップ部品の少なくとも側方に絶縁物質層が被着され,
前記絶縁物質層をこの両面に貫通して形成された貫通孔に、第１の導電材が設けられ 、
前記電極と前記第１の導電材とが別の導電材を介して接続され、
前記電極が少なくとも、前記一方の面とは反対側の他方の面側に電気的に取り出され ている
ことを特徴とする、半導体装置。 In a semiconductor device having a chip component in which an electrode is provided on one surface side and at least a side surface other than the electrode surface is covered with a protective material layer,
An insulating material layer is deposited on at least the sides of the chip component;
A first conductive material is provided in a through hole formed through the insulating material layer on both sides,
The electrode and the first conductive material are connected via another conductive material,
The semiconductor device, wherein the electrode is electrically taken out at least on the other surface side opposite to the one surface. 前記チップ部品の側方において、前記保護物質層とは別の前記絶縁物質層の前記貫通孔に、前記第１の導電材が設けられている、請求項１に記載した半導体装置。   2. The semiconductor device according to claim 1, wherein the first conductive material is provided in the through hole of the insulating material layer different from the protective material layer on a side of the chip component. 前記チップ部品の側方において、前記絶縁物質層を兼ねる前記保護物質層の前記貫通孔に前記第１の導電材が設けられている、請求項１に記載した半導体装置。   2. The semiconductor device according to claim 1, wherein the first conductive material is provided in the through hole of the protective material layer that also serves as the insulating material layer on a side of the chip component. 前記第１の導電材が、前記他方の面側又は／及び前記一方の面側に形成された外部端子に取り出されている、請求項１に記載した半導体装置。   The semiconductor device according to claim 1, wherein the first conductive material is taken out to an external terminal formed on the other surface side and / or the one surface side. 前記第１の導電材が、これとは別の配線を介して前記外部端子に取り出されている、請求項４に記載した半導体装置。   The semiconductor device according to claim 4, wherein the first conductive material is taken out to the external terminal via a wiring different from the first conductive material. 前記チップ部品の前記他方の面側が露出している、請求項１に記載した半導体装置。   The semiconductor device according to claim 1, wherein the other surface side of the chip component is exposed. 一方の面側に電極が設けられ、この電極面以外の少なくとも側面が保護物質層で覆われているチップ部品を有する半導体装置を製造する方法において、
前記チップ部品を配するための欠除部を有し、かつ両面間に形成した貫通孔に第１の 導電材を設けた絶縁物質層を作製する工程と、
前記絶縁物質層を支持体上に固定する工程と、
前記電極面の側にて、前記チップ部品を前記欠除部内にて支持体上に固定する工程と 、
前記チップ部品及び前記絶縁物質層の少なくとも側面を前記保護物質層によって覆う 工程と、
前記保護物質層によって前記チップ部品と前記絶縁物質層とが一体化されてなる疑似 ウェーハを前記支持体から分離して疑似ウェーハを作製する工程と、
前記疑似ウェーハにおいて、前記チップ部品の前記電極を前記第１の導電材とは別の 導電材によって前記第１の導電材に接続する工程と、
前記一方の面とは反対側の他方の面とのうち、少なくとも前記他方の面に前記電極を 電気的に取り出す工程と、
複数の前記チップ部品間で、前記絶縁物質層又は前記保護物質層を切断して各半導体 装置に個片化する工程と
を有することを特徴とする、半導体装置の製造方法。 In a method of manufacturing a semiconductor device having a chip component in which an electrode is provided on one surface side and at least a side surface other than the electrode surface is covered with a protective material layer,
Producing an insulating material layer having a first conductive material in a through-hole formed between both surfaces and having a notch for arranging the chip component;
Fixing the insulating material layer on a support;
Fixing the chip component on the support in the notch portion on the electrode surface side; and
Covering at least side surfaces of the chip component and the insulating material layer with the protective material layer;
Separating a pseudo wafer in which the chip component and the insulating material layer are integrated by the protective material layer from the support, and producing a pseudo wafer;
In the pseudo-wafer, the step of connecting the electrode of the chip component to the first conductive material by a conductive material different from the first conductive material;
Electrically extracting the electrode from at least the other surface of the other surface opposite to the one surface;
And a step of cutting the insulating material layer or the protective material layer into a plurality of individual semiconductor devices between the plurality of chip components. 前記他方の面側において前記疑似ウェーハの前記保護物質層を部分的に除去して、前記第１の導電材を露出させる、請求項７に記載した半導体装置の製造方法。   The method of manufacturing a semiconductor device according to claim 7, wherein the protective material layer of the pseudo wafer is partially removed on the other surface side to expose the first conductive material. 前記チップ部品の前記他方の面側の少なくとも一部を露出させる、請求項７に記載した半導体装置の製造方法。   The method for manufacturing a semiconductor device according to claim 7, wherein at least a part of the other surface side of the chip component is exposed. 特性測定により良品と判定された前記チップ部品を有する前記疑似ウェーハを作製する、請求項７に記載した半導体装置の製造方法。   The method for manufacturing a semiconductor device according to claim 7, wherein the pseudo wafer having the chip parts determined to be non-defective by characteristic measurement is manufactured. 前記疑似ウェーハの状態において前記チップ部品の特性測定を行い、良品のチップ部品又はチップ状電子部品を選択する、請求項７に記載した半導体装置の製造方法。   The method for manufacturing a semiconductor device according to claim 7, wherein characteristics of the chip component are measured in a state of the pseudo wafer, and a good chip component or a chip-shaped electronic component is selected. 請求項１〜６のいずれか１項に記載した半導体装置が、少なくとも前記他方の面側にてプリント配線板に接続されている、半導体装置の実装構造。   A semiconductor device mounting structure, wherein the semiconductor device according to claim 1 is connected to a printed wiring board at least on the other surface side. 前記半導体装置の複数個が、前記一方の面側及び前記他方の面側間での接続下で積層されている、請求項１２に記載した半導体装置の実装構造。   The mounting structure of a semiconductor device according to claim 12, wherein a plurality of the semiconductor devices are stacked under connection between the one surface side and the other surface side. 一方の面側に電極が設けられ、この電極面以外の少なくとも側面が保護物質層で覆われているチップ部品の複数個が、前記保護物質層を介して互いに一体化されてなる疑似ウェーハにおいて、
前記チップ部品の少なくとも側方に絶縁物質層が被着され、
前記絶縁物質層をこの両面に貫通して形成された貫通孔に、第１の導電材が設けられ 、
前記電極と前記第一の導電材とが別の導電材を介して接続され、
前記電極が少なくとも、前記一方の面とは反対側の他方の面側に電気的に取り出され ている
ことを特徴とする、疑似ウェーハ。 In a pseudo wafer in which an electrode is provided on one surface side and a plurality of chip parts in which at least a side surface other than the electrode surface is covered with a protective material layer are integrated with each other via the protective material layer,
An insulating material layer is deposited on at least the sides of the chip component;
A first conductive material is provided in a through hole formed through the insulating material layer on both sides,
The electrode and the first conductive material are connected via another conductive material,
The pseudo-wafer, wherein the electrode is electrically taken out to at least the other surface side opposite to the one surface. 前記チップ部品の側方において、前記保護物質層とは別の前記絶縁物質層の前記貫通孔に、前記第１の導電材が設けられている、請求項１４に記載した疑似ウェーハ。   The pseudo-wafer according to claim 14, wherein the first conductive material is provided in the through hole of the insulating material layer different from the protective material layer on a side of the chip component. 前記チップ部品の側方において、前記絶縁物質層を兼ねる前記保護物質層の前記貫通孔に前記第１の導電材が設けられている、請求項１４に記載した疑似ウェーハ。   The pseudo wafer according to claim 14, wherein the first conductive material is provided in the through hole of the protective material layer that also serves as the insulating material layer on a side of the chip component. 前記第１の導電材が、前記他方の面側又は／及び前記一方の面側に形成された外部端子に取り出されている、請求項１４に記載した疑似ウェーハ。   The pseudo wafer according to claim 14, wherein the first conductive material is taken out to an external terminal formed on the other surface side and / or the one surface side. 前記第１の導電材が、これとは別の配線を介して前記外部端子に取り出されている、請求項１７に記載した疑似ウェーハ。   The pseudo-wafer according to claim 17, wherein the first conductive material is taken out to the external terminal via a wiring different from the first conductive material. 前記チップ部品の前記他方の面側が露出している、請求項１４に記載した疑似ウェーハ。   The pseudo wafer according to claim 14, wherein the other surface side of the chip component is exposed. 特性測定により良品と判定された前記チップ部品を有する、請求項１４に記載した疑似ウェーハ。   The pseudo-wafer according to claim 14, wherein the pseudo-wafer includes the chip part determined to be a non-defective product by characteristic measurement. 前記チップ部品の特性測定を行い、良品のチップ部品又はチップ状電子部品を選択する、請求項１４に記載した疑似ウェーハ。   The pseudo-wafer according to claim 14, wherein characteristics of the chip component are measured and a good chip component or a chip-shaped electronic component is selected. 一方の面側に電極が設けられ、この電極面以外の少なくとも側面が保護物質層で覆われているチップ部品の複数個が、前記保護物質層を介して互いに一体化されてなる疑似ウェーハを製造する方法において、
前記チップ部品を配するための欠除部を有し、かつ両面間に形成した貫通孔に第１の 導電材を設けた絶縁物質層を作製する工程と、
前記絶縁物質層を支持体上に固定する工程と、
前記電極面の側にて、前記チップ部品を前記欠除部内にて支持体上に固定する工程と 、
前記チップ部品及び前記絶縁物質層の少なくとも側面を前記保護物質層によって覆う 工程と、
前記保護物質層によって前記チップ部品と前記絶縁物質層とが一体化されてなる疑似 ウェーハを前記支持体から分離する工程と、
前記チップ部品の前記電極を前記第１の導電材とは別の導電材によって前記第１の導 電材に接続する工程と、
前記一方の面とは反対側の他方の面とのうち、少なくとも前記他方の面に前記電極を 電気的に取り出す工程と
を有することを特徴とする、疑似ウェーハの製造方法。 Manufactures a pseudo wafer in which an electrode is provided on one surface side and a plurality of chip parts each having at least a side surface other than the electrode surface covered with a protective material layer are integrated with each other via the protective material layer In the way to
A step of producing an insulating material layer having a first conductive material in a through-hole formed between both surfaces and having a notch for arranging the chip component;
Fixing the insulating material layer on a support;
Fixing the chip component on the support in the notch portion on the electrode surface side; and
Covering at least side surfaces of the chip component and the insulating material layer with the protective material layer;
Separating the pseudo wafer in which the chip component and the insulating material layer are integrated by the protective material layer from the support;
Connecting the electrode of the chip component to the first conductive material by a conductive material different from the first conductive material;
And a step of electrically taking out the electrode from at least the other surface of the other surface opposite to the one surface. 前記他方の面側において前記保護物質層を部分的に除去して、前記第１の導電材を露出させる、請求項２２に記載した疑似ウェーハの製造方法。   23. The method for manufacturing a pseudo wafer according to claim 22, wherein the protective material layer is partially removed on the other surface side to expose the first conductive material. 前記チップ部品の前記他方の面側の少なくとも一部を露出させる、請求項２２に記載した疑似ウェーハの製造方法。   The method for manufacturing a pseudo wafer according to claim 22, wherein at least a part of the other surface side of the chip part is exposed. 特性測定により良品と判定された前記チップ部品を有する前記疑似ウェーハを作製する、請求項２２に記載した疑似ウェーハの製造方法。   The method for manufacturing a pseudo wafer according to claim 22, wherein the pseudo wafer having the chip parts determined to be non-defective by characteristic measurement is manufactured. 前記疑似ウェーハの状態において前記チップ部品の特性測定を行い、良品のチップ部品又はチップ状電子部品を選択する、請求項２２に記載した疑似ウェーハの製造方法。   23. The method of manufacturing a pseudo wafer according to claim 22, wherein a characteristic of the chip component is measured in the state of the pseudo wafer, and a good chip component or a chip-shaped electronic component is selected. 一方の面側に電極が設けられ、この電極面以外の少なくとも側面が保護物質層で覆われているチップ部品を有する半導体装置を製造する方法において、
支持体上に前記チップ部品を固定する工程と、
前記チップ部品の側方にて第１の導電材を前記支持体上に固定する工程と、
前記第１の導電材を保護物質材料に埋設する工程と、
前記保護物質材料を前記チップ部品の側面に被着して前記保護物質層を形成する工程 と、
前記保護物質層によって前記チップ部品が一体化されてなる疑似ウェーハを前記支持 体から分離する工程と、
前記疑似ウェーハにおいて、前記チップ部品の前記電極を前記第１の導電材とは別の 導電材によって前記第１の導電材に接続する工程と、
前記一方の面とこれとは反対側の他方の面とのうち、少なくとも前記他方の面に前記 電極を電気的に取り出す工程と、
複数の前記チップ部品間で、前記保護物質層を切断して各半導体装置に個片化する工 程と
を有することを特徴とする、半導体装置の製造方法。 In a method of manufacturing a semiconductor device having a chip component in which an electrode is provided on one surface side and at least a side surface other than the electrode surface is covered with a protective material layer,
Fixing the chip component on a support;
Fixing the first conductive material on the support at the side of the chip component;
Embedding the first conductive material in a protective material;
Depositing the protective substance material on the side surface of the chip component to form the protective substance layer;
Separating the pseudo wafer in which the chip parts are integrated by the protective substance layer from the support;
In the pseudo-wafer, connecting the electrode of the chip component to the first conductive material by a conductive material different from the first conductive material;
A step of electrically taking out the electrode to at least the other surface of the one surface and the other surface on the opposite side;
A method of manufacturing a semiconductor device, comprising: a step of cutting the protective material layer into a plurality of individual semiconductor devices between the plurality of chip components. 前記チップ部品を配するための欠除部を有し、かつ両面間に形成した貫通孔に前記第１の導電材を設けた前記保護物質材料層を作製する工程と、
前記保護物質材料層を支持体上に固定する工程と、
前記電極面の側にて前記チップ部品を前記欠除部内にて支持体上に固定する工程と、
前記保護物質材料層を加熱により流動化させ、前記チップ部品の少なくとも側面を前 記保護物質層によって覆う工程と
を有する、請求項２７に記載した半導体装置の製造方法。 Producing the protective material layer having a first conductive material in a through-hole formed between both surfaces and having a notch for arranging the chip component;
Fixing the protective substance material layer on a support;
Fixing the chip component on the support on the electrode surface side in the notch, and
28. The method of manufacturing a semiconductor device according to claim 27, further comprising: fluidizing the protective substance material layer by heating, and covering at least a side surface of the chip component with the protective substance layer. 前記他方の面側において前記疑似ウェーハの前記保護物質層を部分的に除去して、前記第１の導電材を露出させる、請求項２７に記載した半導体装置の製造方法。   28. The method of manufacturing a semiconductor device according to claim 27, wherein the protective material layer of the pseudo wafer is partially removed on the other surface side to expose the first conductive material. 前記チップ部品の前記他方の面側の少なくとも一部を露出させる、請求項２７に記載した半導体装置の製造方法。   28. The method of manufacturing a semiconductor device according to claim 27, wherein at least a part of the other surface side of the chip component is exposed. 特性測定により良品と判定された前記チップ部品を有する前記疑似ウェーハを作製する、請求項２７に記載した半導体装置の製造方法。   28. The method of manufacturing a semiconductor device according to claim 27, wherein the pseudo wafer having the chip part determined to be non-defective by characteristic measurement is manufactured. 前記疑似ウェーハの状態において前記チップ部品の特性測定を行い、良品のチップ部品又はチップ状電子部品を選択する、請求項２７に記載した半導体装置の製造方法。   28. The method of manufacturing a semiconductor device according to claim 27, wherein characteristics of the chip component are measured in the state of the pseudo wafer, and a good chip component or a chip-shaped electronic component is selected. 一方の面側に電極が設けられ、この電極面以外の少なくとも側面が保護物質層で覆われているチップ部品の複数個が、前記保護物質層を介して互いに一体化されてなる疑似ウェーハを製造する方法において、
支持体上に前記チップ部品を固定する工程と、
前記チップ部品の側方にて第１の導電材を前記支持体上に固定する工程と、
前記第１の導電材を保護物質材料に埋設する工程と、
前記保護物質材料を前記チップ部品の側面に被着して前記保護物質層を形成する工程 と、
前記保護物質層によって前記チップ部品が一体化されてなる疑似ウェーハを前記支持 体から分離する工程と、
前記疑似ウェーハにおいて、前記チップ部品の前記電極を前記第１の導電材とは別の 導電材によって前記第１の導電材に接続する工程と、
前記一方の面とこれとは反対側の他方の面とのうち、少なくとも前記他方の面に前記 電極を電気的に取り出す工程と
を有することを特徴とする、疑似ウェーハの製造方法。 Manufactures a pseudo wafer in which an electrode is provided on one surface side and a plurality of chip parts each having at least a side surface other than the electrode surface covered with a protective material layer are integrated with each other via the protective material layer In the way to
Fixing the chip component on a support;
Fixing the first conductive material on the support at the side of the chip component;
Embedding the first conductive material in a protective material;
Depositing the protective substance material on the side surface of the chip component to form the protective substance layer;
Separating the pseudo wafer in which the chip parts are integrated by the protective substance layer from the support;
In the pseudo-wafer, connecting the electrode of the chip component to the first conductive material by a conductive material different from the first conductive material;
A method of manufacturing a pseudo wafer, comprising: a step of electrically extracting the electrode from at least one of the one surface and the other surface opposite to the one surface. 前記チップ部品を配するための欠除部を有し、かつ両面間に形成した貫通孔に前記第１の導電材を設けた前記保護物質材料層を作製する工程と、
前記保護物質材料層を支持体上に固定する工程と、
前記電極面の側にて前記チップ部品を前記欠除部内にて支持体上に固定する工程と、
前記保護物質材料層を加熱により流動化させ、前記チップ部品の少なくとも側面を前 記保護物質層によって覆う工程と
を有する、請求項３３に記載した疑似ウェーハの製造方法。 Producing the protective material layer having a first conductive material in a through-hole formed between both surfaces and having a notch for arranging the chip component;
Fixing the protective substance material layer on a support;
Fixing the chip component on the support on the electrode surface side in the notch, and
The pseudo-wafer manufacturing method according to claim 33, further comprising: fluidizing the protective substance material layer by heating and covering at least a side surface of the chip component with the protective substance layer. 前記他方の面側において前記疑似ウェーハの前記保護物質層を部分的に除去して、前記第１の導電材を露出させる、請求項３３に記載した疑似ウェーハの製造方法。   34. The method of manufacturing a pseudo wafer according to claim 33, wherein the protective material layer of the pseudo wafer is partially removed on the other surface side to expose the first conductive material. 前記チップ部品の前記他方の面側の少なくとも一部を露出させる、請求項３３に記載した疑似ウェーハの製造方法。   The pseudo-wafer manufacturing method according to claim 33, wherein at least a part of the other surface side of the chip part is exposed. 特性測定により良品と判定された前記チップ部品を有する、請求項３３に記載した疑似ウェーハの製造方法。   34. The method for manufacturing a pseudo wafer according to claim 33, wherein the chip component is determined to be a non-defective product by characteristic measurement. 前記チップ部品の特性測定を行い、良品のチップ部品又はチップ状電子部品を選択する、請求項３３に記載した疑似ウェーハの製造方法。   34. The method for manufacturing a pseudo wafer according to claim 33, wherein characteristics of the chip component are measured and a good chip component or a chip-shaped electronic component is selected.
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