KR20140081345A - Semiconductor memory device - Google Patents

Semiconductor memory device Download PDF

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Publication number
KR20140081345A
KR20140081345A KR1020120150996A KR20120150996A KR20140081345A KR 20140081345 A KR20140081345 A KR 20140081345A KR 1020120150996 A KR1020120150996 A KR 1020120150996A KR 20120150996 A KR20120150996 A KR 20120150996A KR 20140081345 A KR20140081345 A KR 20140081345A
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KR
South Korea
Prior art keywords
signal
boot
unit
memory device
delay unit
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Application number
KR1020120150996A
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Korean (ko)
Inventor
이주현
전준현
송호욱
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에스케이하이닉스 주식회사
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Priority to KR1020120150996A priority Critical patent/KR20140081345A/en
Publication of KR20140081345A publication Critical patent/KR20140081345A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G11C29/787—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using a fuse hierarchy
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/808—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a flexible replacement scheme
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

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  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)

Abstract

The present invention relates to a semiconductor memory device, and is a technique for preventing a malfunction of a semiconductor memory device including a fuse array. According to another aspect of the present invention, there is provided a semiconductor memory device including a fuse array in which address information of a defective cell is stored, a boot up control section for activating and outputting a boot up signal according to a power up signal and deactivating and outputting a boot up signal according to a count end signal, And a control unit for generating a drive signal for reading the address information, and when the reset signal is activated, the boot operation is terminated by deactivating the boot-up signal irrespective of the count end signal.

Description

Semiconductor memory device < RTI ID = 0.0 >

The present invention relates to a semiconductor memory device, and is a technique for preventing a malfunction of a semiconductor memory device including a fuse array.

Generally, a semiconductor memory device includes a large number of memory cells, and as the process technology develops, the degree of integration increases and the number of the memory cells increases. If any one of these memory cells is defective, the corresponding semiconductor memory device malfunctions. Therefore, the semiconductor memory device including the defective cell must be discarded because it can not perform the desired operation.

However, as the process technology of the semiconductor memory device is developed these days, only a small amount of defects occur in a small amount of memory cells. In order to dispose of the entire semiconductor memory device as a defective product due to a small amount of defects, It is very inefficient when viewed. Therefore, in order to compensate for this, the semiconductor memory device further includes a redundant memory cell in addition to a normal memory cell.

That is, when a defect occurs in a cell, a redundancy control circuit is used to switch the connection to a cell included in the redundancy circuit instead of a cell in which a defect occurs, when access is requested to the cell in advance through a test. Here, the redundancy circuit is an extra memory cell set separately provided in a memory cell, and is used as a replacement cell of a cell where a defect occurs.

The redundancy memory cell is a circuit provided for the purpose of repairing a memory cell (hereinafter, referred to as " repair target memory cell ") in which a failure occurs in a normal memory cell.

More specifically, for example, when a memory cell to be repaired is accessed during a read and a write operation, a normal memory cell is accessed internally instead of the memory cell to be repaired. At this time, the memory cell to be accessed is a redundancy memory cell. Therefore, when the address corresponding to the memory cell to be repaired is inputted, the semiconductor memory device performs an operation (hereinafter referred to as a repair operation) for accessing the redundancy memory cell other than the memory cell to be repaired (hereinafter referred to as a repair operation) The semiconductor memory device is guaranteed to operate normally.

On the other hand, in order to perform a repair operation, the semiconductor memory device requires not only redundancy memory cells but also other circuit configurations, and one of them is a repair fuse circuit. The repair fuse circuit is for storing an address corresponding to the memory cell to be repaired (hereinafter referred to as a repair object address). The repair fuse circuit programs the repair target address in the fuse. The semiconductor device performs the repair operation using the thus-programmed repair target address.

The present invention is characterized in that when a fuse array information is read according to a boot-up signal, a malfunction occurring during a read operation is prevented.

A semiconductor memory device according to an embodiment of the present invention includes a fuse array in which address information of a defective cell is stored; Up control unit for activating and outputting a boot-up signal according to a power-up signal and deactivating and outputting a boot-up signal according to a count end signal; And a control unit for generating a drive signal for reading address information according to a boot up signal, wherein the boot up control unit deactivates the boot up signal irrespective of the count end signal upon activation of the reset signal, .

According to the present invention, when the fuse array information is read in accordance with the boot-up signal, the read operation is terminated when the reset signal is activated during the read operation, thereby preventing the erroneous operation of the DRAM do.

It will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. .

1 is a configuration diagram of a semiconductor memory device according to an embodiment of the present invention;
FIG. 2 is a detailed circuit diagram of the boot-up control unit of FIG. 1. FIG.
FIG. 3A and FIG. 3B are timing diagrams for explaining the operation of the semiconductor memory device according to the embodiment of the present invention; FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

As the size of each element constituting the semiconductor integrated circuit device is reduced and the number of elements included in one semiconductor chip is increased, the level of defect density is also increasing. This increase in the defect density is a direct cause of lowering the yield of the semiconductor device. If the defect density increases significantly, the wafer on which semiconductor elements are to be formed must be discarded.

In order to lower the defect density, a redundancy circuit for replacing a defective cell with an extra cell has been proposed. The redundancy circuit (or fuse circuit) may be provided for each of a row-based wiring (e.g., a word line) and a column-based wiring (e.g., a bit line) in the case of a semiconductor memory device.

The redundancy circuit includes a fuse array for storing address information of a defective cell. The fuse array is comprised of a plurality of fuse sets including a plurality of fuse wirings. Each fuse set then programs the information in such a way as to dissolve the fuse with an overcurrent.

1 is a configuration diagram of a semiconductor memory device according to an embodiment of the present invention.

The embodiment of the present invention includes a boot up control unit 100, a control unit 200, a fuse array 300, a row decoder 400, a column decoder 500 and a bit line sense amplifier 600.

Here, the boot-up control unit 100 generates the boot-up signal BOOTUP by combining the reset signal RESET, the power-up signal PWRUP and the feedback-input boot-up signal BOOTUP. Up control unit 100 activates the boot-up signal BOOTUP in accordance with the power-up signal PWRUP in order to read the information of the fuse array 300. [

The fuse information of the fuse array 300 is read during a period in which the boot-up signal BOOTUP is activated. Then, after a certain period of time after the boot-up signal BOOTUP is activated, the count-end signal CNTEND is activated and the boot-up signal BOOTUP is inactivated.

The count end signal CNTEND is a control signal for terminating the read operation. At this time, when the reset signal RESET is activated in the state that the boot-up signal BOOTUP is activated according to the power-up signal PWRUP, the read operation is terminated even if the read operation is not completed.

The reset signal RESET is a signal input by a mode register write (MRW) command. For example, the reset signal RESET is included in the Power Ramp and Initialization Sequence in the DDR3 specification of the main memory and is assigned a separate input pin for the reset signal RESET.

The control unit 200 outputs a driving signal to the row decoder 400 and the column decoder 500 according to the control signal CON and the boot-up signal BOOTUP. The controller 200 outputs a drive signal for controlling the read operation of the fuse array 300 to the column decoder 500 when the boot-up signal BOOTUP is activated.

The control signal CON may be a control signal of the row decoder 400 for selecting a row line of the fuse array 300 or a column decoder 500 control signal for selecting a column line of the fuse array 300.

The column decoder 500 selects the corresponding bit line of the fuse array 300 according to the column selection signal YS and the driving signal applied from the control unit 200. [ When the column decoder 500 operates according to the column selection signal YS, the driving signal of the controller 200 is transmitted to the bit line of the fuse array 300.

The fuse array 300 performs a read operation in accordance with a driving signal transmitted through the column decoder 500. The fuse array 300 includes a plurality of fuse sets as the row and column lines to form a matrix structure.

The fuse array 300 stores the address information of the defective cell according to the rupture operation and outputs the stored information to the bit line sense amplifier 600 according to the driving signal transmitted through the column decoder 500. Here, each fuse set may consist of an electrical fuse (E-fuse) that programs information in a manner that melts the fuse with an overcurrent.

The bit line sense amplifier 600 senses and amplifies the address information applied from the fuse array 300 according to the read signal RD, and outputs it to the fuse data line FDL.

2 is a detailed circuit diagram of the boot-up control unit 100 of FIG.

The boot up control unit 100 includes delay units 110, 120 and 140, an input unit 130 and a latch unit 150.

Here, the delay unit 110 delays the power-up signal PWRUP by a predetermined time. The delay unit 120 delays the output of the delay unit 110 by a predetermined time. The delay unit 120 includes a plurality of inverters IV1 to IV7 serially connected between the output terminal of the delay unit 110 and the input terminal of the NAND gate ND1. Inverters IV1 to IV7 delay the output of the delay unit 110 in reverse.

The input unit 130 logically combines the count end signal CNTEND and the reset signal RESET. The input unit 130 performs an OR operation on the count end signal CNTEND and the reset signal RESET. The input unit 130 outputs a high level signal when at least one of the count end signal CNTEND and the reset signal RESET is activated.

This input 130 includes a NOR gate NOR1 and an inverter IV8. The NOR gate NOR1 calculates the count end signal CNTEND and the reset signal RESET in the NOR operation. The inverter IV8 inverts the output of the NOR gate NOR1.

The delay unit 140 delays the output of the input unit 130 by a predetermined time. The delay unit 140 includes a plurality of inverters IV9 to IV15 connected in series between the output terminal of the input unit 130 and the input terminal of the NAND gate ND3. Inverters IV9 to IV15 reverse the output of inverter IV8.

The latch unit 150 includes a plurality of NAND gates ND1 to ND4. Here, the NAND gate ND1 performs a NAND operation on the outputs of the delay units 110 and 120. [ The NAND gate ND2 performs NAND operation on the outputs of the NAND gates ND1 and ND4 and outputs the boot-up signal BOOTUP. The NAND gate ND3 performs a NAND operation on the output of the input unit 130 and the output of the delay unit 140. [ The NAND gate ND4 performs NAND operation on the output of the NAND gate ND3 and the boot-up signal BOOTUP.

Also, the counting section 160 counts up the boot-up signal BOOTUP during the read period and outputs a count end signal CNTEND. That is, the counting unit 160 activates the count end signal CNTEND to the high level after outputting the counting operation by the predetermined number of times of reading.

The operation of the present invention having such a configuration will be described with reference to operation timing diagrams of FIGS. 3A and 3B.

FIG. 3A shows a case where the count end signal CNTEND is normally operated during the activation period of the boot-up signal BOOTUP, and FIG. 3B shows a case where the count end signal CNTEND has abnormally operated during the activation period of the boot-up signal BOOTUP.

First, at time Tb, the power-up signal PWRUP is activated to a high level. The delay unit 110 delays the power-up signal PWRUP by a predetermined time. The output signal of the delay unit 110 is delayed by the delay time of the inverters IV1 to IV7 and transits to the low level. The output signal of the delay unit 120 is input to the latch unit 150 and the boot-up signal BOOTUP is output to the low level according to the latch unit 150. [

At this time, in the period Tb, the boot-up signal BOOTUP maintains a low level. In the period Tb, the count end signal CNTEND and the reset signal RESET are maintained at a low level.

Thus, the boot-up signal BOOTUP maintains a low level in the period Tb. Since the boot-up signal BOOTUP is at a low level, the counting unit 160 does not perform the counting operation.

Thereafter, when the delay time of the delay unit 110 elapses, the input of the latch unit 150 changes and the boot-up signal BOOTUP transits to the high level in the period Tc. When the boot-up signal BOOTUP transits to the high level, the address information of the defective cell stored in the fuse array 300 is read through the control unit 200 and the column decoder 500.

The read operation of the fuse array 300 continues during the period in which the boot-up signal BOOTUP transitions to the high level in the normal operation mode. In the DRAM, when the boot-up signal BOOTUP is activated, the fuse information must be read before the operation of the internal memory is performed.

When the boot-up signal BOOTUP transits to the high level, the counting unit 160 counts the boot-up signal BOOTUP during the read period. Also, the counting unit 160 counts up the boot-up signal BOOTUP and activates the count end signal CNTEND to a high level when the predetermined read period is completed.

When the count end signal CNTEND becomes a high level, the output of the input unit 130 transits to a high level. Then, when transition is made to the high level by the count end signal CNTEND, the boot-up signal BOOTUP transits to the low level after the delay time of the delay unit 140. When the boot-up signal BOOTUP transits to the low level, the read operation of the fuse array 300 is terminated.

3A shows a case where the boot-up signal BOOTUP transits to the high level and the count end signal CNTEND transits to the high level normally before the time Td. The reset signal RESET transits to the high level after the time point Td, so that the read operation of the fuse array 300 is not hindered.

On the other hand, FIG. 3B shows a case where the boot-up signal BOOTUP transits to the high level and the count end signal CNTEND does not normally transition to the high level before the time Td and transits to the high level after the time Td.

The reset signal RESET transitions to the high level before the count end signal CNTEND at the point of time Td while the boot-up signal BOOTUP is at the high level and the read operation of the fuse array 300 is being performed while the count end signal CNTEND is low level .

That is, the read operation may not be completed before the reset signal RESET is activated due to various reasons such as skew variation after the boot-up signal BOOTUP transitions to the high level and the read operation is performed. The operation of reading the information of the fuse array 300 until the reset signal RESET is activated must be terminated in order for normal DRAM operation to be performed.

Then, the output of the latch unit 150 changes according to the reset signal RESET, and the boot-up signal BOOTUP transits to the low level. Since the count end signal CNTEND transits to the high level later than the reset signal RESET at the time Td, the read operation of the fuse array 300 is forcibly terminated.

If the read operation continues despite the transition of the reset signal RESET to the high level during the read operation according to the boot-up signal BOOTUP, the memory cell may not operate normally and malfunction may occur.

As the memory capacity is becoming higher and higher, the capacity of repairing fuses is also increasing. Accordingly, a substantial memory operation can be performed in a state in which the boot-up signal BOOTUP transits to the high level and the read operation is performed. In this case, when the reset signal RESET transitions to the high level in order to perform a normal memory operation, the read operation is forcibly terminated.

Claims (10)

A fuse array in which address information of a defective cell is stored;
A boot up control unit for activating and outputting a boot up signal according to a power up signal and deactivating and outputting the boot up signal according to a count end signal; And
And a control unit for generating a drive signal for reading the address information according to the boot-up signal,
Wherein the boot-up control unit deactivates the boot-up signal irrespective of the count end signal when the reset signal is activated, thereby terminating the read operation of the fuse array. The semiconductor memory device according to claim 1, further comprising a column decoder for selectively outputting the drive signal to the fuse array in accordance with a column select signal. 2. The apparatus of claim 1, wherein the boot-up control unit
And activates the boot-up signal after a predetermined time when the power-up signal is activated, and deactivates the boot-up signal when the count-end signal is activated or the reset signal is activated. 2. The apparatus of claim 1, wherein the boot-up control unit
A first delay unit delaying the power-up signal by a predetermined time;
A second delay unit delaying an output of the first delay unit by a predetermined time;
An input unit for combining the count end signal and the reset signal;
A third delay unit delaying an output of the input unit by a predetermined time;
A latch unit for latching outputs of the first delay unit, the second delay unit, the input unit, and the third delay unit and outputting the boot-up signal; And
And a counting unit counting the boot-up signal and outputting the count end signal. 5. The semiconductor memory device according to claim 4, wherein the input section performs an OR operation on the count end signal and the reset signal. 5. The apparatus of claim 4, wherein the input unit
A No Gate for performing a NOR operation on the count end signal and the reset signal; And
And an inverter for inverting the output of said Noah gate. The semiconductor memory device according to claim 4, wherein the second delay unit includes a plurality of inverters for inverting and delaying the output of the first delay unit. The semiconductor memory device according to claim 4, wherein the third delay unit includes a plurality of inverters for inverting and delaying the output of the input unit. The semiconductor memory device according to claim 4, wherein the latch unit includes a plurality of NAND gates for latching the outputs of the first delay unit, the second delay unit, the input unit, and the third delay unit. The semiconductor memory device according to claim 1, wherein the fuse array includes a plurality of electric fuses.
KR1020120150996A 2012-12-21 2012-12-21 Semiconductor memory device KR20140081345A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9524762B1 (en) 2015-05-27 2016-12-20 SK Hynix Inc. Semiconductor devices having initialization circuits and semiconductor systems including the same
US11138316B2 (en) * 2019-06-28 2021-10-05 Intel Corporation Apparatus and method to provide secure fuse sense protection against power attacks

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9524762B1 (en) 2015-05-27 2016-12-20 SK Hynix Inc. Semiconductor devices having initialization circuits and semiconductor systems including the same
US11138316B2 (en) * 2019-06-28 2021-10-05 Intel Corporation Apparatus and method to provide secure fuse sense protection against power attacks

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