KR20140075532A - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
- Publication number
- KR20140075532A KR20140075532A KR1020120143969A KR20120143969A KR20140075532A KR 20140075532 A KR20140075532 A KR 20140075532A KR 1020120143969 A KR1020120143969 A KR 1020120143969A KR 20120143969 A KR20120143969 A KR 20120143969A KR 20140075532 A KR20140075532 A KR 20140075532A
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- South Korea
- Prior art keywords
- layer
- type
- intermediate layer
- anode
- recombination
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title abstract description 23
- 230000006798 recombination Effects 0.000 claims abstract description 32
- 238000005215 recombination Methods 0.000 claims abstract description 27
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- 230000005684 electric field Effects 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 7
- 238000011084 recovery Methods 0.000 description 14
- 239000000969 carrier Substances 0.000 description 6
- 238000010894 electron beam technology Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910001385 heavy metal Inorganic materials 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- -1 expands Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/8613—Mesa PN junction diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66136—PN junction diodes
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
Abstract
The present invention relates to an intermediate layer of a first conductivity type; A recombination portion of the first conductivity type formed in the intermediate layer and having a higher concentration than the intermediate layer; And an anode layer of a second conductivity type formed in contact with an upper portion of the intermediate layer; To a semiconductor device.
Description
The present invention relates to a semiconductor device.
Recently, high-speed switching diodes are required to have fast switching characteristics and soft recovery characteristics.
Since pn junction diodes commonly used in diodes use a small number of carriers, the forward voltage can be lowered by the conductive modulation effect.
However, because of the reverse recovery characteristic due to a small number of carriers, high-speed switching characteristics are impaired.
The reverse recovery characteristic means that when a voltage is applied in a reverse direction in a state where a forward current flows in a pn junction diode, a large reverse current flows instantaneously because a minority carrier injected in the pn junction moves in the opposite direction, Flowing current until it flows out or disappears.
The fast switching diode has a short recovery time (trr) until the reverse current becomes zero and a soft recovery characteristic by smoothing the reverse current waveform.
High-speed switching diodes are divided into Fast Recovery Diode (FRD), High Efficiency Diode (HED) and Schottky Barrier Diode (SBD).
Among them, FRD is structurally similar to a general pn diode but diffuses impurities into silicon by impurities such as platinum and gold or electron beam and neutron irradiation to increase the center of recombination of electrons and holes, Lt; RTI ID = 0.0 > decay. ≪ / RTI >
However, FRD increases the center of recombination by electron beam, neutron irradiation, heavy metal diffusion, etc., and consequently increases the forward voltage drop to add power.
Therefore, fast switching characteristics and soft recovery characteristics are required by increasing the recombination center without increasing the forward voltage drop.
Patent Document 1 described in the following prior art document describes the invention related to PIN diodes.
The invention described in Patent Document 1 is an invention related to a semiconductor device characterized by comprising a predetermined film having crystal defects formed in an anode portion or a cathode portion.
However, the invention disclosed in Patent Document 1 has a problem that the anode or cathode portion is in contact with a predetermined film, and in such a case, the internal pressure of the contacting portion is not maintained.
Therefore, the invention described in Patent Document 1 can not prevent the forward voltage drop, and there is a difference in the structure and effect from the present invention.
Accordingly, the present specification aims at providing measures to solve the above-mentioned problems.
Specifically, the present specification aims to provide a semiconductor device having a low forward voltage drop and a fast switching characteristic and a soft recovery characteristic.
A semiconductor device according to an embodiment of the present invention includes: an intermediate layer of a first conductivity type; A recombination portion of the first conductivity type formed in the intermediate layer and having a higher concentration than the intermediate layer; And an anode layer of a second conductivity type formed in contact with an upper portion of the intermediate layer; . ≪ / RTI >
The recombination unit may be formed in contact with the anode layer.
The recombination unit may be formed of two or more regions.
And a high-concentration first-conductivity-type cathode layer formed in contact with a lower portion of the intermediate layer.
And an electric field confinement ring of a second conductivity type formed on the intermediate layer.
An anode metal layer formed in contact with an upper portion of the anode layer; And a cathode metal layer formed in contact with a lower portion of the cathode layer.
The first conductivity type may be n-type, and the second conductivity type may be p-type.
Disclosure of the present invention solves the problems of the prior art described above.
Specifically, by making the disclosure of this specification, by forming a high concentration n + -type second region in the low concentration n < + > -type first region, the resistance decreases and the forward voltage drop becomes small by the second region, It is possible to provide a semiconductor device having fast switching characteristics and soft recovery characteristics because the holes quickly recombine and disappear.
1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.
2 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention.
It is noted that the technical terms used herein are used only to describe specific embodiments and are not intended to limit the invention. It is also to be understood that the technical terms used herein are to be interpreted in a sense generally understood by a person skilled in the art to which the present invention belongs, Should not be construed to mean, or be interpreted in an excessively reduced sense. Further, when a technical term used herein is an erroneous technical term that does not accurately express the spirit of the present invention, it should be understood that technical terms that can be understood by a person skilled in the art are replaced. In addition, the general terms used in the present invention should be interpreted according to a predefined or prior context, and should not be construed as being excessively reduced.
Also, the singular forms "as used herein include plural referents unless the context clearly dictates otherwise. In the present application, the term "comprising" or "comprising" or the like should not be construed as necessarily including the various elements or steps described in the specification, Or may be further comprised of additional components or steps.
Furthermore, terms including ordinals such as first, second, etc. used in this specification can be used to describe various elements, but the elements should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.
Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings, wherein like reference numerals refer to like or similar elements throughout the several views, and redundant description thereof will be omitted.
In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. It is to be noted that the accompanying drawings are only for the purpose of facilitating understanding of the present invention, and should not be construed as limiting the scope of the present invention with reference to the accompanying drawings.
The power switch may be implemented by any one of power MOSFET, IGBT, various types of thyristors, and the like. Most of the novel techniques disclosed herein are described on the basis of a fast recovery diode (FRD). However, the various embodiments of the present invention disclosed herein are not limited to FRDs, and may be applied to other types of power switch technologies including power MOSFETs and various types of thyristors, in addition to diodes, for example. Moreover, various embodiments of the present invention are described as including specific p-type and n-type regions. However, it goes without saying that the conductivity types of the various regions disclosed herein can be equally applied to the opposite device.
The n-type and p-type used herein may be defined as a first conductive type or a second conductive type. On the other hand, the first conductive type and the second conductive type mean different conductive types.
In general, '+' means a state doped at a high concentration, and '-' means a state doped at a low concentration.
1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.
Generally, a pn junction diode is formed by bonding a p-type semiconductor and an n-type semiconductor.
When a p-type semiconductor and an n-type semiconductor are bonded, a p-type hole and n-type electrons are combined at the junction region to form a depletion layer.
The depletion layer is an insulating region free of a carrier such as a hole or an electron and interferes with the movement of carriers passing through the junction region.
Therefore, in order for a carrier such as a hole or an electron to pass through the depletion layer, a voltage higher than a certain level is required, and this voltage is called a potential barrier.
A case where a positive voltage is applied to the p-
The holes existing on the side of the p-
Accordingly, the depletion layer, which is formed by the junction of the p-type semiconductor and the n-type semiconductor, is reduced, and the holes and the electrons move smoothly and the current flows.
When a reverse bias is applied due to the reverse flow of the forward bias, the holes existing on the p-
Accordingly, the depletion layer, which is formed by the junction of the p-type semiconductor and the n-type semiconductor, expands, and holes and electrons do not move smoothly and current can not flow.
If a voltage is applied in a reverse direction suddenly while a forward bias is applied, a large reverse current flows instantaneously.
This is because the minority carriers implanted in the pn junction move in the opposite direction, so that current flows until the minority carriers flow out or disappear.
As a result, the reverse current (Ir) flows temporarily. When the minority carriers flow out or disappear, the current does not flow, and the time taken until this is called the reverse recovery time (trr).
Referring to FIG. 1, a semiconductor device according to an embodiment of the present invention includes an n-type
When the voltage is rapidly applied in the reverse direction while the forward bias is applied, the
The
As the
As a result, the reverse current (Ir) is small and thus the switching characteristic is fast and the soft recovery characteristic can be obtained.
In addition, conventionally, when a recombination center is injected through electron beam, neutron irradiation, heavy metal diffusion or the like, such a recombination center functions as a resistor to cause a forward voltage drop. However, the
The
Further, the
In the case where the
However, in this case, a depletion layer may be formed between the
And may include a high-concentration first-conductivity-
The
Accordingly, a depletion layer is formed between the
And an electric
The electric
An
When forward bias is applied, a positive potential is applied to the
When the forward bias is applied, the depletion layer is reduced and the current can flow.
When the forward bias is applied, the
When a reverse bias is applied, a negative potential is applied to the
When the reverse bias is applied, the depletion layer expands and current can not flow.
However, when switching from the forward bias to the reverse bias, the reverse current Ir flows due to the remaining holes.
When a reverse bias is applied, the
2 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention.
Referring to FIG. 2, a semiconductor device according to an embodiment of the present invention includes an n-type
Since the
While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It falls within the scope of the invention.
10: intermediate layer 11: electric field limiting ring
20: recombination unit 30: anode layer
40: cathode layer 50: cathode metal layer
60: anode metal layer
Claims (7)
A recombination portion of the first conductivity type formed in the intermediate layer and having a higher concentration than the intermediate layer; And
An anode layer of a second conductivity type formed in contact with an upper portion of the intermediate layer; ≪ / RTI >
And the recombination unit is formed in contact with the anode layer.
Wherein the recombination unit is formed of two or more regions.
And a high-concentration first-conductivity-type cathode layer formed in contact with a lower portion of the intermediate layer.
An anode metal layer formed in contact with an upper portion of the anode layer; And
And a cathode metal layer formed in contact with a lower portion of the cathode layer.
And an electric field confinement ring of a second conductivity type formed on the intermediate layer.
Wherein the first conductivity type is an n-type and the second conductivity type is a p-type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020120143969A KR20140075532A (en) | 2012-12-11 | 2012-12-11 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020120143969A KR20140075532A (en) | 2012-12-11 | 2012-12-11 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20140075532A true KR20140075532A (en) | 2014-06-19 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020120143969A KR20140075532A (en) | 2012-12-11 | 2012-12-11 | Semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106206752A (en) * | 2015-02-18 | 2016-12-07 | 三垦电气株式会社 | Semiconductor device |
| KR20200062580A (en) | 2018-11-27 | 2020-06-04 | 한양대학교 산학협력단 | Two-terminal vertical one-transistor dynamic random access memory |
-
2012
- 2012-12-11 KR KR1020120143969A patent/KR20140075532A/en active Search and Examination
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106206752A (en) * | 2015-02-18 | 2016-12-07 | 三垦电气株式会社 | Semiconductor device |
| CN106206752B (en) * | 2015-02-18 | 2020-02-07 | 三垦电气株式会社 | Semiconductor device with a plurality of semiconductor chips |
| KR20200062580A (en) | 2018-11-27 | 2020-06-04 | 한양대학교 산학협력단 | Two-terminal vertical one-transistor dynamic random access memory |
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