KR20140064310A - Display device and method of manufacturing the same - Google Patents

Display device and method of manufacturing the same Download PDF

Info

Publication number
KR20140064310A
KR20140064310A KR1020120131504A KR20120131504A KR20140064310A KR 20140064310 A KR20140064310 A KR 20140064310A KR 1020120131504 A KR1020120131504 A KR 1020120131504A KR 20120131504 A KR20120131504 A KR 20120131504A KR 20140064310 A KR20140064310 A KR 20140064310A
Authority
KR
South Korea
Prior art keywords
electrode
capacitor electrode
capacitor
active layer
active
Prior art date
Application number
KR1020120131504A
Other languages
Korean (ko)
Other versions
KR102050401B1 (en
Inventor
강해윤
최희동
고삼민
Original Assignee
엘지디스플레이 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 엘지디스플레이 주식회사 filed Critical 엘지디스플레이 주식회사
Priority to KR1020120131504A priority Critical patent/KR102050401B1/en
Publication of KR20140064310A publication Critical patent/KR20140064310A/en
Application granted granted Critical
Publication of KR102050401B1 publication Critical patent/KR102050401B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

The thin film transistor includes a gate electrode, an active layer, a first active wiring connected to one end of the active layer, a second active wiring connected to the other end of the active layer, A source electrode connected to the first active wiring, and a drain electrode connected to the second active wiring are formed in the first capacitor electrode, the first capacitor electrode, the second capacitor electrode, the third capacitor electrode, 4 capacitor electrodes are formed on the active layer, and the active layer and the second capacitor electrode are formed on the same layer, and a method of manufacturing the same.
According to the present invention, since the display device includes three capacitors, the capacitance capacity is increased.

Description

DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME

The present invention relates to a display device, and more particularly, to a capacitor structure of a display device.

Display devices such as a liquid crystal display device and an organic light emitting device include a thin film transistor and a capacitor as essential components.

Hereinafter, a conventional display device will be described with reference to the drawings.

1 is a schematic cross-sectional view of a conventional display device.

As can be seen from Fig. 1, the conventional display device comprises a thin film transistor (TFT) region and a capacitor region.

A gate electrode 21, a gate insulating film 30, an active layer 40, an etch stopper 50, a source electrode 62, a drain electrode 64, and a protective film 70 are formed in the thin film transistor region have.

The gate electrode 21 is formed on the substrate 10 and the gate insulating film 30 is formed on the gate electrode 21. The gate insulating film 30 is formed on the entire surface of the substrate, and therefore, the gate insulating film 30 is formed not only in the thin film transistor region but also in the capacitor region.

The active layer 40 is formed on the gate insulating film 30 and the etch stopper 50 is formed on the active layer 40. The etch stopper 50 serves to prevent the active layer 40 from being etched during the patterning process of the source electrode 62 and the drain electrode 64.

The source electrode 62 and the drain electrode 64 are formed on the etch stopper 50 and the protective film 70 is formed on the source electrode 62 and the drain electrode 64. The source electrode 62 and the drain electrode 64 are formed to face each other and are connected to one end and the other end of the active layer 40, respectively. The passivation layer 70 is formed on the entire surface of the substrate, and thus the passivation layer 70 is formed not only in the thin film transistor region but also in the capacitor region.

In the capacitor region, a first capacitor electrode 22, a gate insulating film 30, a second capacitor electrode 66, a protective film 70, and a third capacitor electrode 80 are formed.

The first capacitor electrode 22 is formed on the substrate 10 and the gate insulating film 30 is formed on the first capacitor electrode 22. The first capacitor electrode 22 is formed on the same layer as the gate electrode 21.

The second capacitor electrode 66 is formed on the gate insulating film 30 and the protective film 70 is formed on the second capacitor electrode 66. The second capacitor electrode 66 is connected to the drain electrode 64.

The third capacitor electrode 80 is formed on the passivation layer 70.

The conventional display device includes one capacitor by the combination of the first capacitor electrode 22, the gate insulating film 30 and the second capacitor electrode 66, and the second capacitor electrode 66, the protective film 70 ) And the third capacitor electrode 80, and includes a total of two capacitors.

However, according to recent technological developments, capacitance of a larger capacitance is required.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a display device including three capacitors and a method of manufacturing the same.

In order to achieve the above object, the present invention provides a semiconductor device including a thin film transistor region and a capacitor region, wherein the thin film transistor region includes a gate electrode, an active layer, a first active wiring connected to one end of the active layer, A source electrode connected to the first active wiring, and a drain electrode connected to the second active wiring are formed on the first active electrode, the first capacitor electrode and the second capacitor electrode overlapping each other in the capacitor region, A third capacitor electrode, and a fourth capacitor electrode are formed on the active layer, and the active layer and the second capacitor electrode are formed on the same layer.

The present invention also provides a method of manufacturing a display device including a thin film transistor region and a capacitor region, the method comprising: patterning a gate electrode and a first capacitor electrode on a substrate; Forming a gate insulating film on the gate electrode and the first capacitor electrode; Forming an active layer pattern on the gate insulating film; Forming a pattern of an etch stopper on the active layer and carrying out a conducting process for the active layer using the etch stopper as a mask to form a first active wiring in a region of the active layer not covered by the etch stopper, A second active wiring, and a second capacitor electrode; Patterning an interlayer insulating film on the first active wiring, the second active wiring, and the second capacitor electrode; Forming a source electrode connected to the first active wiring on the interlayer insulating film, a drain electrode connected to the second active wiring, and a third capacitor electrode connected to the first capacitor electrode; Forming a protective film on the source electrode, the drain electrode, and the third capacitor electrode; And forming a pattern of a fourth capacitor electrode on the protective film, wherein the step of patterning the active layer on the gate insulating film includes patterning the active layer in the thin film transistor region and the capacitor region, Wherein the step of patterning the etch stopper on the active layer comprises patterning the etch stopper on the active layer of the thin film transistor region and patterning the etch stopper on the active layer of the capacitor region The display device is manufactured by a method comprising the steps of:

The present invention also provides a method of manufacturing a display device including a thin film transistor region and a capacitor region, the method comprising: patterning an active layer on a substrate; Forming a first active wiring, a second active wiring, and a second capacitor electrode in a region of the non-masked active layer by covering a central region of the active layer and performing a conducting process on the active layer, A step of forming an active layer pattern in which the obscured active layer region remains without being converted into a conductor; Patterning a gate insulating film on the active layer pattern and the second capacitor electrode and patterning the gate electrode and the first capacitor electrode on the gate insulating film; Patterning an interlayer insulating film on the gate electrode and the first capacitor electrode; Forming a source electrode connected to the first active wiring on the interlayer insulating film, a drain electrode connected to the second active wiring, and a third capacitor electrode connected to the second capacitor electrode; Forming a protective film on the source electrode, the drain electrode, and the third capacitor electrode; And forming a pattern of a fourth capacitor electrode on the protective film, wherein patterning the active layer on the substrate includes patterning the active layer in each of the thin film transistor region and the capacitor region, Wherein the step of covering the central region of the active layer covers the active layer of the thin film transistor region and does not cover the active layer of the capacitor region.

According to the present invention as described above, the following effects can be obtained.

According to the present invention, since the display device includes three capacitors, the capacitance capacity is increased.

1 is a schematic cross-sectional view of a conventional display device.
2 is a schematic cross-sectional view of a display device according to an embodiment of the present invention.
3 is a schematic cross-sectional view of a display device according to another embodiment of the present invention.
4 is a schematic cross-sectional view of a display device according to another embodiment of the present invention.
5A to 5E are schematic sectional views of a manufacturing process of a display device according to an embodiment of the present invention.
6A to 6E are schematic sectional views of a manufacturing process of a display device according to another embodiment of the present invention.
7A to 7E are schematic sectional views of a manufacturing process of a display device according to another embodiment of the present invention.
8A to 8F are schematic sectional views of a manufacturing process of a display device according to another embodiment of the present invention.

The term "on " as used herein is meant to encompass not only when a configuration is formed directly on top of another configuration, but also to the extent that a third configuration is interposed between these configurations.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

2 is a schematic cross-sectional view of a display device according to an embodiment of the present invention, which relates to a bottom gate structure in which a gate electrode is located below an active layer.

As can be seen from FIG. 2, the display device according to an embodiment of the present invention includes a thin film transistor (TFT) region and a capacitor region.

Although not shown, a display device according to an exemplary embodiment of the present invention further includes a pixel region in addition to the thin film transistor (TFT) region and the capacitor region. The pixel region is appropriately changed depending on the type of display device. For example, when the display device according to an embodiment of the present invention is an organic light emitting device, the pixel region includes a pair of electrodes and an organic light emitting layer formed between the pair of electrodes. When the display device according to an embodiment of the present invention is a liquid crystal display device, a pixel electrode and a common electrode for generating an electric field for liquid crystal driving may be formed in the pixel region. Since a characteristic of the present invention resides in a thin film transistor (TFT) region and a capacitor region, a separate description of the pixel region will be omitted, and the pixel region can be changed into various forms have. The pixel region will not be described in detail with respect to the display device according to various embodiments of the present invention described below as well as the display device according to the embodiment of the present invention shown in FIG.

2, a gate electrode 210 and a first capacitor electrode 220 are formed on a substrate 100. A gate insulating film 300 is formed on the gate electrode 210 and the first capacitor electrode 220, Respectively.

Although glass is mainly used for the substrate 100, transparent plastic such as polyimide which can be bent or rolled can be used. When polyimide is used as the material of the substrate 100, polyimide excellent in heat resistance that can withstand high temperatures can be used, considering that a high temperature deposition process is performed on the substrate 100.

The gate electrode 210 is formed in a thin film transistor region (hereinafter referred to as a TFT region), and the first capacitor electrode 220 is formed in a capacitor region. The gate electrode 210 and the first capacitor electrode 220 are isolated from each other. The gate electrode 210 and the first capacitor electrode 220 may be formed of the same material in the same layer in the same process. The gate electrode 210 and the first capacitor electrode 220 may be formed of a metal such as molybdenum, aluminum, chromium, gold, titanium, nickel, neodymium, , Copper (Cu), or an alloy thereof, and may be a single layer of the metal or alloy, or a multilayer of two or more layers.

The gate insulating layer 300 is formed on the entire surface of the substrate including the gate electrode 210 and the first capacitor electrode 220. The gate insulating layer 300 may be made of an inorganic insulating material such as silicon oxide or silicon nitride. However, the gate insulating layer 300 may be formed of an organic insulating material such as photo acryl or benzocyclobutene (BCB) have.

An active layer 400, a first active wiring 410, a second active wiring 420, and a second capacitor electrode 430 are formed on the gate insulating layer 300.

The active layer 400, the first active wiring 410 and the second active wiring 420 are formed in the TFT region and the second capacitor electrode 430 is formed in the capacitor region.

The active layer 400 is formed to overlap with the gate electrode 210. The first active wiring 410 is connected to one end of the active layer 400. The second active wiring 420, Is connected to the other end of the active layer 400. The second capacitor electrode 430 is isolated from the active layer 400, the first active wiring 410, and the second active wiring 420 in an insulated state. The second capacitor electrode 430 may overlap the first capacitor electrode 220 and may be formed by a combination of the first capacitor electrode 220, the gate insulating layer 300, and the second capacitor electrode 430 One capacitor (first capacitor) is constituted.

The active layer 400 may be made of an oxide semiconductor such as In-Ga-Zn-O (IGZO), but is not limited thereto. The first active wiring 410 and the second active wiring 420 may be formed through a conductive process for the oxide semiconductor constituting the active layer 400, as will be seen from the manufacturing process described later. The first active wiring 410 and the second active wiring 420 are formed in the same layer as the active layer 400 and the first active wiring 410 and the second active wiring 420 are formed in the same layer as the active layer 400, The active layers 400 are formed so as not to overlap each other.

The second capacitor electrode 430 may be formed through a conducting process for an oxide semiconductor constituting the active layer 400 like the first active wiring 410 and the second active wiring 420. Accordingly, both the active layer 400, the first active wiring 410, the second active wiring 420, and the second capacitor electrode 430 may be formed on the same layer.

An etch stopper 500 is formed on the active layer 400.

The etch stopper 500 is formed in the TFT region. The etch stopper 500 protects the active layer 400 and serves as a mask for defining a region that is not made conductive (that is, the active layer 400) in the conducting process for the oxide semiconductor. This can be easily understood with reference to a manufacturing process described later. The etch stopper 500 may be made of an inorganic insulating material such as silicon oxide or silicon nitride. However, the etch stopper 500 may be made of an organic insulating material such as photo acryl or benzocyclobutene (BCB) have.

An interlayer insulating film 600 is formed on the etch stopper 500.

The interlayer insulating layer 600 is formed on the entire surface of the substrate including the etch stopper 500, the first active wiring 410, the second active wiring 420, and the second capacitor electrode 430. The interlayer insulating layer 600 includes a first contact hole CH1, a second contact hole CH2, a third contact hole CH3, and a fourth contact hole CH4.

The first contact hole CH1 and the second contact hole CH2 are formed in the TFT region. Specifically, the first contact hole CH1 exposes a predetermined region of the first active wiring 410 , And the second contact hole (CH 2) exposes a predetermined region of the second active wiring (420).

The third contact hole CH3 and the fourth contact hole CH4 are formed in the capacitor region. Specifically, the third contact hole CH3 exposes a predetermined region of the first capacitor electrode 220 , And the fourth contact hole (CH4) exposes a predetermined region of the second capacitor electrode (430). The third contact hole CH3 is formed not only in the interlayer insulating layer 600 but also in the gate insulating layer 300 to expose a predetermined region of the first capacitor electrode 220. [

The interlayer insulating layer 600 may be formed of an inorganic insulating material such as silicon oxide or silicon nitride but may be formed of an organic insulating material such as photo acryl or benzocyclobutene have.

A source electrode 710, a drain electrode 720, a third capacitor electrode 730, and a connection electrode 740 are formed on the interlayer insulating layer 600.

The source electrode 710 and the drain electrode 720 are formed in the TFT region and the third capacitor electrode 730 and the connection electrode 740 are formed in the capacitor region.

The source electrode 710 is connected to the first active wiring 410 through the first contact hole CH1 and the drain electrode 720 is connected to the second active wiring 410 through the second contact hole CH2. And is connected to the wiring 420.

The third capacitor electrode 730 is connected to the first capacitor electrode 220 through the third contact hole CH3 and the connection electrode 740 is connected to the third contact hole CH4 through the fourth contact hole CH4. 2 capacitor electrode 420. In this case,

The drain electrode 720 and the third capacitor electrode 730 are connected to each other and the third capacitor electrode 730 is connected to the source electrode 710 and the drain electrode 720, And the connection electrode 740 are isolated from each other.

The third capacitor electrode 730 is formed to overlap with the second capacitor electrode 430 and is formed by a combination of the second capacitor electrode 430, the interlayer insulating film 600, and the third capacitor electrode 730 And the other capacitor (second capacitor) is constituted.

The source electrode 710, the drain electrode 720, the third capacitor electrode 730, and the connection electrode 740 may be formed of the same material in the same layer in the same process. The source electrode 710, the drain electrode 720, the third capacitor electrode 730 and the connection electrode 740 may be formed of a metal such as molybdenum (Mo), aluminum (Al), chromium (Cr) (Ni), neodymium (Nd), copper (Cu), or alloys thereof, and may be a single layer of the metal or alloy, or multiple layers of two or more layers.

The passivation layer 800 is formed on the source electrode 710, the drain electrode 720, the third capacitor electrode 730, and the connection electrode 740.

The protective film 800 is formed on the entire surface of the substrate with a fifth contact hole CH5. The fifth contact hole CH 5 is formed in the capacitor region. Specifically, the fifth contact hole CH 5 exposes a predetermined region of the connection electrode 740.

The passivation layer 800 may be formed of an inorganic insulating material such as silicon oxide or silicon nitride but may be formed of an organic insulating material such as photo acryl or benzocyclobutene (BCB) .

A fourth capacitor electrode 900 is formed on the passivation layer 800.

The fourth capacitor electrode 900 is formed in the capacitor region. In particular, the fourth capacitor electrode 900 is connected to the connection electrode 740 through the fifth contact hole CH5. That is, the fourth capacitor electrode 900 is electrically connected to the second capacitor electrode 430 through the connection electrode 740.

The fourth capacitor electrode 900 may be formed to overlap the third capacitor electrode 730 and may be formed by a combination of the third capacitor electrode 730, the protective film 800 and the fourth capacitor electrode 900 And another capacitor (third capacitor) is constituted.

The fourth capacitor electrode 900 may be made of a transparent metal oxide such as ITO. However, the fourth capacitor electrode 900 may not necessarily be formed of an opaque metal. The fourth capacitor electrode 900 may be formed of the same material in the same layer in the same process as the pixel electrode formed in the pixel region (not shown).

The display device according to an embodiment of the present invention includes three capacitors in total. That is, one capacitor (first capacitor) is formed by the combination of the first capacitor electrode 220, the gate insulating film 300 and the second capacitor electrode 430, and the second capacitor electrode 430, the interlayer insulating film (Second capacitor) is formed by the combination of the first capacitor electrode 600 and the third capacitor electrode 730 and the combination of the third capacitor electrode 730, the protective film 800 and the fourth capacitor electrode 900 Another capacitor (a third capacitor) is constituted. As described above, according to the embodiment of the present invention, the total capacitance of the capacitors is increased by including three capacitors.

According to an embodiment of the present invention, the first capacitor electrode 220 is electrically connected to the third capacitor electrode 730, and the second capacitor electrode 430 is electrically connected to the fourth capacitor electrode 900 So that it is advantageous that a total of three capacitors can be realized by only voltage fluctuation of two wiring lines.

3 is a schematic cross-sectional view of a display device according to another embodiment of the present invention, which relates to a top gate structure in which a gate electrode is located on an active layer. The same reference numerals are given to the same components as those of the above-described embodiment, and repetitive description of the same items in the materials, structures and the like will be omitted.

As shown in FIG. 3, a buffer layer 150 is formed on the substrate 100.

The buffer layer 150 is formed on the entire surface of the substrate 100. The buffer layer 150 serves to prevent diffusion of a substance contained on the substrate 100 into the active layer during a high temperature deposition process. In addition, the buffer layer 150 may prevent external moisture or moisture from penetrating into the organic light emitting device when the display device according to the present invention is an organic light emitting device. The buffer layer 150 may be formed of silicon oxide or silicon nitride. The buffer layer 150 may be omitted in some cases.

An active layer 400, a first active wiring 410, a second active wiring 420, and a second capacitor electrode 430 are formed on the buffer layer 150.

The active layer 400, the first active wiring 410 and the second active wiring 420 are formed in the TFT region and the second capacitor electrode 430 is formed in the capacitor region.

The first active wiring 410 is connected to one end of the active layer 400. The second active wiring 420 is connected to the other end of the active layer 400. The second capacitor electrode 430 are isolated from the active layer 400, the first active wiring 410, and the second active wiring 420 in an insulated state.

The first active wiring 410, the second active wiring 420 and the second capacitor electrode 430 may be formed through a conductive process for the oxide semiconductor constituting the active layer 400. Accordingly, both the active layer 400, the first active wiring 410, the second active wiring 420, and the second capacitor electrode 430 may be formed on the same layer.

A gate insulating layer 300 is formed on the active layer 400 and the second capacitor electrode 430. The gate insulating layer 300 is not formed on the entire surface of the substrate but is patterned on the active layer 400 and the second capacitor electrode 430.

A gate electrode 210 and a first capacitor electrode 220 are formed on the gate insulating layer 300.

The gate electrode 210 is formed in a TFT region, and the first capacitor electrode 220 is formed in a capacitor region. The gate electrode 210 and the first capacitor electrode 220 are isolated from each other. The gate electrode 210 and the first capacitor electrode 220 may be formed in the same pattern as the gate insulating layer 300. The first capacitor electrode 220 overlaps with the second capacitor electrode 430 and is formed by a combination of the first capacitor electrode 220, the gate insulating layer 300 and the second capacitor electrode 430 One capacitor (first capacitor) is constituted.

An interlayer insulating layer 600 is formed on the gate electrode 210 and the first capacitor electrode 220.

The interlayer insulating layer 600 is formed on the entire surface of the substrate including the first contact hole CH1, the second contact hole CH2, and the third contact hole CH3.

The first contact hole CH1 and the second contact hole CH2 are formed in the TFT region. Specifically, the first contact hole CH1 exposes a predetermined region of the first active wiring 410 , And the second contact hole (CH 2) exposes a predetermined region of the second active wiring (420).

The third contact hole CH3 is formed in the capacitor region. Specifically, the third contact hole CH3 exposes a predetermined region of the second capacitor electrode 430. [

A source electrode 710, a drain electrode 720, and a third capacitor electrode 730 are formed on the interlayer insulating layer 600.

The source electrode 710 and the drain electrode 720 are formed in the TFT region and the third capacitor electrode 730 is formed in the capacitor region.

The source electrode 710 is connected to the first active wiring 410 through the first contact hole CH1 and the drain electrode 720 is connected to the second active wiring 410 through the second contact hole CH2. And is connected to the wiring 420.

The third capacitor electrode 730 is connected to the second capacitor electrode 420 through the third contact hole CH3.

The source electrode 710 and the drain electrode 720 are isolated from each other and the drain electrode 720 and the third capacitor electrode 730 are connected to each other.

The third capacitor electrode 730 is formed to overlap with the first capacitor electrode 220 and is formed by a combination of the first capacitor electrode 220, the interlayer insulating film 600, and the third capacitor electrode 730 And the other capacitor (second capacitor) is constituted.

The source electrode 710, the drain electrode 720, the third capacitor electrode 730, and the connection electrode 740 may be formed of the same material in the same layer in the same process.

A protective film 800 is formed on the source electrode 710, the drain electrode 720, and the third capacitor electrode 730.

The protective film 800 is formed on the entire surface of the substrate with a fifth contact hole CH5. The fifth contact hole CH5 is formed in the capacitor region. Specifically, the fifth contact hole CH5 exposes a predetermined region of the first capacitor electrode 220. In addition, The fifth contact hole CH 5 is formed not only in the protective film 800 but also in the interlayer insulating film 600 to expose a predetermined region of the first capacitor electrode 220.

A fourth capacitor electrode 900 is formed on the passivation layer 800.

The fourth capacitor electrode 900 is formed in the capacitor region. In particular, the fourth capacitor electrode 900 is electrically connected to the first capacitor electrode 220 through the fifth contact hole CH5.

The fourth capacitor electrode 900 may be formed to overlap the third capacitor electrode 730 and may be formed by a combination of the third capacitor electrode 730, the protective film 800 and the fourth capacitor electrode 900 And another capacitor (third capacitor) is constituted.

The display device according to another embodiment of the present invention includes three capacitors in total. The first capacitor electrode 220 is electrically connected to the fourth capacitor electrode 900, and the second capacitor electrode Since the third capacitor electrode 430 is electrically connected to the third capacitor electrode 730, it is possible to realize a total of three capacitors by only changing the voltage of the two wirings.

4 is a schematic cross-sectional view of a display device according to another embodiment of the present invention, which is the same as the above-described display device according to Fig. 3 except that the configuration of the gate insulating film is changed. Therefore, the same reference numerals are assigned to the same components, and only the different components will be described below.

As shown in FIG. 4, a gate insulating film is formed on the active layer 400 and the second capacitor electrode 430.

The gate insulating layer formed on the active layer 400 includes a first gate insulating layer 310 and a second gate insulating layer 320 and a gate insulating layer formed on the second capacitor electrode 430 includes a second gate And an insulating film 320. The first gate insulating layer 310 and the second gate insulating layer 320 may be formed of the same material or different materials.

4, a double-layer gate insulating film is formed on the active layer 400 while a single-layer gate insulating film is formed on the second capacitor electrode 430. As a result, the capacitance increases as compared with the structure according to FIG. .

Further, by configuring the gate insulating film formed on the active layer 400 and the gate insulating film formed on the second capacitor electrode 430 different from each other in this way, the gate electrode 210 of the TFT region can be patterned more precisely This can be easily understood by referring to the manufacturing process described later.

Figs. 5A to 5E are schematic sectional views of a manufacturing process of a display device according to an embodiment of the present invention, which relates to the manufacturing process of the display device according to Fig. 2 described above. Hereinafter, repetitive description of the repetitive portions in the materials, structures and the like of each constitution will be omitted.

5A, a gate electrode 210 and a first capacitor electrode 220 are pattern-formed on a substrate 100, and a gate electrode 210 and a gate electrode 220 are formed on the gate electrode 210 and the first capacitor electrode 220, An insulating film 300 is formed.

The gate electrode 210 and the first capacitor electrode 220 are formed by depositing an electrode layer on the substrate 100 by sputtering and forming a photoresist pattern on the electrode layer and then performing an exposure, A patterning process can be performed using a so-called mask process. Pattern formation for each structure described below can also be performed using a mask process including the above-described exposure, development and etching processes.

The gate insulating layer 300 may be formed on the entire surface of the substrate including the gate electrode 210 and the first capacitor electrode 220 by PECVD.

5B, the active layer 400 is patterned on the gate insulating layer 300. Next, as shown in FIG.

The active layer 400 is formed in the TFT region and the capacitor region, respectively. The active layer 400 of the TFT region is patterned to overlap with the gate electrode 210 and the active layer 400 of the capacitor region is patterned to overlap with the first capacitor electrode 220.

The active layer 400 may be formed by depositing an amorphous oxide semiconductor such as a-IGZO on the gate insulating layer 300 using sputtering or MOCVD (Metal Organic Chemical Vapor Deposition) The amorphous oxide semiconductor may be crystallized by performing a high temperature annealing process at about 650 ° C. or higher through a rapid thermal process (RTP), and the crystallized oxide semiconductor may be patterned by a mask process.

5C, an etch stopper 500 is patterned on the active layer 400 and a conducting process is performed on the active layer 400 using the etch stopper 500 as a mask. Next, as shown in FIG. 5C, do.

The etch stopper 500 is formed on the active layer 400 of the TFT region and is not formed on the active layer 400 of the capacitor region.

The area of the active layer 400 not covered by the etch stopper 500 is made conductive and the first active wiring 410, the second active wiring 420, An electrode 430 is formed. Then, the area of the active layer 400 covered with the etch stopper 500 remains unconductored, and the final active layer 400 pattern is completed. That is, the pattern of the final active layer 400 is formed in the same manner as the etch stopper 500 pattern. Here, the fact that the pattern of the final active layer 400 is the same as the pattern of the etch stopper 500 should be interpreted to include not only the case where the patterns are completely identical but also the case where an anomaly occurs in the process progress.

The etch stopper 500 is formed on the center side of the active layer 400 of the TFT region so that the first active wiring 410 is formed in one end region of the pattern of the final active layer 400, And the second active wiring 420 is formed in the other end region of the pattern of the final active layer 400. In addition, the active layer 400 of the capacitor region is all made conductive to form the second capacitor electrode 430.

The conducting process may be a process of performing a plasma process on the oxide semiconductor. That is, when plasma processing is performed on an oxide semiconductor such as IGZO, the characteristics of the oxide semiconductor are changed to be a conductor.

The plasma treatment for the oxide semiconductor may be performed by plasma etching or enhanced capacitively coupled plasma (enhanced capacitively coupled plasma) treatment. The plasma etching or enhanced capacitively coupled plasma (enhanced capacitively coupled plasma) processing can reduce the equipment development cost because the conventional dry etching equipment can be used.

As a specific example, the plasma etching may be performed for 5 to 180 seconds at a power of 5 K to 25 K, a pressure of 200 to 350 mTorr, and an O 2 atmosphere, but is not limited thereto. The Enhanced Capacitively Coupled Plasma can be performed at a power of 2K to 13K (source) and 0K to 13K (Bias), at a pressure of 20 to 150 mTorr and in an O 2 atmosphere for 5 to 150 seconds, But is not limited thereto.

5D, the interlayer insulating layer 600 is patterned on the etch stopper 500, the first active wiring 410, the second active wiring 420, and the second capacitor electrode 430, A source electrode 710, a drain electrode 720, a third capacitor electrode 730, and a connection electrode 740 are formed in a pattern on the interlayer insulating layer 600.

The interlayer insulating layer 600 is patterned to have a first contact hole CH1, a second contact hole CH2, a third contact hole CH3, and a fourth contact hole CH4. The first contact hole CH1 exposes a predetermined region of the first active wiring 410 and the second contact hole CH2 exposes a predetermined region of the second active wiring 420, 3 contact hole CH3 exposes a predetermined region of the first capacitor electrode 220 and the fourth contact hole CH4 exposes a predetermined region of the second capacitor electrode 430. [ The third contact hole CH3 is formed not only in the interlayer insulating layer 600 but also in the gate insulating layer 300 to expose a predetermined region of the first capacitor electrode 220. [

The source electrode 710 is patterned to be connected to the first active wiring 410 through the first contact hole CH1 and the drain electrode 720 is formed through the second contact hole CH2 And the third capacitor electrode 730 is pattern-formed to be connected to the first capacitor electrode 220 through the third contact hole CH3, The electrode 740 is patterned to be connected to the second capacitor electrode 420 through the fourth contact hole CH4.

The source electrode 710 and the drain electrode 720 are patterned so as to be spaced apart from each other and patterned to connect the drain electrode 720 and the third capacitor electrode 730 to each other, The electrode 730 and the connection electrode 740 are patterned so as to be isolated from each other.

5E, a protective film 800 is pattern-formed on the source electrode 710, the drain electrode 720, the third capacitor electrode 730, and the connecting electrode 740, 800, the fourth capacitor electrode 900 is pattern-formed.

The passivation layer 800 is patterned to have a fifth contact hole CH5. The fifth contact hole CH 5 exposes a predetermined region of the connection electrode 740.

The fourth capacitor electrode 900 is patterned to be connected to the connection electrode 740 through the fifth contact hole CH5.

6A to 6E are schematic sectional views of a manufacturing process of a display device according to another embodiment of the present invention, which relates to a manufacturing process of the display device according to the aforementioned FIG. Hereinafter, a duplicate description of the same configuration as the above embodiment will be omitted.

6A, a buffer layer 150 is formed on a substrate 100, and an active layer 400 is formed on the buffer layer 150 by patterning.

The buffer layer 150 may be formed on the entire surface of the substrate 100 by PECVD.

The active layer 400 forms a pattern in the TFT region and the capacitor region, respectively.

6B, a photoresist pattern PR is formed on the active layer 400 and a conducting process for the active layer 400 is performed using the photoresist pattern PR as a mask .

The photoresist pattern PR is formed on the active layer 400 of the TFT region and is not formed on the active layer 400 of the capacitor region.

The area of the active layer 400 not covered by the photoresist pattern PR is made conductive to form the first active wiring 410, the second active wiring 420, and the second A capacitor electrode 430 is formed. Then, the region of the active layer 400 covered with the photoresist pattern PR remains without being converted into a conductor, and the final active layer 400 pattern is completed. That is, the pattern of the final active layer 400 is formed in the same manner as the photoresist pattern PR.

The photoresist pattern PR is formed on the center side of the active layer 400 of the TFT region so that the first active wiring 410 is formed in one end region of the pattern of the final active layer 400, A second active wiring 420 is formed in the other end region of the pattern of the final active layer 400. In addition, the active layer 400 of the capacitor region is all made conductive to form the second capacitor electrode 430.

6C, the photoresist pattern PR is removed, the gate insulating layer 300 is pattern-formed on the pattern of the final active layer 400 and the second capacitor electrode 430, A gate electrode 210 and a first capacitor electrode 220 are pattern-formed on the insulating film 300.

The gate insulating layer 300 is not formed on the entire surface of the substrate but is patterned on the final active layer 400 pattern and the second capacitor electrode 430.

The gate electrode 210 is patterned on the gate insulating layer 300 of the TFT region and the first capacitor electrode 220 is patterned on the gate insulating layer 300 of the capacitor region. Accordingly, the first capacitor electrode 220 is formed to overlap with the second capacitor electrode 430.

6D, an interlayer insulating layer 600 is pattern-formed on the gate electrode 210 and the first capacitor electrode 220, and a source electrode 710, a drain The electrode 720, and the third capacitor electrode 730 are pattern-formed.

The interlayer insulating layer 600 is formed to include a first contact hole CH1, a second contact hole CH2, and a third contact hole CH3. The first contact hole CH1 exposes a predetermined region of the first active wiring 410 and the second contact hole CH2 exposes a predetermined region of the second active wiring 420, 3 contact hole CH3 exposes a predetermined region of the second capacitor electrode 430. [

The source electrode 710 is patterned to be connected to the first active wiring 410 through the first contact hole CH1 and the drain electrode 720 is formed through the second contact hole CH2 And the third capacitor electrode 730 is pattern-formed to be connected to the second capacitor electrode 420 through the third contact hole CH3.

The source electrode 710 and the drain electrode 720 are patterned so as to be spaced apart from each other and patterned to connect the drain electrode 720 and the third capacitor electrode 730 to each other.

6E, a protective film 800 is patterned on the source electrode 710, the drain electrode 720, and the third capacitor electrode 730, and a protective film 800 is formed on the protective film 800, The capacitor electrode 900 is pattern-formed.

The passivation layer 800 is patterned to have a fifth contact hole CH5. The fifth contact hole CH 5 exposes a predetermined region of the first capacitor electrode 220. The fifth contact hole CH 5 is formed not only in the protective film 800 but also in the interlayer insulating film 600 to expose a predetermined region of the first capacitor electrode 220.

The fourth capacitor electrode 900 is patterned to be connected to the first capacitor electrode 220 through the fifth contact hole CH5.

Figs. 7A to 7E are schematic sectional views of a manufacturing process of a display device according to another embodiment of the present invention, which relates to the manufacturing process of the display device according to Fig. 4 described above. Hereinafter, a duplicate description of the same configuration as the above embodiment will be omitted.

7A, a buffer layer 150 is formed on a substrate 100, and an active layer 400 is formed on the buffer layer 150 by patterning.

7B, a first gate insulating layer 310 is pattern-formed on the active layer 400 and a conductive layer 400 is formed on the active layer 400 using the first gate insulating layer 310 as a mask. .

The first gate insulating layer 310 is formed on the active layer 400 of the TFT region and is not formed on the active layer 400 of the capacitor region.

The area of the active layer 400 not covered by the first gate insulating layer 310 is made conductive to form the first active wiring 410, the second active wiring 420, 2 capacitor electrode 430 are formed. The region of the active layer 400 covered by the first gate insulating layer 310 remains without being converted into a conductor, and the pattern of the final active layer 400 is completed. That is, the pattern of the final active layer 400 is formed in the same manner as the first gate insulating film 310.

The first gate insulating layer 310 is formed on the center side of the active layer 400 of the TFT region so that the first active wiring 410 is formed in one end region of the pattern of the final active layer 400 , And the second active wiring 420 is formed in the other end region of the pattern of the final active layer 400. In addition, the active layer 400 of the capacitor region is all made conductive to form the second capacitor electrode 430.

7C, a second gate insulating layer 320 is pattern-formed on the first gate insulating layer 310 and the second capacitor electrode 430, and a gate insulating layer 320 is formed on the second gate insulating layer 320. Then, The electrode 210 and the first capacitor electrode 220 are pattern-formed.

The second gate insulating layer 320 is patterned on the first gate insulating layer 310 of the TFT region and the second capacitor electrode 430 of the capacitor region.

The gate electrode 210 is patterned on the second gate insulating layer 320 of the TFT region and the first capacitor electrode 220 is patterned on the second gate insulating layer 320 of the capacitor region.

7D, an interlayer insulating layer 600 is pattern-formed on the gate electrode 210 and the first capacitor electrode 220, and a source electrode 710, a drain The electrode 720, and the third capacitor electrode 730 are pattern-formed.

This process is the same as the process of FIG. 6D described above, so a detailed description thereof will be omitted.

7E, a protective film 800 is pattern-formed on the source electrode 710, the drain electrode 720, and the third capacitor electrode 730, and a protective film 800 is formed on the protective film 800, The capacitor electrode 900 is pattern-formed.

This process is the same as the process of FIG. 6E described above, so a detailed description will be omitted.

8A to 8F are schematic sectional views of a manufacturing process of a display device according to another embodiment of the present invention, which relates to a manufacturing process of the display device according to the aforementioned Fig. Hereinafter, a duplicate description of the same configuration as the above embodiment will be omitted.

8A, a buffer layer 150 is formed on a substrate 100, and an active layer 400 is formed on the buffer layer 150 by patterning.

8B, a first gate insulating layer 310 is patterned on the active layer 400, and a conductive layer 400 is formed on the active layer 400 using the first gate insulating layer 310 as a mask. .

The first gate insulating layer 310 is formed on the active layer 400 of the TFT region and is not formed on the active layer 400 of the capacitor region.

The area of the active layer 400 not covered by the first gate insulating layer 310 is made conductive to form the first active wiring 410, the second active wiring 420, 2 capacitor electrode 430 are formed. The region of the active layer 400 covered with the first gate insulating layer 310 remains without being converted into a conductor, and the active layer 400 pattern is completed.

8C, a second gate insulating layer 320 is pattern-formed on the first gate insulating layer 310 and the second capacitor electrode 430, and a gate insulating layer 320 is formed on the second gate insulating layer 320. Then, The electrode 210 and the first capacitor electrode 220 are pattern-formed.

The second gate insulating layer 320 is patterned on the first gate insulating layer 310 of the TFT region and the second capacitor electrode 430 of the capacitor region.

7C of the above-described embodiment, the second gate insulating film 320 and the gate electrode 210 of the TFT region are formed in the same pattern as the first gate insulating film 310 thereunder, The second gate insulating film 320 and the gate electrode 210 are formed in a pattern having a narrower width than the first gate insulating film 310 thereunder. Particularly, the second gate insulating film 320 and the gate electrode 210 in the TFT region are pattern-formed on the center side of the first gate insulating film 310 under the first gate insulating film 310, .

8D, the exposed first gate insulating layer 310 is etched using the gate electrode 210 as a mask, and a conducting process for the active layer 400 is further performed do.

When the exposed first gate insulating layer 310 is etched, the underlying active layer 400 is exposed, and the exposed active layer 400 is further subjected to a conducting process.

When the additional active layer 400 is subjected to an additional conducting process, the active layer 400, which is not covered by the gate electrode 210, 2 active wirings 420 are additionally formed and the region of the active layer 400 covered by the gate electrode 210 remains without being converted into a conductor and the final active layer 400 pattern is completed.

When the final active layer 400 pattern is formed through two conducting processes as shown in FIGS. 8B to 8D, the final active layer 400 pattern is formed through one conducting process as shown in FIG. 7B The alignment between the pattern of the final active layer 400 and the first gate insulating layer 310, the second gate insulating layer 320 and the gate electrode 210 is more precise have.

8E, an interlayer insulating layer 600 is patterned on the gate electrode 210 and the first capacitor electrode 220, and a source electrode 710, a drain The electrode 720, and the third capacitor electrode 730 are pattern-formed.

This process is the same as the process of FIG. 6D described above, so a detailed description thereof will be omitted.

8F, a protective film 800 is patterned on the source electrode 710, the drain electrode 720, and the third capacitor electrode 730, and a protective film 800 is formed on the protective film 800, The capacitor electrode 900 is pattern-formed.

This process is the same as the process of FIG. 6E described above, so a detailed description will be omitted.

Meanwhile, the various embodiments according to the present invention described above relate to a substrate on which a thin film transistor and a capacitor are formed, and the display device according to the present invention may further include an opposing substrate, etc., .

For example, when the display device is a liquid crystal display device, the liquid crystal display device further includes a color filter substrate including a color filter layer thereon, and a liquid crystal layer formed between both substrates. Further, when the display device is an organic light emitting device, it may further include an upper protective substrate.

100: substrate 210: gate electrode
220: first capacitor electrode 300: gate insulating film
310: first gate insulating film 320: second gate insulating film
400: active layer 410, 420: first and second active wirings
430: second capacitor electrode 500: etch stopper
600: interlayer insulating film 710, 720: source electrode, drain electrode
730 third capacitor electrode 740 connection electrode
800: Protection film 900: Fourth capacitor electrode

Claims (13)

A thin film transistor region and a capacitor region,
Wherein the thin film transistor region includes a gate electrode, an active layer, a first active wiring connected to one end of the active layer, a second active wiring connected to the other end of the active layer, a source electrode connected to the first active wiring, A drain electrode connected to the wiring is formed,
A first capacitor electrode, a second capacitor electrode, a third capacitor electrode, and a fourth capacitor electrode overlapping each other are formed in the capacitor region,
Wherein the active layer and the second capacitor electrode are formed on the same layer. The method according to claim 1,
Wherein the second capacitor electrode is made of a material in which an oxide semiconductor is made conductive as in the case of the first active wiring and the second active wiring. The method according to claim 1,
And the third capacitor electrode is connected to the drain electrode. The method according to claim 1,
Wherein the first capacitor electrode is formed below the third capacitor electrode, and the fourth capacitor electrode is formed above the third capacitor electrode. The method according to claim 1,
Wherein one of the first capacitor electrode, the second capacitor electrode, the third capacitor electrode, and the fourth capacitor electrode is connected to each other, and the other pair of capacitor electrodes are connected to each other, Wherein the pair of capacitor electrodes and the other pair of capacitor electrodes are insulated from each other. The method according to claim 1,
The gate electrode and the first capacitor electrode are formed on a substrate,
A gate insulating film is formed on the gate electrode and the first capacitor electrode,
The active layer, the first active wiring, the second active wiring, and the second capacitor electrode are formed on the gate insulating film,
An interlayer insulating film is formed on the first active wiring, the second active wiring, and the second capacitor electrode,
The source electrode, the drain electrode, and the third capacitor electrode are formed on the interlayer insulating film,
A protective film is formed on the source electrode, the drain electrode, and the third capacitor electrode,
And the fourth capacitor electrode is formed on the protective film. The method according to claim 1,
The active layer, the first active wiring, the second active wiring, and the second capacitor electrode are formed on a substrate,
A gate insulating film is formed on the active layer and the second capacitor electrode,
The gate electrode and the first capacitor electrode are formed on the gate insulating film,
An interlayer insulating film is formed on the gate electrode and the first capacitor electrode,
The source electrode, the drain electrode, and the third capacitor electrode are formed on the interlayer insulating film,
A protective film is formed on the source electrode, the drain electrode, and the third capacitor electrode,
And the fourth capacitor electrode is formed on the protective film. 8. The method of claim 7,
Wherein the gate insulating film formed on the active layer comprises a first gate insulating film and a second gate insulating film, and the gate insulating film formed on the second capacitor electrode comprises the second gate insulating film. A manufacturing method of a display device including a thin film transistor region and a capacitor region,
Patterning a gate electrode and a first capacitor electrode on a substrate;
Forming a gate insulating film on the gate electrode and the first capacitor electrode;
Forming an active layer pattern on the gate insulating film;
Forming a pattern of an etch stopper on the active layer and carrying out a conducting process for the active layer using the etch stopper as a mask to form a first active wiring in a region of the active layer not covered by the etch stopper, A second active wiring, and a second capacitor electrode;
Patterning an interlayer insulating film on the first active wiring, the second active wiring, and the second capacitor electrode;
Forming a source electrode connected to the first active wiring on the interlayer insulating film, a drain electrode connected to the second active wiring, and a third capacitor electrode connected to the first capacitor electrode;
Forming a protective film on the source electrode, the drain electrode, and the third capacitor electrode; And
And forming a fourth capacitor electrode pattern on the protective film,
At this time, the step of patterning the active layer on the gate insulating film includes a step of pattern-forming the active layer in each of the thin film transistor region and the capacitor region,
Wherein the step of patterning the etch stopper on the active layer comprises patterning the etch stopper on the active layer of the thin film transistor region and not patterning the etch stopper on the active layer of the capacitor region. ≪ / RTI > 10. The method of claim 9,
Forming a source electrode, a drain electrode, and a third capacitor electrode pattern on the interlayer insulating film, the process further comprising forming a connection electrode connected to the second capacitor electrode,
Wherein the step of patterning the fourth capacitor electrode on the protective film pattern-forms the fourth capacitor electrode to connect the connection electrode. A manufacturing method of a display device including a thin film transistor region and a capacitor region,
Patterning an active layer on a substrate;
Forming a first active wiring, a second active wiring, and a second capacitor electrode in a region of the non-masked active layer by covering a central region of the active layer and performing a conducting process on the active layer, A step of forming an active layer pattern in which the obscured active layer region remains without being converted into a conductor;
Patterning a gate insulating film on the active layer pattern and the second capacitor electrode and patterning the gate electrode and the first capacitor electrode on the gate insulating film;
Patterning an interlayer insulating film on the gate electrode and the first capacitor electrode;
Forming a source electrode connected to the first active wiring on the interlayer insulating film, a drain electrode connected to the second active wiring, and a third capacitor electrode connected to the second capacitor electrode;
Forming a protective film on the source electrode, the drain electrode, and the third capacitor electrode; And
And forming a fourth capacitor electrode pattern on the protective film,
At this time, the step of patterning the active layer on the substrate includes a step of pattern-forming the active layer in each of the thin film transistor region and the capacitor region,
Wherein the step of covering the central region of the active layer covers the active layer of the thin film transistor region and does not cover the active layer of the capacitor region. 12. The method of claim 11,
The step of covering the central region of the active layer comprises a step of forming a first gate insulating film in the central region of the active layer,
Wherein the step of patterning the gate insulating film on the active layer pattern and the second capacitor electrode comprises the step of forming a second gate insulating film. 13. The method of claim 12,
Wherein the second gate insulating film and the gate electrode of the thin film transistor region are formed in a pattern having a narrower width than the first gate insulating film to expose the first gate insulating film,
The gate insulating film is etched using the gate electrode as a mask before the step of patterning the interlayer insulating film, and a conducting process for the active layer pattern exposed by etching the first gate insulating film is performed Wherein the step (c) comprises:
KR1020120131504A 2012-11-20 2012-11-20 Display Device and Method of manufacturing the same KR102050401B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020120131504A KR102050401B1 (en) 2012-11-20 2012-11-20 Display Device and Method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020120131504A KR102050401B1 (en) 2012-11-20 2012-11-20 Display Device and Method of manufacturing the same

Publications (2)

Publication Number Publication Date
KR20140064310A true KR20140064310A (en) 2014-05-28
KR102050401B1 KR102050401B1 (en) 2019-11-29

Family

ID=50891779

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020120131504A KR102050401B1 (en) 2012-11-20 2012-11-20 Display Device and Method of manufacturing the same

Country Status (1)

Country Link
KR (1) KR102050401B1 (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150100566A (en) * 2014-02-24 2015-09-02 엘지디스플레이 주식회사 Thin Film Transistor Substrate And Display Using The Same
KR20160029165A (en) * 2014-09-04 2016-03-15 엘지디스플레이 주식회사 Organic light emitting display panel and fabricating thereof
KR20160094579A (en) * 2015-01-30 2016-08-10 엘지디스플레이 주식회사 Organic light emitting display device and method for manufacturing thereof
JP2018101681A (en) * 2016-12-20 2018-06-28 株式会社Ｊｏｌｅｄ Semiconductor device and display device
CN108957884A (en) * 2018-07-23 2018-12-07 深圳市华星光电技术有限公司 array substrate, liquid crystal display panel and array substrate manufacturing method
KR20190098315A (en) * 2018-02-13 2019-08-22 삼성디스플레이 주식회사 Display apparatus
JP2021002053A (en) * 2015-02-13 2021-01-07 株式会社半導体エネルギー研究所 Display device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030069668A (en) * 2002-02-22 2003-08-27 삼성전자주식회사 Active matrix type organic light emitting display device and method of manufacturing the same
JP2005260145A (en) * 2004-03-15 2005-09-22 Seiko Epson Corp Electro-optical device and manufacturing method thereof, and electronic apparatus
KR20060104220A (en) * 2005-03-29 2006-10-09 엘지.필립스 엘시디 주식회사 Array substrate for liquid crystal display device and method of fabricating the same
KR20060104219A (en) * 2005-03-29 2006-10-09 엘지.필립스 엘시디 주식회사 Array substrate for liquid crystal display device and method of fabricating the same
KR20110113040A (en) * 2010-04-08 2011-10-14 엘지디스플레이 주식회사 Array substrate for organic electroluminescent device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030069668A (en) * 2002-02-22 2003-08-27 삼성전자주식회사 Active matrix type organic light emitting display device and method of manufacturing the same
JP2005260145A (en) * 2004-03-15 2005-09-22 Seiko Epson Corp Electro-optical device and manufacturing method thereof, and electronic apparatus
KR20060104220A (en) * 2005-03-29 2006-10-09 엘지.필립스 엘시디 주식회사 Array substrate for liquid crystal display device and method of fabricating the same
KR20060104219A (en) * 2005-03-29 2006-10-09 엘지.필립스 엘시디 주식회사 Array substrate for liquid crystal display device and method of fabricating the same
KR20110113040A (en) * 2010-04-08 2011-10-14 엘지디스플레이 주식회사 Array substrate for organic electroluminescent device

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150100566A (en) * 2014-02-24 2015-09-02 엘지디스플레이 주식회사 Thin Film Transistor Substrate And Display Using The Same
KR20160029165A (en) * 2014-09-04 2016-03-15 엘지디스플레이 주식회사 Organic light emitting display panel and fabricating thereof
US9331101B2 (en) 2014-09-04 2016-05-03 Lg Display Co., Ltd. Organic light emitting display panel
CN105789244A (en) * 2014-09-04 2016-07-20 乐金显示有限公司 Organic light emitting display panel and method of manufacturing the same
US9484395B2 (en) 2014-09-04 2016-11-01 Lg Display Co., Ltd. Method of manufacturing organic light emitting display panel
CN105789244B (en) * 2014-09-04 2019-02-19 乐金显示有限公司 Organic light emitting display panel and its manufacturing method
KR20160094579A (en) * 2015-01-30 2016-08-10 엘지디스플레이 주식회사 Organic light emitting display device and method for manufacturing thereof
KR20220017984A (en) * 2015-01-30 2022-02-14 엘지디스플레이 주식회사 Organic light emitting display device and method for manufacturing thereof
JP2022075800A (en) * 2015-02-13 2022-05-18 株式会社半導体エネルギー研究所 Semiconductor device
JP2022176225A (en) * 2015-02-13 2022-11-25 株式会社半導体エネルギー研究所 Display device
JP2022116032A (en) * 2015-02-13 2022-08-09 株式会社半導体エネルギー研究所 Semiconductor device
JP2021002053A (en) * 2015-02-13 2021-01-07 株式会社半導体エネルギー研究所 Display device
JP2018101681A (en) * 2016-12-20 2018-06-28 株式会社Ｊｏｌｅｄ Semiconductor device and display device
KR20190098315A (en) * 2018-02-13 2019-08-22 삼성디스플레이 주식회사 Display apparatus
CN108957884A (en) * 2018-07-23 2018-12-07 深圳市华星光电技术有限公司 array substrate, liquid crystal display panel and array substrate manufacturing method

Also Published As

Publication number Publication date
KR102050401B1 (en) 2019-11-29

Similar Documents

Publication Publication Date Title
KR102050401B1 (en) Display Device and Method of manufacturing the same
US6969889B2 (en) Wire structure, a thin film transistor substrate of using the wire structure and a method of manufacturing the same
KR101346874B1 (en) Semiconductor device and process for production thereof
US8445301B2 (en) Thin-film transistor substrate, method of manufacturing the same, and display device including the same
US9449998B2 (en) Manufacturing method of pixel structure with data line, scan line and gate electrode formed on the same layer
WO2016061940A1 (en) Thin film transistor array substrate and manufacturing method therefor, and display device
KR102305495B1 (en) Thin film transistor substrate and method of manufacturing the same
KR20120039947A (en) Display device and method for manufacturing the same
JP5450802B2 (en) Display device and manufacturing method thereof
KR20100021236A (en) Thin film transistor array panel and method of fabricating the same
KR20110113040A (en) Array substrate for organic electroluminescent device
KR101525883B1 (en) Thin film transistor array panel and method of fabricating the same
US20150263050A1 (en) Pixel Structure and Manufacturing Method thereof
US9741861B2 (en) Display device and method for manufacturing the same
JP5176003B2 (en) Semiconductor device and manufacturing method thereof
TW584908B (en) Method of manufacturing IPS-LCD by using 4-mask process
KR20100050222A (en) Thin film transistor array substrate and method of fabricating the same
KR20150028449A (en) Thin-film transistor substrate and method of manufacturing thin-film transistor substrate
US10553614B2 (en) Thin-film transistor array substrate and manufacturing method for the same
KR20100069935A (en) Thin film transistor array substrate and method for fabricating the same
KR20060088617A (en) Thin film transistor substrate and method of manufacturing for the same
KR20150080674A (en) Display substrate and method of manufacturing the same
KR102527227B1 (en) Thin film transistor substrate and manufacturing method of the same
KR102041973B1 (en) Thin film transistor and Display Device and Method of manufacturing the sames
KR100986907B1 (en) Manufacturing method for liquid crystal display panel and the liquid crystal display panel manufactured thereby

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant