WO2016061940A1 - Thin film transistor array substrate and manufacturing method therefor, and display device - Google Patents

Thin film transistor array substrate and manufacturing method therefor, and display device Download PDF

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Publication number
WO2016061940A1
WO2016061940A1 PCT/CN2015/072142 CN2015072142W WO2016061940A1 WO 2016061940 A1 WO2016061940 A1 WO 2016061940A1 CN 2015072142 W CN2015072142 W CN 2015072142W WO 2016061940 A1 WO2016061940 A1 WO 2016061940A1
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Prior art keywords
thin film
film transistor
conductive layer
array substrate
oxidation
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PCT/CN2015/072142
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French (fr)
Chinese (zh)
Inventor
杨小飞
杨玉清
莫再隆
石天雷
朴承翊
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Publication of WO2016061940A1 publication Critical patent/WO2016061940A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a thin film transistor array substrate, a method of fabricating the same, and a display device.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • the TFT-LCD array substrate is one of the important components of the TFT-LCD.
  • the array substrate includes a display area and a non-display area located at a periphery of the display area, and the display area is formed with horizontally intersecting gate lines and data lines to define a plurality of pixel units, wherein each of the pixel units includes a thin film transistor (Thin Film Transistor) , referred to as TFT) and pixel electrodes.
  • TFT Thin Film Transistor
  • the drain electrode of the TFT is electrically connected to the pixel electrode, the source electrode and the data line are electrically connected, and the gate electrode and the gate line are electrically connected.
  • the thin film transistor is turned on by the gate line, and the pixel voltage transmitted on the data line is transmitted to the pixel electrode through the thin film transistor for driving the liquid crystal molecules to deflect to realize display of a specific gray scale.
  • the non-display area includes a PAD area and a GOA (Gate On Array) area.
  • the GOA region is a region in which a gate switching circuit is formed, and a signal line of the gate switching circuit is formed by a conductive layer forming a signal line (a signal line including a gate line, a data line, and the like) on the array substrate, thereby eliminating the gate.
  • the PAD region is a crimping region, and is located on one side or two adjacent sides of the array substrate, and is a region that connects the signal lines such as the gate lines and the data lines on the array substrate to the pins of the external driving circuit board. , including gate line PAD area, data line PAD area, and the like.
  • the signal lines of the PAD region are also formed by a conductive layer forming signal lines on the array substrate, and the uppermost layer is formed of a transparent conductive layer exposed on the surface for crimping with the pins of the driving chip, as shown in FIG.
  • the mainstream resolution of the display screen on the market has been developed to FHD (PPI above 400), and QHD (PPI above 480) has become a trend.
  • PPI PPI above 400
  • QHD PPI above 480
  • the metal signal lines of the array substrate are usually made of a metal alloy layer such as Ti-Al-Ti.
  • the array substrate of the high PPI display mainly adopts the LTPS process.
  • the basic process of the conventional LTPS TFT array substrate is: buffer layer 2 ⁇ polysilicon active layer (not shown) ⁇ gate insulating layer 3 ⁇ gate metal Layer 4 ⁇ interlayer insulating layer 5 ⁇ source/drain metal layer 6 ⁇ flat layer (generally Acrylic Resin material, not shown) ⁇ first transparent conductive layer 7, for the array substrate for driving the electric field to be a transverse electric field, further includes A second transparent conductive layer 8 is formed.
  • the Acrylic Resin layer is only distributed in the display area of the array substrate.
  • the source-drain metal layer of the signal line of the GOA region and the PAD region directly leaks into the environment, and therefore, when AcrylicResin is cured, it is easily oxidized, which greatly affects the GOA region and the PAD.
  • the present disclosure provides a thin film transistor array substrate, a manufacturing method thereof, and a display device for solving a problem that when a metal conductive layer of a non-display region is exposed to the environment and a thin film pattern is formed only in the display region, the metal conductive layer is oxidized. The problem.
  • the present disclosure provides a thin film transistor array substrate including a display area and a non-display area located at a periphery of the display area, the thin film transistor array substrate including a metal conductive layer located in the non-display area, and a cover
  • the first anti-oxidation structure on the surface of the metal conductive layer protects the metal conductive layer from oxidation.
  • the present disclosure also provides a display device including the thin film transistor array substrate as described above.
  • the present disclosure also provides a method for fabricating a thin film transistor array substrate, the thin film transistor array substrate including a display area and a non-display area located at a periphery of the display area, and the manufacturing method includes:
  • a first oxidation resistant structure covering the surface of the metal conductive layer is formed to protect the metal conductive layer from oxidation.
  • the surface of the metal conductive layer of the non-display area of the array substrate is covered with an oxidation resistant structure to prevent the metal conductive layer from being oxidized, so that when the metal conductive layer is exposed to the environment and formed only in the display area
  • the anti-oxidation structure can protect the thin film pattern
  • the metal conductive layer is not oxidized, reducing the transmission resistance of the metal conductive layer, improving the electrical contact characteristics of the metal conductive layer and the subsequently formed conductive layer, thereby improving the quality of the array substrate.
  • 1 is a schematic structural view of an array substrate
  • Figure 2 is a cross-sectional view along line A-A of Figure 1 of the prior art
  • Figure 3 is a cross-sectional view along line A-A of Figure 1 in an embodiment of the present disclosure
  • FIG. 9, and FIG. 10 are schematic diagrams showing a process of fabricating an array substrate in an embodiment of the present disclosure
  • Fig. 8 is a plan view of Fig. 7.
  • the thin film transistor array substrate includes a display area and a non-display area located at a periphery of the display area, and a non-display area is formed with a conductive layer for transmitting signals for providing a display area with a signal required for display.
  • the conductive layer includes a metal conductive layer.
  • the conductive layer of the non-display area and the conductive layer of the display area are formed by a patterning process of the same material film.
  • the metal conductive layer of the non-display region is exposed to the environment at this time, the metal conductive layer has a problem of being easily oxidized.
  • the present disclosure provides a thin film transistor array substrate and a method of fabricating the same, which can protect the metal conductive layer from being oxidized by forming an oxidation resistant structure covering a surface of the metal conductive layer located in the non-display region.
  • the transmission resistance of the metal conductive layer improves the electrical contact characteristics of the metal conductive layer and the subsequently formed conductive layer, thereby improving the quality of the array substrate.
  • a method for fabricating a thin film transistor array substrate includes a display area and a non-display area located at a periphery of the display area, and the manufacturer The law includes:
  • a first oxidation resistant structure covering the surface of the metal conductive layer is formed to protect the metal conductive layer from oxidation.
  • the metal conductive layer of the non-display area can be protected from being oxidized, the transmission resistance of the metal conductive layer is reduced, and the electrical contact characteristics of the metal conductive layer and the subsequently formed conductive layer are improved, thereby improving The quality of the array substrate.
  • an embodiment of the present disclosure further provides a thin film transistor array substrate including a display area and a non-display area located at a periphery of the display area.
  • the thin film transistor array substrate includes a metal conductive layer located in the non-display area, and a first oxidation resistant structure covering a surface of the metal conductive layer.
  • the first oxidation resistant structure serves to protect the metal conductive layer from oxidation.
  • a thin film pattern located only in the display region is formed, thereby being located in the non-display region in the process of forming the thin film pattern located only in the display region.
  • the surface of the metal conductive layer is covered with an oxidation resistant structure to protect the metal conductive layer from oxidation.
  • the conductive layer pattern of the non-display area and the conductive layer pattern of the display area are simultaneously formed by a patterning process for the same material film.
  • a plurality of pixel units are formed in a display region of the thin film transistor array substrate, and each of the pixel units includes a thin film transistor.
  • the thin film transistor includes a gate electrode, a gate insulating layer, an active layer pattern, a source electrode, and a drain electrode.
  • the gate line and the gate electrode are formed by patterning a film of the same gate metal (metals such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W, and alloys of these metals), data lines
  • the source electrode and the drain electrode are formed by a patterning process of a thin film of the same source/drain metal (metals such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W, and alloys of these metals).
  • the metal conductive layer located in the non-display area in the embodiment of the present disclosure includes a gate metal layer and a source/drain metal layer.
  • the pixel unit of the thin film transistor array substrate further includes a pixel electrode (formed of a transparent conductive film).
  • the conductive layer of the non-display area further includes a transparent conductive layer on the first oxidation resistant structure, and the transparent conductive layer may And electrically contacting the metal conductive layer through the first via in the first oxidation resistant structure. That is, the signal line of the non-display area includes a metal conductive layer and a transparent conductive layer located above the metal conductive layer.
  • the signal line that can set the non-display area includes a gate metal conductive layer, a source/drain metal layer, and a transparent conductive layer.
  • the step of forming the first anti-oxidation structure covering the surface of the metal conductive layer includes:
  • the photoresist semi-reserved area corresponds to a region where the via hole in the first anti-oxidation structure is located, and the photoresist completely reserved region corresponds to a portion of the first anti-oxidation structure from which the first via hole is removed. a region where the photoresist non-reserved region corresponds to other regions;
  • the remaining photoresist is removed.
  • the first via hole in the first anti-oxidation structure and the first anti-oxidation structure may be simultaneously formed by one patterning process, and the first via hole specifically corresponds to the photoresist semi-reserved region.
  • the step of forming the first anti-oxidation structure covering the surface of the metal conductive layer further includes:
  • the thin film pattern located only in the display region After forming the thin film pattern located only in the display region, etching the remaining anti-oxidation film of the photoresist semi-retained region to form the first anti-oxidation structure and the first of the first anti-oxidation structures Through hole. Since the metal conductive layer pattern is covered with the first oxidation resistant structure in the process of forming the thin film only in the display region, it can be effectively protected from oxidation. At the same time, the first via hole in the first anti-oxidation structure can be formed only by the etching process, and the patterning process for fabricating the first via hole is omitted, which simplifies the fabrication process.
  • Thin film transistors can be classified into polycrystalline silicon (Poly-Si, P-Si) TFTs and amorphous silicon (a-Si) TFTs depending on the material of the active layer.
  • the molecular structure of P-Si is in The arrangement in the grain is neat and directional, so the electron mobility is 200-300 times faster than the disordered amorphous silicon.
  • the fabrication process of P-Si mainly includes high temperature polysilicon (HTPS) and low temperature poly-Silicon (LTPS).
  • HTPS high temperature polysilicon
  • LTPS low temperature poly-Silicon
  • the array substrate of the high-resolution display mainly adopts the LTPS process.
  • the non-display area further includes a transparent conductive layer electrically connected to the metal conductive layer to ensure reliable transmission of the electrical signal.
  • the thin film transistor array substrate is an LTPS array substrate including a thin film transistor and a pixel electrode located in the display region, and simultaneously forms a conductive layer of the non-display region in the fabrication process of the thin film transistor and the pixel electrode. Therefore, the method for fabricating the thin film transistor array substrate in the embodiment of the present disclosure further includes:
  • a source/drain metal film Forming a source/drain metal film, patterning the source/drain metal film, forming a source electrode and a drain electrode of the thin film transistor, and a source/drain metal layer located in the non-display region;
  • a source layer and a drain electrode of the thin film transistor are formed, a flat layer located only in the display region is formed.
  • the source/drain metal layer of the non-display region is exposed to the environment, and is easily oxidized when the flat layer is cured.
  • the source/drain metal layer of the non-display region can be effectively protected from oxidation.
  • the specific plan is:
  • a flat layer is formed on the substrate on which the first oxidation resistant structure is formed, the flat layer being located only in a display region of the thin film transistor array substrate.
  • a pixel electrode and a transparent conductive layer located in the non-display region are formed on the substrate on which the flat layer is formed, and the transparent conductive layer and the source/drain metal layer are electrically connected.
  • the transparent conductive layer is a low-temperature transparent conductive layer
  • residue is likely to occur when the transparent conductive film is etched, especially at a position where the film layer difference is large. (Specifically the boundary position of the display area because the flat layer is only located in the display area).
  • the residual transparent conductive film causes adjacent source and drain metal layers to be connected together to form a short circuit.
  • the pixel electrode is in electrical contact with the drain electrode of the thin film transistor through a via hole in the planar layer.
  • the manufacturing process of the flat layer is: coating, exposure development and curing of the Acrylic Resin material, wherein the curing process is performed after the via hole exposing the drain electrode is formed in the flat layer, so that the drain electrode of the thin film transistor exists. Easy to be oxidized.
  • a second oxidation resistant structure covering the drain electrode surface of the thin film transistor is formed to protect the drain electrode Not oxidized.
  • the second anti-oxidation structure and the first anti-oxidation structure may be the same material.
  • a second via hole is formed in the second oxidation resistant structure while forming the first via hole in the first oxidation resistant structure.
  • the pixel electrode is in electrical contact with a drain electrode of the thin film transistor through the second via.
  • the LTPS array substrate of the liquid crystal display device and the driving electric field is a lateral electric field is taken as an example to specifically describe the manufacturing method in the embodiment of the present disclosure.
  • a schematic diagram of a non-display area is shown, and a schematic view of the display area is omitted.
  • a person skilled in the art can obtain a schematic diagram of the display area through a schematic diagram of the non-display area without requiring creative labor.
  • the manufacturing method includes the following steps:
  • Step S1 providing a base substrate 1, which may be a transparent substrate such as a glass substrate, a quartz substrate, or an organic resin substrate, and forming a buffer layer 2 on the base substrate 1, and forming an active layer of the thin film transistor on the buffer layer 2.
  • the pattern is then formed with a gate insulating layer 3 on the active layer pattern.
  • the material of the active layer may be a silicon semiconductor or a metal oxide semiconductor.
  • the material of the buffer layer 2 and the gate insulating layer 3 may be an oxide, a nitride or an oxynitride, and may be a single layer, a double layer or a multilayer structure.
  • the gate insulating layer 3 may be SiNx, SiOx or Si(ON)x.
  • Step S2 simultaneously forming a gate metal layer 4 located in the non-display region, and a gate electrode and a gate located in the display region on the substrate 1 on which the step S1 is completed by patterning the same gate metal film line.
  • a thickness of a thickness of the substrate substrate 1 on which the step S1 is completed may be performed by sputtering or thermal evaporation.
  • the gate metal layer may be a metal such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W, or an alloy of these metals; the gate metal layer may be a single layer structure or a multilayer structure, and the multilayer structure For example, Cu ⁇ Mo, Ti ⁇ Cu ⁇ Ti, Mo ⁇ Al ⁇ Mo, Ti/Al/Ti, and the like.
  • a photoresist is coated on the gate metal film, and the photoresist is exposed and developed by using a mask to form a photoresist non-retained region and a photoresist retention region, wherein the photoresist is retained.
  • the region corresponds to the region where the gate metal layer 4, the gate line and the gate electrode are located, and the photoresist non-retained region corresponds to other regions; the gate metal film of the photoresist non-retained region is completely etched by the etching process, and the remaining portion is peeled off.
  • the photoresist forms a gate metal layer 4, a gate line, and a gate electrode.
  • Step S3 an interlayer insulating layer 5 is formed on the base substrate 1 on which the step S2 is completed, and a via hole is formed in the interlayer insulating layer 5 by a patterning process to expose the gate metal layer 4.
  • the material of the interlayer insulating layer 5 may be an oxide, a nitride or an oxynitride, and may be a single layer, a double layer or a multilayer structure. Specifically, the interlayer insulating layer 5 may be SiNx, SiOx or Si(ON)x.
  • Step S4 forming a source/drain metal layer 6 located in the non-display area, and a source electrode, a drain electrode, and a data line located in the display area on the base substrate 1 completing the step S3 by patterning the same source/drain metal film;
  • the source/drain metal layer 6 is electrically connected to the gate metal layer 4 through via holes in the interlayer insulating layer 5.
  • a thickness of about one layer may be deposited by magnetron sputtering, thermal evaporation, or other film formation method on the substrate 1 on which the step S3 is completed.
  • the source-drain metal film, the source-drain metal film may be a metal such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W, and an alloy of these metals.
  • the source/drain metal layer may be a single layer structure or a multilayer structure such as Cu ⁇ Mo, Ti ⁇ Cu ⁇ Ti, Mo ⁇ Al ⁇ Mo, Ti/Al/Ti, or the like.
  • Step S5 forming an oxidation resistant film 10 on the substrate 1 of the step S4, and performing an patterning process on the oxide film 10 to form the oxidation resistant structure 12;
  • the material of the oxidation resistant film 10 may be an oxide, a nitride or an oxynitride, and may be a single layer, a double layer or a multilayer structure. Specifically, the oxidation resistant film 10 may be SiNx, SiOx or Si(ON)x.
  • the plasma enhanced chemical vapor deposition (PECVD) method can be used to form the oxidation resistant film 10 on the substrate 1 of the step S4;
  • a photoresist 11 is formed on the oxidation resistant film 10;
  • the photoresist 11 is exposed through a gray tone or halftone mask 20 as shown in FIG. 4; wherein the mask 20 includes a semi-transmissive region 13, an opaque region 14, and a fully transparent region 15
  • the exposed photoresist 11 includes a photoresist semi-reserved region 23, a photoresist completely remaining region 24, and a photoresist non-retained region, as shown in FIG.
  • the photoresist semi-reserved region 23 corresponds to the first The area of the first via hole in the oxidation resistant structure 12, the photoresist completely remaining area 24 corresponds to the area where the first anti-oxidation structure 12 removes the portion of the first via hole, and the photoresist non-reserved area corresponds to other areas;
  • the anti-oxidation film 10 of the photoresist non-retained region is etched away;
  • the photoresist of the photoresist semi-retained region 23 is removed by an ashing process, and the photoresist of the photoresist 24 completely retaining the region 24 has a certain thinning effect;
  • a pattern of the first anti-oxidation structure 12 covering the source/drain metal layer 6 of the non-display region and the region of the first via hole in the first anti-oxidation structure 12 is formed, wherein the first via corresponds to the photoresist semi-reserved Area 23.
  • a second anti-oxidation structure (not shown) having the same shape as the first anti-oxidation structure 12 is also formed on the drain electrode of the thin film transistor, covering the surface of the drain electrode because In the fabrication process of the flat layer, the drain electrode is also easily oxidized when exposed to the environment.
  • step S6 a flat layer is formed on the base substrate 1 which is completed in step S5.
  • the material of the flat layer shown is an Acrylic Resin material, which is only located in the display area of the array substrate.
  • the surface of the source/drain metal layer 6 of the non-display region of the array substrate is covered with an anti-oxidation film and is not oxidized.
  • the drain electrode surface of the thin film transistor is also covered with an anti-oxidation film and is not oxidized.
  • the manufacturing process of the flat layer may be:
  • the formed Acrylic Resin film is exposed and developed through a mask to form Acrylic The Resin retention area and the Acrylic Resin non-reserved area, the Acrylic Resin non-retained area at least corresponding to the area where the drain electrode is located, exposing the thinner portion of the second anti-oxidation structure covering the surface of the drain electrode, and the Acrylic Resin reserved area corresponding to other areas ;
  • Step S7 after the step S6 is completed, the thin anti-oxidation film is etched to form the first anti-oxidation structure 12, wherein the first anti-oxidation structure 12 is provided with the first via 30, as shown in FIG. .
  • FIG. 8 is a top view of FIG. 7. It can be seen that the first anti-oxidation structure 12 is formed with a first via hole 30 in the middle thereof to expose the underlying source/drain metal layer 6.
  • the thin portion of the second anti-oxidation structure covering the surface of the drain electrode is simultaneously etched to form a second via hole, and the drain electrode is exposed, so that the subsequently formed pixel electrode and the drain electrode are electrically contacted. And conduct.
  • Step S8 forming a first transparent conductive layer 7 located in the non-display area and a pixel electrode located in the display area on the base substrate 1 completing the step S7 by patterning the same first transparent conductive film, as shown in FIG. .
  • the thickness is deposited by magnetron sputtering, thermal evaporation or other film formation method on the base substrate 1 subjected to step S7.
  • the transparent conductive film, the transparent conductive film may be ITO or IZO.
  • Coating a photoresist on the transparent conductive film exposing and developing the photoresist by using a mask to form a photoresist non-retained region and a photoresist retention region, wherein the photoresist remains
  • the area corresponds to the area where the first transparent conductive layer 7 and the pixel electrode are located, and the photoresist non-reserved area corresponds to other areas; the transparent conductive film of the photoresist non-retained area is completely etched by the etching process, and the remaining lithography is peeled off.
  • the glue forms a first transparent conductive layer 7 and a pixel electrode.
  • the first transparent conductive layer 7 is electrically connected to the source/drain metal layer 6 through the first via hole in the first oxidation resistant structure 12 .
  • the pixel electrode is in electrical contact with the drain electrode of the thin film transistor through the second via hole penetrating the flat layer and the second oxidation resistant structure.
  • Step S9 forming a passivation layer 8 on the substrate 1 on which the step S8 is completed, and forming the passivation layer 8 A patterning process is performed to form passivation layer vias 31.
  • the passivation layer 8 covers at least the active layer of the thin film transistor for ensuring electrical characteristics of the thin film transistor.
  • Step S10 forming a second transparent conductive layer 9 located in the non-display area and a common electrode located in the display area on the base substrate 1 completing the step S9 by patterning the same transparent conductive film, as shown in FIG.
  • the LTPS array substrate formed by the above steps specifically includes:
  • the base substrate 1 is a transparent substrate such as a glass substrate, a quartz substrate, or an organic resin substrate;
  • a gate metal layer 4 formed on the gate insulating layer 3 and located in the non-display region, a gate electrode and a gate line formed on the gate insulating layer 3 and located in the display region, the gate metal layer 4, the gate electrode and the gate line passing through A patterning process of the same gate metal film is formed;
  • a source/drain metal layer 6 formed on the interlayer insulating layer 5 and located in the non-display region, a source electrode, a drain electrode and a data line formed on the interlayer insulating layer 5 and located in the display region, the source/drain metal layer 6, the The source electrode, the drain electrode and the data line are formed by a patterning process on the same source/drain metal film, and the source/drain metal layer 6 is electrically contacted with the gate metal layer 4 through via holes in the interlayer insulating layer 5;
  • a first anti-oxidation structure 12 covering the surface of the source/drain metal layer 6, covering the second anti-oxidation structure on the surface of the drain electrode;
  • the second via in the oxidized structure is in electrical contact with the drain electrode;
  • a patterning process of a transparent conductive film is formed, and the second transparent conductive layer 9 is electrically contacted with the first transparent conductive layer 7 through via holes in the passivation layer 8.
  • the driving electric field of the LTPS array substrate is a transverse electric field
  • the signal line of the non-display area includes the electrically connected gate metal layer 4, the source/drain metal layer 5, the first transparent conductive layer 7, and the second transparent conductive layer 9, which have higher Reliability.
  • the driving electric field is a longitudinal electric field
  • it does not include a passivation layer formed on the pixel electrode and a common electrode formed on the passivation layer, and a fabrication process of the passivation layer and the common electrode is omitted.
  • a display device including the thin film transistor array substrate as described above is also provided in the embodiment of the present disclosure.
  • the display device may be a liquid crystal display device or an active organic light emitting diode display device.
  • the fabrication process of the thin film transistor is the same as described above, and the first oxidation resistant structure covering the surface of the source/drain metal layer of the non-display region can be formed by the same process, and the source/drain metal layer can also be The first via in the first oxidation resistant structure is electrically connected to the subsequently formed conductive layer.
  • the manufacturing process of the organic light emitting diode please refer to the prior art, which will not be described in detail herein.
  • the surface of the metal conductive layer of the non-display area of the array substrate is covered with an oxidation resistant structure to prevent the metal conductive layer from being oxidized, so that when the metal conductive layer is exposed to the environment and formed only When the film pattern of the region is displayed, the oxidation resistant structure can protect the metal conductive layer from being oxidized, reduce the transmission resistance of the metal conductive layer, and improve electrical contact between the metal conductive layer and the subsequently formed conductive layer. characteristic. At the same time, it also facilitates high-density line layout in the non-display area and improves the quality of the array substrate.

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Abstract

A thin film transistor array substrate and a manufacturing method therefor, and a display device. The surface of a metal conductive layer (6) in a non-display region of the array substrate is covered with an antioxidant structure (12) so as to prevent the metal conductive layer (6) from being oxidized.

Description

薄膜晶体管阵列基板及其制作方法、显示装置Thin film transistor array substrate, manufacturing method thereof, and display device
相关申请的交叉引用Cross-reference to related applications
本申请主张在2014年10月24日在中国提交的中国专利申请号No.201410578332.8的优先权，其全部内容通过引用包含于此。The present application claims priority to Chinese Patent Application No. 20141057833, filed on Oct. 24, 2014, the entire content of which is hereby incorporated by reference.
技术领域Technical field
本公开涉及显示技术领域，特别是涉及一种薄膜晶体管阵列基板及其制作方法、显示装置。The present disclosure relates to the field of display technologies, and in particular, to a thin film transistor array substrate, a method of fabricating the same, and a display device.
背景技术Background technique
薄膜晶体管液晶显示器(Thin Film Transistor Liquid Crystal Display，简称TFT-LCD)具有体积小、功耗低、无辐射、制造成本相对较低等特点，在当前的平板显示器市场占据了主导地位。TFT-LCD阵列基板是TFT-LCD的重要部件之一。阵列基板包括显示区域和位于显示区域***的非显示区域，在显示区域形成有横纵交叉的栅线和数据线，以限定多个像素单元，其中，每个像素单元包括薄膜晶体管(Thin Film Transistor，简称TFT)和像素电极。TFT的漏电极和像素电极电性连接，源电极和数据线电性连接，栅电极和栅线电性连接。通过栅线来打开薄膜晶体管，数据线上传输的像素电压通过薄膜晶体管传输至像素电极，用于驱动液晶分子偏转，实现特定灰阶的显示。而非显示区域包括PAD区域和GOA(Gate On Array)区域。GOA区域是集成栅极开关电路的区域，所述栅极开关电路的信号线由形成阵列基板上的信号线(包括栅线、数据线等信号线)的导电层形成，这样可以省掉栅极驱动集成电路。PAD区域即为压接区域，位于阵列基板的一个边或相邻的两个边上，是将阵列基板上的栅线、数据线等信号线与外部驱动电路板的引脚压接连通的区域，包括栅线PAD区域、数据线PAD区域等。PAD区域的信号线也由形成阵列基板上的信号线的导电层形成，且最上层为暴露在表面的透明导电层形成，用于与驱动芯片的引脚压接，如图1所示。Thin Film Transistor Liquid Crystal Display (TFT-LCD) has the characteristics of small size, low power consumption, no radiation, relatively low manufacturing cost, and has a dominant position in the current flat panel display market. The TFT-LCD array substrate is one of the important components of the TFT-LCD. The array substrate includes a display area and a non-display area located at a periphery of the display area, and the display area is formed with horizontally intersecting gate lines and data lines to define a plurality of pixel units, wherein each of the pixel units includes a thin film transistor (Thin Film Transistor) , referred to as TFT) and pixel electrodes. The drain electrode of the TFT is electrically connected to the pixel electrode, the source electrode and the data line are electrically connected, and the gate electrode and the gate line are electrically connected. The thin film transistor is turned on by the gate line, and the pixel voltage transmitted on the data line is transmitted to the pixel electrode through the thin film transistor for driving the liquid crystal molecules to deflect to realize display of a specific gray scale. The non-display area includes a PAD area and a GOA (Gate On Array) area. The GOA region is a region in which a gate switching circuit is formed, and a signal line of the gate switching circuit is formed by a conductive layer forming a signal line (a signal line including a gate line, a data line, and the like) on the array substrate, thereby eliminating the gate. Drive the integrated circuit. The PAD region is a crimping region, and is located on one side or two adjacent sides of the array substrate, and is a region that connects the signal lines such as the gate lines and the data lines on the array substrate to the pins of the external driving circuit board. , including gate line PAD area, data line PAD area, and the like. The signal lines of the PAD region are also formed by a conductive layer forming signal lines on the array substrate, and the uppermost layer is formed of a transparent conductive layer exposed on the surface for crimping with the pins of the driving chip, as shown in FIG.
目前，市场上显示器屏幕的主流分辨率已经发展到FHD(400以上PPI)，QHD(480以上PPI)已成趋势。随着PPI的增加，分辨率变大，特征尺寸变小，对阵列基板上金属信号线的电阻电容的延迟的要求标准越来越高。为 了获得良好的导电特性，阵列基板的金属信号线通常采用金属合金层，如Ti-Al-Ti。At present, the mainstream resolution of the display screen on the market has been developed to FHD (PPI above 400), and QHD (PPI above 480) has become a trend. As the PPI increases, the resolution becomes larger, the feature size becomes smaller, and the requirement for the delay of the resistance and capacitance of the metal signal line on the array substrate becomes higher and higher. For In order to obtain good electrical conductivity, the metal signal lines of the array substrate are usually made of a metal alloy layer such as Ti-Al-Ti.
高PPI显示器的阵列基板主要采用LTPS工艺，结合图2所示，传统的LTPS TFT阵列基板基本工艺为：缓冲层2→多晶硅有源层(图中未示出)→栅绝缘层3→栅金属层4→层间绝缘层5→源漏金属层6→平坦层(一般为Acrylic Resin材料，图中未示出)→第一透明导电层7，对于驱动电场为横向电场的阵列基板，还包括形成第二透明导电层8。其中，所述Acrylic Resin层只分布在阵列基板的显示区域。在形成Acrylic Resin层的制作工艺中，GOA区域和PAD区域信号线的源漏金属层直接暴漏在环境中，因此，在AcrylicResin固化时，很容易被氧化，将极大的影响GOA区域和PAD区域源漏金属层的电阻以及源漏金属层与后续工艺形成的透明导电层的电性接触性能。The array substrate of the high PPI display mainly adopts the LTPS process. As shown in FIG. 2, the basic process of the conventional LTPS TFT array substrate is: buffer layer 2→polysilicon active layer (not shown)→gate insulating layer 3→gate metal Layer 4 → interlayer insulating layer 5 → source/drain metal layer 6 → flat layer (generally Acrylic Resin material, not shown) → first transparent conductive layer 7, for the array substrate for driving the electric field to be a transverse electric field, further includes A second transparent conductive layer 8 is formed. Wherein, the Acrylic Resin layer is only distributed in the display area of the array substrate. In the fabrication process of forming the Acrylic Resin layer, the source-drain metal layer of the signal line of the GOA region and the PAD region directly leaks into the environment, and therefore, when AcrylicResin is cured, it is easily oxidized, which greatly affects the GOA region and the PAD. The electrical resistance of the region source/drain metal layer and the electrical contact properties of the source/drain metal layer and the transparent conductive layer formed by the subsequent process.
发明内容Summary of the invention
本公开提供一种薄膜晶体管阵列基板及其制作方法、显示装置，用以解决当非显示区域的金属导电层暴露在环境中且形成只位于显示区域的薄膜图形时，会造成金属导电层被氧化的问题。The present disclosure provides a thin film transistor array substrate, a manufacturing method thereof, and a display device for solving a problem that when a metal conductive layer of a non-display region is exposed to the environment and a thin film pattern is formed only in the display region, the metal conductive layer is oxidized. The problem.
为解决上述技术问题，本公开提供一种薄膜晶体管阵列基板，包括显示区域和位于显示区域***的非显示区域，所述薄膜晶体管阵列基板包括位于所述非显示区域的金属导电层，以及覆盖所述金属导电层表面的第一抗氧化结构，以保护所述金属导电层不被氧化。In order to solve the above technical problem, the present disclosure provides a thin film transistor array substrate including a display area and a non-display area located at a periphery of the display area, the thin film transistor array substrate including a metal conductive layer located in the non-display area, and a cover The first anti-oxidation structure on the surface of the metal conductive layer protects the metal conductive layer from oxidation.
本公开还提供一种显示装置，包括如上所述的薄膜晶体管阵列基板。The present disclosure also provides a display device including the thin film transistor array substrate as described above.
本公开还提供一种薄膜晶体管阵列基板的制作方法，所述薄膜晶体管阵列基板包括显示区域和位于显示区域***的非显示区域，所述制作方法包括：The present disclosure also provides a method for fabricating a thin film transistor array substrate, the thin film transistor array substrate including a display area and a non-display area located at a periphery of the display area, and the manufacturing method includes:
形成位于所述非显示区域的金属导电层；Forming a metal conductive layer located in the non-display area;
形成覆盖所述金属导电层表面的第一抗氧化结构，以保护所述金属导电层不被氧化。A first oxidation resistant structure covering the surface of the metal conductive layer is formed to protect the metal conductive layer from oxidation.
本公开的上述技术方案的有益效果如下：The beneficial effects of the above technical solutions of the present disclosure are as follows:
上述技术方案中，阵列基板的非显示区域的金属导电层表面覆盖有抗氧化结构，用以防止所述金属导电层被氧化，从而当所述金属导电层暴露在环境中并且形成只位于显示区域的薄膜图形时，所述抗氧化结构可以保护所述 金属导电层不被氧化，降低了所述金属导电层的传输电阻，改善了所述金属导电层与后续形成的导电层的电学接触特性，从而提高了阵列基板的质量。In the above technical solution, the surface of the metal conductive layer of the non-display area of the array substrate is covered with an oxidation resistant structure to prevent the metal conductive layer from being oxidized, so that when the metal conductive layer is exposed to the environment and formed only in the display area The anti-oxidation structure can protect the thin film pattern The metal conductive layer is not oxidized, reducing the transmission resistance of the metal conductive layer, improving the electrical contact characteristics of the metal conductive layer and the subsequently formed conductive layer, thereby improving the quality of the array substrate.
附图说明DRAWINGS
为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings to be used in the embodiments or the prior art description will be briefly described below. Obviously, the drawings in the following description are only some of the embodiments of the present disclosure, and those skilled in the art can obtain other drawings according to the drawings without any inventive labor.
图1表示阵列基板的结构示意图；1 is a schematic structural view of an array substrate;
图2表示现有技术中图1沿A-A的剖视图；Figure 2 is a cross-sectional view along line A-A of Figure 1 of the prior art;
图3表示本公开实施例中图1沿A-A的剖视图；Figure 3 is a cross-sectional view along line A-A of Figure 1 in an embodiment of the present disclosure;
图4-图7、图9和图10表示本公开实施例中阵列基板的制作过程示意图；4, FIG. 9, and FIG. 10 are schematic diagrams showing a process of fabricating an array substrate in an embodiment of the present disclosure;
图8表示图7的俯视图。Fig. 8 is a plan view of Fig. 7.
具体实施方式detailed description
薄膜晶体管阵列基板包括显示区域和位于显示区域***的非显示区域，在非显示区域形成有传输信号的导电层，用于为显示区域提供显示所需的信号。所述导电层包括金属导电层。为简化制作工艺，非显示区域的导电层与显示区域的导电层通过同一材料薄膜的构图工艺形成。The thin film transistor array substrate includes a display area and a non-display area located at a periphery of the display area, and a non-display area is formed with a conductive layer for transmitting signals for providing a display area with a signal required for display. The conductive layer includes a metal conductive layer. In order to simplify the fabrication process, the conductive layer of the non-display area and the conductive layer of the display area are formed by a patterning process of the same material film.
当形成仅位于显示区域的薄膜图形如：液晶显示器件的平坦层时，若此时非显示区域的金属导电层暴露在环境中，则所述金属导电层存在易被氧化的问题。When a thin film pattern such as a liquid crystal display device which is located only in the display region is formed, if the metal conductive layer of the non-display region is exposed to the environment at this time, the metal conductive layer has a problem of being easily oxidized.
为了解决上述技术问题，本公开提供一种薄膜晶体管阵列基板及其制作方法，通过形成覆盖位于非显示区域的金属导电层的表面的抗氧化结构，可以保护所述金属导电层不被氧化，降低了所述金属导电层的传输电阻，改善了所述金属导电层与后续形成的导电层的电学接触特性，从而提高了阵列基板的质量。In order to solve the above technical problem, the present disclosure provides a thin film transistor array substrate and a method of fabricating the same, which can protect the metal conductive layer from being oxidized by forming an oxidation resistant structure covering a surface of the metal conductive layer located in the non-display region. The transmission resistance of the metal conductive layer improves the electrical contact characteristics of the metal conductive layer and the subsequently formed conductive layer, thereby improving the quality of the array substrate.
下面将结合附图和实施例，对本公开的具体实施方式作进一步详细描述。以下实施例用于说明本公开，但不用来限制本公开的范围。Specific embodiments of the present disclosure will be further described in detail below with reference to the drawings and embodiments. The following examples are intended to illustrate the disclosure, but are not intended to limit the scope of the disclosure.
本公开实施例中提供一种薄膜晶体管阵列基板的制作方法，所述薄膜晶体管阵列基板包括显示区域和位于显示区域***的非显示区域，所述制作方 法包括：In the embodiment of the present disclosure, a method for fabricating a thin film transistor array substrate includes a display area and a non-display area located at a periphery of the display area, and the manufacturer The law includes:
形成位于所述非显示区域的金属导电层；Forming a metal conductive layer located in the non-display area;
形成覆盖所述金属导电层表面的第一抗氧化结构，以保护所述金属导电层不被氧化。A first oxidation resistant structure covering the surface of the metal conductive layer is formed to protect the metal conductive layer from oxidation.
通过上述技术方案，可以保护非显示区域的金属导电层不被氧化，降低了所述金属导电层的传输电阻，改善了所述金属导电层与后续形成的导电层的电学接触特性，从而提高了阵列基板的质量。Through the above technical solution, the metal conductive layer of the non-display area can be protected from being oxidized, the transmission resistance of the metal conductive layer is reduced, and the electrical contact characteristics of the metal conductive layer and the subsequently formed conductive layer are improved, thereby improving The quality of the array substrate.
相应地，本公开实施例中还提供一种薄膜晶体管阵列基板，其包括显示区域和位于显示区域***的非显示区域。所述薄膜晶体管阵列基板包括位于所述非显示区域的金属导电层，以及覆盖所述金属导电层表面的第一抗氧化结构。所述第一抗氧化结构用于保护所述金属导电层不被氧化。Accordingly, an embodiment of the present disclosure further provides a thin film transistor array substrate including a display area and a non-display area located at a periphery of the display area. The thin film transistor array substrate includes a metal conductive layer located in the non-display area, and a first oxidation resistant structure covering a surface of the metal conductive layer. The first oxidation resistant structure serves to protect the metal conductive layer from oxidation.
可选地，在形成覆盖所述金属导电层表面的抗氧化结构的步骤之后，再形成仅位于显示区域的薄膜图形，从而在形成仅位于显示区域的薄膜图形的制作工艺中，位于非显示区域的金属导电层表面覆盖有抗氧化结构，可以保护所述金属导电层不被氧化。Optionally, after the step of forming an oxidation resistant structure covering the surface of the metal conductive layer, a thin film pattern located only in the display region is formed, thereby being located in the non-display region in the process of forming the thin film pattern located only in the display region. The surface of the metal conductive layer is covered with an oxidation resistant structure to protect the metal conductive layer from oxidation.
为了简化阵列基板的制作工艺，非显示区域的导电层图形与显示区域的导电层图形通过对同一材料薄膜的构图工艺同时形成。In order to simplify the fabrication process of the array substrate, the conductive layer pattern of the non-display area and the conductive layer pattern of the display area are simultaneously formed by a patterning process for the same material film.
在薄膜晶体管阵列基板的显示区域形成有多个像素单元，每个像素单元包括薄膜晶体管。所述薄膜晶体管包括栅电极、栅绝缘层、有源层图案、源电极和漏电极。其中，栅线和栅电极通过对同一栅金属(Cu，Al，Ag，Mo，Cr，Nd，Ni，Mn，Ti，Ta，W等金属以及这些金属的合金)薄膜的构图工艺形成，数据线、源电极和漏电极通过对同一源漏金属(Cu，Al，Ag，Mo，Cr，Nd，Ni，Mn，Ti，Ta，W等金属以及这些金属的合金)薄膜的构图工艺形成。A plurality of pixel units are formed in a display region of the thin film transistor array substrate, and each of the pixel units includes a thin film transistor. The thin film transistor includes a gate electrode, a gate insulating layer, an active layer pattern, a source electrode, and a drain electrode. Wherein, the gate line and the gate electrode are formed by patterning a film of the same gate metal (metals such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W, and alloys of these metals), data lines The source electrode and the drain electrode are formed by a patterning process of a thin film of the same source/drain metal (metals such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W, and alloys of these metals).
则，本公开实施例中位于非显示区域的金属导电层包括栅金属层和源漏金属层。Then, the metal conductive layer located in the non-display area in the embodiment of the present disclosure includes a gate metal layer and a source/drain metal layer.
对于液晶显示装置，薄膜晶体管阵列基板的像素单元还包括像素电极(由透明导电薄膜形成)。为了保证非显示区域信号传输的可靠性，非显示区域的导电层还包括位于所述第一抗氧化结构上的透明导电层，所述透明导电层可 以通过所述第一抗氧化结构中的第一过孔与金属导电层电性接触。即，非显示区域的信号线包括金属导电层和位于金属导电层上方的透明导电层。For a liquid crystal display device, the pixel unit of the thin film transistor array substrate further includes a pixel electrode (formed of a transparent conductive film). In order to ensure the reliability of signal transmission in the non-display area, the conductive layer of the non-display area further includes a transparent conductive layer on the first oxidation resistant structure, and the transparent conductive layer may And electrically contacting the metal conductive layer through the first via in the first oxidation resistant structure. That is, the signal line of the non-display area includes a metal conductive layer and a transparent conductive layer located above the metal conductive layer.
则，本公开实施例中薄膜晶体管阵列基板的制作方法还包括：The method for fabricating the thin film transistor array substrate in the embodiment of the present disclosure further includes:
在所述第一抗氧化结构上形成透明导电层；Forming a transparent conductive layer on the first oxidation resistant structure;
在所述第一抗氧化结构中形成第一过孔，所述透明导电层通过所述第一过孔与所述金属导电层电性接触。Forming a first via in the first oxidation resistant structure, the transparent conductive layer being in electrical contact with the metal conductive layer through the first via.
更进一步地，可以设置非显示区域的信号线包括栅金属导电层、源漏金属层和透明导电层。Further, the signal line that can set the non-display area includes a gate metal conductive layer, a source/drain metal layer, and a transparent conductive layer.
本公开实施例中，形成覆盖金属导电层表面的第一抗氧化结构的步骤包括：In the embodiment of the present disclosure, the step of forming the first anti-oxidation structure covering the surface of the metal conductive layer includes:
在所述金属导电层上形成抗氧化薄膜；Forming an oxidation resistant film on the metal conductive layer;
在所述抗氧化薄膜上涂覆光刻胶，采用半色调或灰色调掩膜板对光刻胶进行曝光，形成光刻胶不保留区域、光刻胶完全保留区域和光刻胶半保留区域，所述光刻胶半保留区域对应所述第一抗氧化结构中的过孔所在的区域，所述光刻胶完全保留区域对应所述第一抗氧化结构除去第一过孔的部分所在的区域，所述光刻胶不保留区域对应其他区域；Coating the photoresist on the anti-oxidation film, and exposing the photoresist by using a halftone or gray tone mask to form a photoresist non-retained region, a photoresist completely reserved region, and a photoresist semi-reserved region. The photoresist semi-reserved area corresponds to a region where the via hole in the first anti-oxidation structure is located, and the photoresist completely reserved region corresponds to a portion of the first anti-oxidation structure from which the first via hole is removed. a region where the photoresist non-reserved region corresponds to other regions;
刻蚀掉所述光刻胶不保留区域的抗氧化薄膜；Etching the anti-oxidation film of the photoresist non-retained region;
通过灰化工艺去除所述光刻胶半保留区域的光刻胶；Removing the photoresist of the semi-reserved region of the photoresist by an ashing process;
刻蚀一定厚度的、位于所述光刻胶半保留区域的抗氧化薄膜；Etching an anti-oxidation film of a certain thickness in the semi-reserved region of the photoresist;
去除剩余的光刻胶。The remaining photoresist is removed.
上述步骤中，可以通过一次构图工艺同时形成第一抗氧化结构和第一抗氧化结构中的第一过孔，所述第一过孔具体对应所述光刻胶半保留区域。In the above step, the first via hole in the first anti-oxidation structure and the first anti-oxidation structure may be simultaneously formed by one patterning process, and the first via hole specifically corresponds to the photoresist semi-reserved region.
进一步地，形成覆盖金属导电层表面的第一抗氧化结构的步骤还包括：Further, the step of forming the first anti-oxidation structure covering the surface of the metal conductive layer further includes:
在形成仅位于显示区域的薄膜图形的步骤之后，刻蚀掉所述光刻胶半保留区域剩余的抗氧化薄膜，形成所述第一抗氧化结构以及所述第一抗氧化结构中的第一过孔。由于在形成仅位于显示区域的薄膜的制作工艺中，金属导电层图形上覆盖有第一抗氧化结构，所以可以有效保护其不会被氧化。同时，仅通过刻蚀工艺即可形成第一抗氧化结构中的第一过孔，省略了制作第一过孔的构图工艺，简化了制作过程。 After forming the thin film pattern located only in the display region, etching the remaining anti-oxidation film of the photoresist semi-retained region to form the first anti-oxidation structure and the first of the first anti-oxidation structures Through hole. Since the metal conductive layer pattern is covered with the first oxidation resistant structure in the process of forming the thin film only in the display region, it can be effectively protected from oxidation. At the same time, the first via hole in the first anti-oxidation structure can be formed only by the etching process, and the patterning process for fabricating the first via hole is omitted, which simplifies the fabrication process.
薄膜晶体管(Thin Film Transistor，TFT)根据有源层材料的不同，可分为多晶硅(Poly-Si，P-Si)TFT与非晶硅(a-Si)TFT，P-Si的分子结构在一颗晶粒(Grain)中的排列状态是整齐而有方向性的，因此电子移动率比排列杂乱的非晶硅快了200-300倍。P-Si的制作工艺主要包含高温多晶硅(HTPS)与低温多晶硅(Low Temperature Poly-Silicon，LTPS)两种工艺。高分辨率显示器的阵列基板主要采用LTPS工艺。Thin film transistors (TFTs) can be classified into polycrystalline silicon (Poly-Si, P-Si) TFTs and amorphous silicon (a-Si) TFTs depending on the material of the active layer. The molecular structure of P-Si is in The arrangement in the grain is neat and directional, so the electron mobility is 200-300 times faster than the disordered amorphous silicon. The fabrication process of P-Si mainly includes high temperature polysilicon (HTPS) and low temperature poly-Silicon (LTPS). The array substrate of the high-resolution display mainly adopts the LTPS process.
对于液晶显示装置，可选地，非显示区域还包括透明导电层，与金属导电层电性连接，以保证电学信号的可靠传输。在一个具体实施方式中，薄膜晶体管阵列基板为LTPS阵列基板，包括位于显示区域的薄膜晶体管和像素电极，并在薄膜晶体管和像素电极的制作工艺中，同时形成非显示区域的导电层。因此，本公开实施例中薄膜晶体管阵列基板的制作方法还具体包括：For the liquid crystal display device, optionally, the non-display area further includes a transparent conductive layer electrically connected to the metal conductive layer to ensure reliable transmission of the electrical signal. In one embodiment, the thin film transistor array substrate is an LTPS array substrate including a thin film transistor and a pixel electrode located in the display region, and simultaneously forms a conductive layer of the non-display region in the fabrication process of the thin film transistor and the pixel electrode. Therefore, the method for fabricating the thin film transistor array substrate in the embodiment of the present disclosure further includes:
形成源漏金属薄膜，对所述源漏金属薄膜进行构图工艺，形成薄膜晶体管的源电极和漏电极，以及位于非显示区域的源漏金属层；Forming a source/drain metal film, patterning the source/drain metal film, forming a source electrode and a drain electrode of the thin film transistor, and a source/drain metal layer located in the non-display region;
形成透明导电薄膜，对所述透明导电薄膜进行构图工艺，形成像素电极和位于非显示区域的透明导电层，所述透明导电层和源漏金属层电性连接。Forming a transparent conductive film, and patterning the transparent conductive film to form a pixel electrode and a transparent conductive layer located in the non-display region, wherein the transparent conductive layer and the source/drain metal layer are electrically connected.
由于在形成薄膜晶体管的源电极和漏电极后，会形成仅位于显示区域的平坦层。在制作平坦层的制作工艺(包括Acrylic Resin材料的涂覆，曝光显影和固化)中，非显示区域的源漏金属层暴露在环境中，在平坦层固化时，易被氧化。通过本公开的技术方案，可以有效保护非显示区域的源漏金属层不被氧化。具体的方案为：Since a source layer and a drain electrode of the thin film transistor are formed, a flat layer located only in the display region is formed. In the fabrication process for making a flat layer (including coating of Acrylic Resin material, exposure development and curing), the source/drain metal layer of the non-display region is exposed to the environment, and is easily oxidized when the flat layer is cured. With the technical solution of the present disclosure, the source/drain metal layer of the non-display region can be effectively protected from oxidation. The specific plan is:
在一基板上形成薄膜晶体管的源电极和漏电极，以及位于非显示区域的源漏金属层；Forming a source electrode and a drain electrode of the thin film transistor on a substrate, and a source/drain metal layer located in the non-display region;
形成覆盖所述源漏金属层的第一抗氧化结构；Forming a first anti-oxidation structure covering the source/drain metal layer;
在形成有所述第一抗氧化结构的基板上形成平坦层，所述平坦层仅位于薄膜晶体管阵列基板的显示区域。A flat layer is formed on the substrate on which the first oxidation resistant structure is formed, the flat layer being located only in a display region of the thin film transistor array substrate.
在形成有所述平坦层的基板上形成像素电极和位于非显示区域的透明导电层，所述透明导电层和源漏金属层电性连接。A pixel electrode and a transparent conductive layer located in the non-display region are formed on the substrate on which the flat layer is formed, and the transparent conductive layer and the source/drain metal layer are electrically connected.
在形成所述透明导电层的构图工艺中，由于所述透明导电层为低温透明导电层，在刻蚀透明导电薄膜的时候易发生残留，尤其在膜层段差大的位置 (具体为显示区域的边界位置，因为平坦层仅位于显示区域)。现有技术中，由于源漏金属层裸露在外，残留的透明导电薄膜使得相邻的源漏金属层连接在一起，形成短路。而通过采用本公开的技术方案，即使刻蚀工艺中存在残留的透明导电薄膜，由于源漏金属层上覆盖有所述第一抗氧化结构，因而不会造成相邻的源漏金属层连接短路，有利于实现高密度的线排布。In the patterning process for forming the transparent conductive layer, since the transparent conductive layer is a low-temperature transparent conductive layer, residue is likely to occur when the transparent conductive film is etched, especially at a position where the film layer difference is large. (Specifically the boundary position of the display area because the flat layer is only located in the display area). In the prior art, since the source/drain metal layer is exposed, the residual transparent conductive film causes adjacent source and drain metal layers to be connected together to form a short circuit. By adopting the technical solution of the present disclosure, even if there is a residual transparent conductive film in the etching process, since the source and drain metal layers are covered with the first anti-oxidation structure, the adjacent source/drain metal layers are not short-circuited. It is conducive to achieving high-density line layout.
在LTPS阵列基板的制作工艺中，像素电极通过所述平坦层中的过孔与薄膜晶体管的漏电极电性接触。而由于平坦层的制作工艺为：Acrylic Resin材料的涂覆，曝光显影和固化，其中，在所述平坦层中形成露出漏电极的过孔后才进行固化工艺，这样会存在薄膜晶体管的漏电极易被氧化的问题。In the fabrication process of the LTPS array substrate, the pixel electrode is in electrical contact with the drain electrode of the thin film transistor through a via hole in the planar layer. The manufacturing process of the flat layer is: coating, exposure development and curing of the Acrylic Resin material, wherein the curing process is performed after the via hole exposing the drain electrode is formed in the flat layer, so that the drain electrode of the thin film transistor exists. Easy to be oxidized.
对于上述问题，本公开实施例中在形成覆盖非显示区域的源漏金属层的第一抗氧化结构的同时，形成覆盖薄膜晶体管的漏电极表面的第二抗氧化结构，以保护所述漏电极不被氧化。其中所述第二抗氧化结构与第一抗氧化结构可以为同一材质。For the above problem, in the embodiment of the present disclosure, while forming the first oxidation resistant structure covering the source/drain metal layer of the non-display region, a second oxidation resistant structure covering the drain electrode surface of the thin film transistor is formed to protect the drain electrode Not oxidized. The second anti-oxidation structure and the first anti-oxidation structure may be the same material.
进一步地，在所述第一抗氧化结构中形成第一过孔的同时，在所述第二抗氧化结构中形成第二过孔。所述像素电极通过所述第二过孔与薄膜晶体管的漏电极电性接触。Further, a second via hole is formed in the second oxidation resistant structure while forming the first via hole in the first oxidation resistant structure. The pixel electrode is in electrical contact with a drain electrode of the thin film transistor through the second via.
结合图3、图4-图10所示，下面以液晶显示装置的、且驱动电场为横向电场的LTPS阵列基板为例，来具体介绍本公开实施例中的制作方法，其中，各个附图仅示出了非显示区域的示意图，而略去了显示区域的示意图。本领域技术人员可以通过非显示区域的示意图来获得显示区域的示意图，而无需付出创造性的劳动。所述制作方法包括以下步骤：As shown in FIG. 3 and FIG. 4 to FIG. 10 , the LTPS array substrate of the liquid crystal display device and the driving electric field is a lateral electric field is taken as an example to specifically describe the manufacturing method in the embodiment of the present disclosure. A schematic diagram of a non-display area is shown, and a schematic view of the display area is omitted. A person skilled in the art can obtain a schematic diagram of the display area through a schematic diagram of the non-display area without requiring creative labor. The manufacturing method includes the following steps:
步骤S1、提供一衬底基板1，其可以为玻璃基板、石英基板、有机树脂基板等透明基板，并在衬底基板1上形成缓冲层2，在缓冲层2上形成薄膜晶体管的有源层图案，然后在有源层图案上形成栅绝缘层3。Step S1, providing a base substrate 1, which may be a transparent substrate such as a glass substrate, a quartz substrate, or an organic resin substrate, and forming a buffer layer 2 on the base substrate 1, and forming an active layer of the thin film transistor on the buffer layer 2. The pattern is then formed with a gate insulating layer 3 on the active layer pattern.
其中，有源层的材料可以为硅半导体，也可以为金属氧化物半导体。缓冲层2和栅绝缘层3材料可以选用氧化物、氮化物或者氮氧化物，可以为单层、双层或多层结构。具体地，栅绝缘层3可以是SiNx，SiOx或Si(ON)x。The material of the active layer may be a silicon semiconductor or a metal oxide semiconductor. The material of the buffer layer 2 and the gate insulating layer 3 may be an oxide, a nitride or an oxynitride, and may be a single layer, a double layer or a multilayer structure. Specifically, the gate insulating layer 3 may be SiNx, SiOx or Si(ON)x.
步骤S2、通过对同一栅金属薄膜的构图工艺在完成步骤S1的衬底基板1上同时形成位于非显示区域的栅金属层4，以及位于显示区域的栅电极和栅 线。Step S2, simultaneously forming a gate metal layer 4 located in the non-display region, and a gate electrode and a gate located in the display region on the substrate 1 on which the step S1 is completed by patterning the same gate metal film line.
具体地，可以采用溅射或热蒸发的方法在完成步骤S1的衬底基板1上沉积一层厚度为
Figure PCTCN2015072142-appb-000001
的栅金属薄膜。栅金属层可以是Cu、Al、Ag、Mo、Cr、Nd、Ni、Mn、Ti、Ta、W等金属以及这些金属的合金；栅金属层可以为单层结构或者多层结构，多层结构比如Cu\Mo、Ti\Cu\Ti、Mo\Al\Mo、Ti/Al/Ti等。Specifically, a thickness of a thickness of the substrate substrate 1 on which the step S1 is completed may be performed by sputtering or thermal evaporation.
Figure PCTCN2015072142-appb-000001
Grid metal film. The gate metal layer may be a metal such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W, or an alloy of these metals; the gate metal layer may be a single layer structure or a multilayer structure, and the multilayer structure For example, Cu\Mo, Ti\Cu\Ti, Mo\Al\Mo, Ti/Al/Ti, and the like.
在栅金属薄膜上涂覆一层光刻胶，采用掩膜板对光刻胶进行曝光，显影，使光刻胶形成光刻胶不保留区域和光刻胶保留区域，其中，光刻胶保留区域对应于栅金属层4、栅线和栅电极的所在区域，光刻胶不保留区域对应于其他区域；通过刻蚀工艺完全刻蚀掉光刻胶不保留区域的栅金属薄膜，剥离剩余的光刻胶，形成栅金属层4、栅线和栅电极。A photoresist is coated on the gate metal film, and the photoresist is exposed and developed by using a mask to form a photoresist non-retained region and a photoresist retention region, wherein the photoresist is retained. The region corresponds to the region where the gate metal layer 4, the gate line and the gate electrode are located, and the photoresist non-retained region corresponds to other regions; the gate metal film of the photoresist non-retained region is completely etched by the etching process, and the remaining portion is peeled off. The photoresist forms a gate metal layer 4, a gate line, and a gate electrode.
步骤S3、在完成步骤S2的衬底基板1上形成层间绝缘层5，通过构图工艺在层间绝缘层5中形成过孔，露出栅金属层4。Step S3, an interlayer insulating layer 5 is formed on the base substrate 1 on which the step S2 is completed, and a via hole is formed in the interlayer insulating layer 5 by a patterning process to expose the gate metal layer 4.
其中，层间绝缘层5材料可以选用氧化物、氮化物或者氮氧化物，可以为单层、双层或多层结构。具体地，层间绝缘层5可以是SiNx，SiOx或Si(ON)x。The material of the interlayer insulating layer 5 may be an oxide, a nitride or an oxynitride, and may be a single layer, a double layer or a multilayer structure. Specifically, the interlayer insulating layer 5 may be SiNx, SiOx or Si(ON)x.
步骤S4、通过对同一源漏金属薄膜的构图工艺在完成步骤S3的衬底基板1上形成位于非显示区域的源漏金属层6，以及位于显示区域的源电极、漏电极和数据线；Step S4, forming a source/drain metal layer 6 located in the non-display area, and a source electrode, a drain electrode, and a data line located in the display area on the base substrate 1 completing the step S3 by patterning the same source/drain metal film;
其中，源漏金属层6通过层间绝缘层5中的过孔与栅金属层4电性接触。The source/drain metal layer 6 is electrically connected to the gate metal layer 4 through via holes in the interlayer insulating layer 5.
具体地，可以在完成步骤S3的衬底基板1上采用磁控溅射、热蒸发或其它成膜方法沉积一层厚度约为
Figure PCTCN2015072142-appb-000002
的源漏金属薄膜，源漏金属薄膜可以是Cu、Al、Ag、Mo、Cr、Nd、Ni、Mn、Ti、Ta、W等金属以及这些金属的合金。源漏金属层可以是单层结构或者多层结构，多层结构比如Cu\Mo、Ti\Cu\Ti、Mo\Al\Mo、Ti/Al/Ti等。Specifically, a thickness of about one layer may be deposited by magnetron sputtering, thermal evaporation, or other film formation method on the substrate 1 on which the step S3 is completed.
Figure PCTCN2015072142-appb-000002
The source-drain metal film, the source-drain metal film may be a metal such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W, and an alloy of these metals. The source/drain metal layer may be a single layer structure or a multilayer structure such as Cu\Mo, Ti\Cu\Ti, Mo\Al\Mo, Ti/Al/Ti, or the like.
步骤S5、在完成步骤S4的衬底基板1上形成抗氧化薄膜10，对抗氧化薄膜10进行构图工艺形成抗氧化结构12；Step S5, forming an oxidation resistant film 10 on the substrate 1 of the step S4, and performing an patterning process on the oxide film 10 to form the oxidation resistant structure 12;
其中，抗氧化薄膜10的材料可以选用氧化物、氮化物或者氮氧化物，可以为单层、双层或多层结构。具体地，抗氧化薄膜10可以是SiNx，SiOx或Si(ON)x。 The material of the oxidation resistant film 10 may be an oxide, a nitride or an oxynitride, and may be a single layer, a double layer or a multilayer structure. Specifically, the oxidation resistant film 10 may be SiNx, SiOx or Si(ON)x.
具体地，首先，可以采用等离子体增强化学气相沉积(PECVD)方法在完成步骤S4的衬底基板1上形成抗氧化薄膜10；Specifically, first, the plasma enhanced chemical vapor deposition (PECVD) method can be used to form the oxidation resistant film 10 on the substrate 1 of the step S4;
之后，在抗氧化薄膜10上形成光刻胶11；Thereafter, a photoresist 11 is formed on the oxidation resistant film 10;
之后，通过灰色调或半色调掩膜板20对光刻胶11进行曝光，如图4所示；其中，掩膜板20包括半透光区域13、不透光区域14和全透光区域15；曝光后的光刻胶11包括光刻胶半保留区域23、光刻胶完全保留区域24和光刻胶不保留区域，结合图5所示；其中，光刻胶半保留区域23对应第一抗氧化结构12中的第一过孔所在的区域，光刻胶完全保留区域24对应第一抗氧化结构12除去第一过孔的部分所在的区域，光刻胶不保留区域对应其他区域；Thereafter, the photoresist 11 is exposed through a gray tone or halftone mask 20 as shown in FIG. 4; wherein the mask 20 includes a semi-transmissive region 13, an opaque region 14, and a fully transparent region 15 The exposed photoresist 11 includes a photoresist semi-reserved region 23, a photoresist completely remaining region 24, and a photoresist non-retained region, as shown in FIG. 5; wherein the photoresist semi-reserved region 23 corresponds to the first The area of the first via hole in the oxidation resistant structure 12, the photoresist completely remaining area 24 corresponds to the area where the first anti-oxidation structure 12 removes the portion of the first via hole, and the photoresist non-reserved area corresponds to other areas;
之后，刻蚀掉光刻胶不保留区域的抗氧化薄膜10；Afterwards, the anti-oxidation film 10 of the photoresist non-retained region is etched away;
之后，通过灰化工艺去除光刻胶半保留区域23的光刻胶，并对刻胶完全保留区域24的光刻胶有一定的减薄作用；Thereafter, the photoresist of the photoresist semi-retained region 23 is removed by an ashing process, and the photoresist of the photoresist 24 completely retaining the region 24 has a certain thinning effect;
然后，刻蚀一定厚度的、位于光刻胶半保留区域23的抗氧化薄膜10；Then, etching a certain thickness of the anti-oxidation film 10 in the photoresist semi-retained region 23;
最后，剥离剩余的光刻胶，如图6所示。Finally, the remaining photoresist is stripped as shown in FIG.
至此，形成覆盖非显示区域的源漏金属层6的第一抗氧化结构12以及第一抗氧化结构12中的第一过孔所在区域的图形，其中，第一过孔对应光刻胶半保留区域23。So far, a pattern of the first anti-oxidation structure 12 covering the source/drain metal layer 6 of the non-display region and the region of the first via hole in the first anti-oxidation structure 12 is formed, wherein the first via corresponds to the photoresist semi-reserved Area 23.
在上述制作工艺过程中，同时在薄膜晶体管的漏电极上也形成与第一抗氧化结构12形状相同的第二抗氧化结构(图中未示出)，覆盖在漏电极的表面，因为在后续平坦层的制作工艺中，漏电极暴露在环境中也易被氧化。During the above fabrication process, a second anti-oxidation structure (not shown) having the same shape as the first anti-oxidation structure 12 is also formed on the drain electrode of the thin film transistor, covering the surface of the drain electrode because In the fabrication process of the flat layer, the drain electrode is also easily oxidized when exposed to the environment.
步骤S6、在完成步骤S5的衬底基板1上形成平坦层，所示平坦层的材料为Acrylic Resin材料，仅位于阵列基板的显示区域。在平坦层的制作工艺中，阵列基板的非显示区域的源漏金属层6表面覆盖有抗氧化薄膜，不会被氧化。In step S6, a flat layer is formed on the base substrate 1 which is completed in step S5. The material of the flat layer shown is an Acrylic Resin material, which is only located in the display area of the array substrate. In the fabrication process of the flat layer, the surface of the source/drain metal layer 6 of the non-display region of the array substrate is covered with an anti-oxidation film and is not oxidized.
同时，薄膜晶体管的漏电极表面也覆盖有抗氧化薄膜，不会被氧化。At the same time, the drain electrode surface of the thin film transistor is also covered with an anti-oxidation film and is not oxidized.
具体地，平坦层的制作工艺可以为：Specifically, the manufacturing process of the flat layer may be:
在完成步骤S5的衬底基板1上的显示区域涂覆Acrylic Resin材料，形成Acrylic Resin薄膜；Coating the Acrylic Resin material on the display area on the base substrate 1 of the step S5 to form an Acrylic Resin film;
通过掩膜板对形成的Acrylic Resin薄膜进行曝光、显影，形成Acrylic  Resin保留区域和Acrylic Resin不保留区域，Acrylic Resin不保留区域至少对应漏电极的一部分所在的区域，露出覆盖漏电极表面的第二抗氧化结构的厚度较薄的部分，Acrylic Resin保留区域对应其他区域；The formed Acrylic Resin film is exposed and developed through a mask to form Acrylic The Resin retention area and the Acrylic Resin non-reserved area, the Acrylic Resin non-retained area at least corresponding to the area where the drain electrode is located, exposing the thinner portion of the second anti-oxidation structure covering the surface of the drain electrode, and the Acrylic Resin reserved area corresponding to other areas ;
对Acrylic Resin保留区域的Acrylic Resin薄膜进行固化，形成仅位于显示区域的平坦层，其中，所述平坦层中设置有露出第二抗氧化结构的厚度较薄的部分的过孔，所述第二抗氧化结构覆盖在漏电极的表面。Curing the Acrylic Resin film of the Acrylic Resin retention region to form a flat layer only in the display region, wherein the flat layer is provided with a via having a thinner portion exposing the second oxidation resistant structure, the second The anti-oxidation structure covers the surface of the drain electrode.
步骤S7、在完成步骤S6后，刻蚀掉厚度较薄的抗氧化薄膜，形成第一抗氧化结构12，其中，第一抗氧化结构12中设置有第一过孔30，如图7所示。Step S7, after the step S6 is completed, the thin anti-oxidation film is etched to form the first anti-oxidation structure 12, wherein the first anti-oxidation structure 12 is provided with the first via 30, as shown in FIG. .
图8所示为图7的俯视图，可见，形成的第一抗氧化结构12的中部具有第一过孔30，露出下面的源漏金属层6。8 is a top view of FIG. 7. It can be seen that the first anti-oxidation structure 12 is formed with a first via hole 30 in the middle thereof to expose the underlying source/drain metal layer 6.
在此步骤中，同时刻蚀掉覆盖在漏电极表面的第二抗氧化结构的厚度较薄的部分，形成第二过孔，露出漏电极，可以使得后续形成的像素电极与漏电极电性接触并导通。In this step, the thin portion of the second anti-oxidation structure covering the surface of the drain electrode is simultaneously etched to form a second via hole, and the drain electrode is exposed, so that the subsequently formed pixel electrode and the drain electrode are electrically contacted. And conduct.
步骤S8、通过对同一第一透明导电膜的构图工艺在完成步骤S7的衬底基板1上形成位于非显示区域的第一透明导电层7，以及位于显示区域的像素电极，如图9所示。Step S8, forming a first transparent conductive layer 7 located in the non-display area and a pixel electrode located in the display area on the base substrate 1 completing the step S7 by patterning the same first transparent conductive film, as shown in FIG. .
具体地，在经过步骤S7的衬底基板1上采用磁控溅射、热蒸发或其它成膜方法沉积厚度为
Figure PCTCN2015072142-appb-000003
的透明导电薄膜，透明导电薄膜可以是ITO或IZO。在透明导电薄膜上涂敷一层光刻胶；采用掩膜板对光刻胶进行曝光，显影，使光刻胶形成光刻胶不保留区域和光刻胶保留区域，其中，光刻胶保留区域对应于第一透明导电层7和像素电极所在区域，光刻胶不保留区域对应于其他区域；通过刻蚀工艺完全刻蚀掉光刻胶不保留区域的透明导电薄膜，剥离剩余的光刻胶，形成第一透明导电层7和像素电极。Specifically, the thickness is deposited by magnetron sputtering, thermal evaporation or other film formation method on the base substrate 1 subjected to step S7.
Figure PCTCN2015072142-appb-000003
The transparent conductive film, the transparent conductive film may be ITO or IZO. Coating a photoresist on the transparent conductive film; exposing and developing the photoresist by using a mask to form a photoresist non-retained region and a photoresist retention region, wherein the photoresist remains The area corresponds to the area where the first transparent conductive layer 7 and the pixel electrode are located, and the photoresist non-reserved area corresponds to other areas; the transparent conductive film of the photoresist non-retained area is completely etched by the etching process, and the remaining lithography is peeled off. The glue forms a first transparent conductive layer 7 and a pixel electrode.
其中，第一透明导电层7通过第一抗氧化结构12中的第一过孔与源漏金属层6电性连接。The first transparent conductive layer 7 is electrically connected to the source/drain metal layer 6 through the first via hole in the first oxidation resistant structure 12 .
而在显示区域，像素电极通过贯穿平坦层和第二抗氧化结构的第二过孔与薄膜晶体管的漏电极电性接触。In the display region, the pixel electrode is in electrical contact with the drain electrode of the thin film transistor through the second via hole penetrating the flat layer and the second oxidation resistant structure.
步骤S9、在完成步骤S8的衬底基板1上形成钝化层8，并对钝化层8 进行构图工艺，形成钝化层过孔31。Step S9, forming a passivation layer 8 on the substrate 1 on which the step S8 is completed, and forming the passivation layer 8 A patterning process is performed to form passivation layer vias 31.
在阵列基板的显示区域，钝化层8至少覆盖薄膜晶体管的有源层，用于保证薄膜晶体管的电学特性。In the display region of the array substrate, the passivation layer 8 covers at least the active layer of the thin film transistor for ensuring electrical characteristics of the thin film transistor.
步骤S10、通过对同一透明导电薄膜的构图工艺在完成步骤S9的衬底基板1上形成位于非显示区域的第二透明导电层9，以及位于显示区域的公共电极，如图3所示。Step S10, forming a second transparent conductive layer 9 located in the non-display area and a common electrode located in the display area on the base substrate 1 completing the step S9 by patterning the same transparent conductive film, as shown in FIG.
通过上述步骤形成的LTPS阵列基板具体包括：The LTPS array substrate formed by the above steps specifically includes:
衬底基板1，为透明基板，如：玻璃基板、石英基板、有机树脂基板；The base substrate 1 is a transparent substrate such as a glass substrate, a quartz substrate, or an organic resin substrate;
形成在衬底基板1上的缓冲层2；a buffer layer 2 formed on the base substrate 1;
形成在缓冲层2上的栅绝缘层3；a gate insulating layer 3 formed on the buffer layer 2;
形成在栅绝缘层3上且位于非显示区域的栅金属层4，形成在栅绝缘层3上且位于显示区域的栅电极和栅线，栅金属层4、所述栅电极和栅线通过对同一栅金属薄膜的构图工艺形成；a gate metal layer 4 formed on the gate insulating layer 3 and located in the non-display region, a gate electrode and a gate line formed on the gate insulating layer 3 and located in the display region, the gate metal layer 4, the gate electrode and the gate line passing through A patterning process of the same gate metal film is formed;
形成在栅金属层4、所述栅电极和栅线上的层间绝缘层5；An interlayer insulating layer 5 formed on the gate metal layer 4, the gate electrode and the gate line;
形成在层间绝缘层5上且位于非显示区域的源漏金属层6，形成在层间绝缘层5上且位于显示区域的源电极、漏电极和数据线，源漏金属层6、所述源电极、漏电极和数据线通过对同一源漏金属薄膜的构图工艺形成，源漏金属层6通过层间绝缘层5中的过孔与栅金属层4电性接触；a source/drain metal layer 6 formed on the interlayer insulating layer 5 and located in the non-display region, a source electrode, a drain electrode and a data line formed on the interlayer insulating layer 5 and located in the display region, the source/drain metal layer 6, the The source electrode, the drain electrode and the data line are formed by a patterning process on the same source/drain metal film, and the source/drain metal layer 6 is electrically contacted with the gate metal layer 4 through via holes in the interlayer insulating layer 5;
覆盖在源漏金属层6表面上的第一抗氧化结构12，覆盖在漏电极表面上的第二抗氧化结构；a first anti-oxidation structure 12 covering the surface of the source/drain metal layer 6, covering the second anti-oxidation structure on the surface of the drain electrode;
形成在所述源电极、漏电极和数据线上的平坦层；Forming a flat layer on the source electrode, the drain electrode, and the data line;
形成在第一抗氧化结构12和平坦层上且位于非显示区域的第一透明导电层7，形成在第一抗氧化结构12和平坦层上且位于显示区域的像素电极，第一透明导电层7和像素电极通过对同一透明导电薄膜的构图工艺形成，第一透明导电层7通过第一抗氧化结构12中的第一过孔与源漏金属层6电性接触，像素电极通过第二抗氧化结构中的第二过孔与漏电极电性接触；a first transparent conductive layer 7 formed on the first oxidation resistant structure 12 and the flat layer and located in the non-display region, a pixel electrode formed on the first oxidation resistant structure 12 and the flat layer and located in the display region, the first transparent conductive layer 7 and the pixel electrode are formed by a patterning process on the same transparent conductive film, the first transparent conductive layer 7 is electrically contacted with the source/drain metal layer 6 through the first via hole in the first oxidation resistant structure 12, and the pixel electrode passes the second anti-resistance The second via in the oxidized structure is in electrical contact with the drain electrode;
形成在第一透明导电层7和像素电极上的钝化层8；Forming a passivation layer 8 on the first transparent conductive layer 7 and the pixel electrode;
形成在钝化层8上且位于非显示区域的第二透明导电层9，形成在钝化层8上且位于显示区域的公共电极，第二透明导电层9和公共电极通过对同 一透明导电薄膜的构图工艺形成，第二透明导电层9通过钝化层8中的过孔与第一透明导电层7电性接触。a second transparent conductive layer 9 formed on the passivation layer 8 and located in the non-display region, formed on the passivation layer 8 and located at the common electrode of the display region, and the second transparent conductive layer 9 and the common electrode pass through the same A patterning process of a transparent conductive film is formed, and the second transparent conductive layer 9 is electrically contacted with the first transparent conductive layer 7 through via holes in the passivation layer 8.
上述LTPS阵列基板的驱动电场为横向电场，非显示区域的信号线包括电性连接的栅金属层4、源漏金属层5、第一透明导电层7和第二透明导电层9，具有较高的可靠性。The driving electric field of the LTPS array substrate is a transverse electric field, and the signal line of the non-display area includes the electrically connected gate metal layer 4, the source/drain metal layer 5, the first transparent conductive layer 7, and the second transparent conductive layer 9, which have higher Reliability.
对于驱动电场为纵向电场的阵列基板，其不包括形成在像素电极上的钝化层以及形成在钝化层上的公共电极，省略了钝化层和公共电极的制作工艺。For an array substrate in which the driving electric field is a longitudinal electric field, it does not include a passivation layer formed on the pixel electrode and a common electrode formed on the passivation layer, and a fabrication process of the passivation layer and the common electrode is omitted.
本公开实施例中还提供一种显示装置，其包括如上所述的薄膜晶体管阵列基板。A display device including the thin film transistor array substrate as described above is also provided in the embodiment of the present disclosure.
其中，所述显示装置可以为液晶显示装置，也可以为有源有机发光二极管显示装置。The display device may be a liquid crystal display device or an active organic light emitting diode display device.
对于有源有机发光二极管显示装置，其薄膜晶体管的制作工艺与上述相同，可以通过同样的工艺形成覆盖非显示区域的源漏金属层表面的第一抗氧化结构，所述源漏金属层也可以通过所述第一抗氧化结构中的第一过孔与后续形成的导电层电性连接。而对于有机发光二极管的制作工艺请参见现有技术，在此不再详述。For the active organic light emitting diode display device, the fabrication process of the thin film transistor is the same as described above, and the first oxidation resistant structure covering the surface of the source/drain metal layer of the non-display region can be formed by the same process, and the source/drain metal layer can also be The first via in the first oxidation resistant structure is electrically connected to the subsequently formed conductive layer. For the manufacturing process of the organic light emitting diode, please refer to the prior art, which will not be described in detail herein.
本公开的技术方案中，阵列基板的非显示区域的金属导电层表面覆盖有抗氧化结构，用以防止所述金属导电层被氧化，从而当所述金属导电层暴露在环境中且形成只位于显示区域的薄膜图形时，所述抗氧化结构可以保护所述金属导电层不被氧化，降低了所述金属导电层的传输电阻，改善了所述金属导电层与后续形成的导电层的电学接触特性。同时，还有利于非显示区域实现高密度的线排布，提高了阵列基板的质量。In the technical solution of the present disclosure, the surface of the metal conductive layer of the non-display area of the array substrate is covered with an oxidation resistant structure to prevent the metal conductive layer from being oxidized, so that when the metal conductive layer is exposed to the environment and formed only When the film pattern of the region is displayed, the oxidation resistant structure can protect the metal conductive layer from being oxidized, reduce the transmission resistance of the metal conductive layer, and improve electrical contact between the metal conductive layer and the subsequently formed conductive layer. characteristic. At the same time, it also facilitates high-density line layout in the non-display area and improves the quality of the array substrate.
以上所述仅是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开技术原理的前提下，还可以做出若干改进和替换，这些改进和替换也应视为本公开的保护范围。 The above description is only a preferred embodiment of the present disclosure, and it should be noted that those skilled in the art can make several improvements and substitutions without departing from the principles of the disclosed technology. It should also be considered as the scope of protection of the present disclosure.

Claims (20)

  1. 一种薄膜晶体管阵列基板，包括显示区域和位于显示区域***的非显示区域，所述薄膜晶体管阵列基板包括位于所述非显示区域的金属导电层，其中，所述薄膜晶体管阵列基板还包括：A thin film transistor array substrate includes a display area and a non-display area on the periphery of the display area, the thin film transistor array substrate includes a metal conductive layer in the non-display area, wherein the thin film transistor array substrate further includes:
    覆盖所述金属导电层表面的第一抗氧化结构，以保护所述金属导电层不被氧化。A first oxidation resistant structure covering the surface of the metal conductive layer to protect the metal conductive layer from oxidation.
  2. 根据权利要求1所述的薄膜晶体管阵列基板，还包括：The thin film transistor array substrate of claim 1, further comprising:
    仅位于显示区域的薄膜。A film that is only located in the display area.
  3. 根据权利要求2所述的薄膜晶体管阵列基板，还包括：The thin film transistor array substrate of claim 2, further comprising:
    位于所述第一抗氧化结构上的透明导电层；a transparent conductive layer on the first oxidation resistant structure;
    所述第一抗氧化结构中设置有第一过孔，所述透明导电层通过所述第一过孔与所述金属导电层电性接触。A first via is disposed in the first oxidation resistant structure, and the transparent conductive layer is in electrical contact with the metal conductive layer through the first via.
  4. 根据权利要求3所述的薄膜晶体管阵列基板，其中，所述薄膜晶体管阵列基板为LTPS阵列基板，所述薄膜晶体管阵列基板包括位于显示区域的薄膜晶体管和像素电极，所述仅位于显示区域的薄膜为平坦层；The thin film transistor array substrate according to claim 3, wherein the thin film transistor array substrate is an LTPS array substrate, and the thin film transistor array substrate includes a thin film transistor and a pixel electrode located in a display region, and the thin film is only located in the display region a flat layer;
    所述金属导电层为源漏金属层。The metal conductive layer is a source/drain metal layer.
  5. 根据权利要求4所述的薄膜晶体管阵列基板，其中，所述源漏金属层的材质为Cu\Mo或Ti\Cu\Ti或Mo\Al\Mo或Ti/Al/Ti。The thin film transistor array substrate according to claim 4, wherein the source/drain metal layer is made of Cu\Mo or Ti\Cu\Ti or Mo\Al\Mo or Ti/Al/Ti.
  6. 根据权利要求4所述的薄膜晶体管阵列基板，其中，所述非显示区域的源漏金属层与薄膜晶体管的源电极、漏电极为同一材质；The thin film transistor array substrate according to claim 4, wherein the source/drain metal layer of the non-display region and the source electrode and the drain electrode of the thin film transistor are made of the same material;
    所述非显示区域的透明导电层与像素电极为同一材质。The transparent conductive layer of the non-display area is made of the same material as the pixel electrode.
  7. 根据权利要求4所述的薄膜晶体管阵列基板，还包括：The thin film transistor array substrate of claim 4, further comprising:
    覆盖所述薄膜晶体管的漏电极表面的第二抗氧化结构；a second oxidation resistant structure covering a drain electrode surface of the thin film transistor;
    所述第二抗氧化结构与第一抗氧化结构为同一材质。The second oxidation resistant structure is the same material as the first oxidation resistant structure.
  8. 根据权利要求7所述的薄膜晶体管阵列基板，其中，所述第二抗氧化结构中设置有第二过孔，所述像素电极通过所述第二过孔与薄膜晶体管的漏电极电性接触。The thin film transistor array substrate according to claim 7, wherein a second via hole is disposed in the second oxidation resistant structure, and the pixel electrode is in electrical contact with a drain electrode of the thin film transistor through the second via hole.
  9. 根据权利要求1所述的薄膜晶体管阵列基板，其中，所述第一抗氧化 结构的材质为SiNx、SiOx或Si(ON)x。The thin film transistor array substrate of claim 1, wherein the first oxidation resistance The material of the structure is SiNx, SiOx or Si(ON)x.
  10. 一种显示装置，包括权利要求1-9任一项所述的薄膜晶体管阵列基板。A display device comprising the thin film transistor array substrate of any one of claims 1-9.
  11. 一种薄膜晶体管阵列基板的制作方法，所述薄膜晶体管阵列基板包括显示区域和位于显示区域***的非显示区域，所述制作方法包括：A method of fabricating a thin film transistor array substrate, the thin film transistor array substrate comprising a display area and a non-display area located at a periphery of the display area, the manufacturing method comprising:
    形成位于所述非显示区域的金属导电层，Forming a metal conductive layer located in the non-display area,
    形成覆盖所述金属导电层表面的第一抗氧化结构。A first anti-oxidation structure covering the surface of the metal conductive layer is formed.
  12. 根据强烈要求11所述的制作方法，其中，形成覆盖所述金属导电层表面的第一抗氧化结构的步骤之后，所述制作方法还包括：According to the manufacturing method of claim 11, wherein the step of forming the first anti-oxidation structure covering the surface of the metal conductive layer, the manufacturing method further comprises:
    形成仅位于显示区域的薄膜。A film is formed only in the display area.
  13. 根据强烈要求12所述的制作方法，还包括：According to the production method described in the strong requirement 12, the method further includes:
    在所述第一抗氧化结构上形成透明导电层；Forming a transparent conductive layer on the first oxidation resistant structure;
    在所述第一抗氧化结构中形成第一过孔；Forming a first via in the first oxidation resistant structure;
    所述透明导电层通过所述第一过孔与所述金属导电层电性接触。The transparent conductive layer is in electrical contact with the metal conductive layer through the first via.
  14. 根据权利要求13所述的制作方法，其中，形成所述第一抗氧化结构的步骤包括：The manufacturing method according to claim 13, wherein the forming the first antioxidant structure comprises:
    在所述金属导电层上形成抗氧化薄膜；Forming an oxidation resistant film on the metal conductive layer;
    在所述抗氧化薄膜上涂覆光刻胶，采用半色调或灰色调掩膜板对光刻胶进行曝光，形成光刻胶不保留区域、光刻胶完全保留区域和光刻胶半保留区域，所述光刻胶半保留区域对应所述第一抗氧化结构中的第一过孔所在的区域，所述光刻胶完全保留区域对应所述第一抗氧化结构除去第一过孔的部分所在的区域，所述光刻胶不保留区域对应其他区域；Coating the photoresist on the anti-oxidation film, and exposing the photoresist by using a halftone or gray tone mask to form a photoresist non-retained region, a photoresist completely reserved region, and a photoresist semi-reserved region. The photoresist semi-reserved area corresponds to a region of the first anti-oxidation structure where the first via hole is located, and the photoresist completely reserved region corresponds to the portion of the first anti-oxidation structure that removes the first via hole Where the photoresist does not retain the area corresponding to other areas;
    刻蚀掉所述光刻胶不保留区域的抗氧化薄膜；Etching the anti-oxidation film of the photoresist non-retained region;
    通过灰化工艺去除所述光刻胶半保留区域的光刻胶；Removing the photoresist of the semi-reserved region of the photoresist by an ashing process;
    刻蚀一定厚度的、位于所述光刻胶半保留区域的抗氧化薄膜，；Etching an anti-oxidation film of a certain thickness in the semi-reserved region of the photoresist;
    去除剩余的光刻胶。The remaining photoresist is removed.
  15. 根据权利要求14所述的制作方法，其中，形成所述第一抗氧化结构的步骤还包括：The manufacturing method according to claim 14, wherein the step of forming the first antioxidant structure further comprises:
    在形成仅位于显示区域的薄膜的步骤之后，刻蚀掉对应所述光刻胶半保留区域剩余的抗氧化薄膜，形成所述第一抗氧化结构以及所述第一抗氧化结 构中的第一过孔。After forming the film only in the display region, etching the remaining anti-oxidation film corresponding to the semi-reserved region of the photoresist to form the first anti-oxidation structure and the first anti-oxidation junction The first via in the structure.
  16. 根据权利要求15所述的制作方法，其中，所述薄膜晶体管阵列基板为LTPS阵列基板，所述薄膜晶体管阵列基板包括位于显示区域的薄膜晶体管和像素电极，所述仅位于显示区域的薄膜为平坦层；The fabrication method according to claim 15, wherein the thin film transistor array substrate is an LTPS array substrate, the thin film transistor array substrate comprises a thin film transistor and a pixel electrode located in a display region, and the film located only in the display region is flat Floor;
    所述金属导电层为源漏金属层。The metal conductive layer is a source/drain metal layer.
  17. 根据权利要求16所述的制作方法，其中，在形成所述第一抗氧化结构的同时，形成覆盖薄膜晶体管的漏电极表面的第二抗氧化结构。The fabricating method according to claim 16, wherein a second oxidation resistant structure covering a drain electrode surface of the thin film transistor is formed while forming the first oxidation resistant structure.
  18. 根据权利要求17所述的制作方法，其中，在所述第一抗氧化结构中形成第一过孔的同时，在所述第二抗氧化结构中形成第二过孔，所述像素电极通过所述第二过孔与薄膜晶体管的漏电极电性接触。The fabricating method according to claim 17, wherein a second via hole is formed in the second oxidation resistant structure while the first via hole is formed in the first oxidation resistant structure, and the pixel electrode passes through The second via is in electrical contact with the drain electrode of the thin film transistor.
  19. 根据权利要求16所述的制作方法，还包括：The method according to claim 16, further comprising:
    形成源漏金属薄膜，对所述源漏金属薄膜进行构图工艺，形成薄膜晶体管的源电极和漏电极，以及位于非显示区域的源漏金属层；Forming a source/drain metal film, patterning the source/drain metal film, forming a source electrode and a drain electrode of the thin film transistor, and a source/drain metal layer located in the non-display region;
    形成透明导电薄膜，对所述透明导电薄膜进行构图工艺，形成像素电极，以及位于非显示区域的透明导电层，所述透明导电层与源漏金属层电性连接，所述像素电极与所述源电极电性连接。Forming a transparent conductive film, patterning the transparent conductive film to form a pixel electrode, and a transparent conductive layer located in the non-display area, the transparent conductive layer being electrically connected to the source/drain metal layer, the pixel electrode and the The source electrode is electrically connected.
  20. 根据权利要求11所述的制作方法，其中，非显示区域的导电层图形与显示区域的导电层图形通过对同一材料薄膜的构图工艺同时形成。 The fabricating method according to claim 11, wherein the conductive layer pattern of the non-display area and the conductive layer pattern of the display area are simultaneously formed by a patterning process for the same material film.
PCT/CN2015/072142 2014-10-24 2015-02-03 Thin film transistor array substrate and manufacturing method therefor, and display device WO2016061940A1 (en)

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