KR20130137983A - Nitride semiconductor and method thereof - Google Patents

Nitride semiconductor and method thereof Download PDF

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KR20130137983A
KR20130137983A KR1020120061731A KR20120061731A KR20130137983A KR 20130137983 A KR20130137983 A KR 20130137983A KR 1020120061731 A KR1020120061731 A KR 1020120061731A KR 20120061731 A KR20120061731 A KR 20120061731A KR 20130137983 A KR20130137983 A KR 20130137983A
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layer
gan layer
gan
semiconductor device
oxide film
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KR1020120061731A
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Korean (ko)
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조성무
김광중
장태훈
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엘지전자 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

Abstract

Provided in this specification are a semiconductor device and a manufacturing method thereof having a normally-off property, a little leakage current property and a large yield voltage property via a gate electrode, formed on a region recessed to a second GaN layer or an AlGaN layer, and a first oxide film layer, formed on the second GaN layer, wherein the semiconductor includes a first GaN layer, the AlGaN layer, the gate electrode, a source electrode and a drain electrode. For this, the semiconductor device according to an embodiment comprises: a substrate; the first GaN layer formed on the substrate; the AlGaN layer formed on the first GaN layer; the second GaN layer formed on the AlGaN layer; the gate electrode formed on the region recessed to the second GaN layer or the AlGaN layer; the source electrode and the drain electrode formed on a partial region of the second GaN layer; and the first film oxide layer formed on the second GaN layer, wherein the first oxide film layer is formed between the source electrode or the drain electrode and the recessed region.

Description

Nitride semiconductor device and method for manufacturing the same

The present specification relates to a nitride semiconductor device including a recessed gate structure and an in-situ oxide film and a method of manufacturing the same.

Nitride semiconductors have been studied with high critical electric field, low on resistance, high temperature and high frequency operation characteristics compared with silicon and are being studied as materials of next generation semiconductor devices.

In recent years, high output power devices are mainly mainstream, MOSFETs and IGBTs, and GaN series devices such as HEMTs, HFETs, and MOSFETs have been studied.

In the case of HEMT, the high electron mobility is used for communication devices having high frequency characteristics, but in the case of MOSFETs, there is a lack of a good gate oxide film, and ion implantation for selectively forming a P-type or N-type region. Due to the difficulty of the thermal diffusion process, the effect of the device is less pronounced than the material properties of GaN.

1 is an exemplary view showing a general structure of a heterojunction field effect transistor (HFET).

Referring to FIG. 1, a typical HFET may switch 2DEG current flowing from a drain electrode to a source electrode through a schottky gate electrode.

The general HFET 10 includes a substrate (not shown), a first GaN layer 11 formed on the substrate, an AlGaN layer 12 formed on the first GaN layer, and a second GaN formed on the AlGaN layer. The layer 13 may include a gate electrode 14, a source electrode 15, and a drain electrode 16 formed on the second GaN layer.

In the case of a typical HFET device, the quality of the schottky characteristic using the gate operation can have a big influence on the switch characteristics of the device. What is the role of minimizing the gate side leakage and enlarging the depletion region? More important. In addition, a technique is required to move the threshold voltage (supply voltage) in a positive direction so that the current flow of the two-dimensional electon gas (2DEG) channel in the heterojunction structure can be normally turned off.

There is also a need for a technique that reduces the leakage current of the HFET and maximizes the breakdown voltage.

In the present specification, a semiconductor device including a first GaN layer, an AlGaN layer, a second GaN layer, a gate electrode, a source electrode, and a drain electrode, which are sequentially stacked on a substrate, is recessed to the second GaN layer or the AlGaN layer. To provide a semiconductor device exhibiting a normally-off characteristic, a small leakage current and a large breakdown voltage characteristics through a gate electrode formed on the region and a first oxide layer formed on the second GaN layer and a method of manufacturing the same The purpose is.

A semiconductor device according to the present specification for achieving the above objects, the substrate; A first GaN layer formed on the substrate; An AlGaN layer formed on the first GaN layer; A second GaN layer formed on the AlGaN layer; A gate electrode formed on a region recessed to the second GaN layer or the AlGaN layer; A source electrode and a drain electrode formed on a portion of the second GaN layer; And a first oxide layer formed on the second GaN layer, wherein the first oxide layer is formed between the source electrode or the drain electrode and the recessed region.

As an example related to the present specification, the first oxide layer may be formed of Si x N y .

As an example related to the present specification, the gate electrode may be in contact with an upper portion of one side of the first oxide layer.

As an example related to the present specification, the method may further include a second oxide layer formed on the recessed region, wherein the gate electrode may be formed on the second oxide layer.

As an example related to the present specification, the second oxide layer may be formed of at least one of SiO 2 , Si 3 N 4 , HfO 2 , Al 2 O 3 , ZnO, and Ga 2 O 3 .

As an example related to the present specification, the first oxide layer may be formed in-situ after the formation of the second GaN layer.

As an example related to the present specification, the thickness of the first oxide layer may be 1 nm to 500 nm, and the thickness of the second oxide layer may be 2 nm to 200 nm.

As an example related to the present specification, the first oxide layer or the second oxide layer may be formed of an organic metal vapor deposition method (MOCVD), a molecular beam epitaxial growth method (MBE), a helide vapor deposition method (HVPE), or a PECVD (Plasma). It may be formed based on at least one of enhanced chemical vapor deposition (SPE), sputtering, and atomic layer deposition (ALD).

As an example related to the present specification, the depth of the recessed region may be 1 nm to 1000 nm.

As an example associated with the present specification, the recessed region may have at least one of a trench form, a V-groove form, and a semicircle form.

As an example related to the present specification, the substrate may be at least one of an insulating substrate, a sapphire substrate, a GaN substrate, a SiC substrate, and a Si substrate.

As an example related to the present specification, the thickness of the first GaN layer may be 1 μm to 10 μm.

As an example related to the present specification, the semiconductor device may further include a high-resistance GaN layer formed by injecting at least one dopant among C, Fe, and Mg dopants on the first GaN layer.

As an example related to the present specification, the concentration of the at least one dopant may be 1e 17 / cm 3 to 1e 19 / cm 3 .

As an example related to the present specification, the AlGaN layer may be 2 nm to 100 nm.

As an example related to the present specification, the thickness of the second GaN layer may be 2 nm to 10 nm.

A method of manufacturing a semiconductor device according to the present specification for achieving the above objects comprises the steps of forming a first GaN layer on a substrate; Forming an AlGaN layer on the first GaN layer; Forming a second GaN layer on the AlGaN layer; Forming a first oxide layer on the second GaN layer; Selectively etching the first oxide layer to define a source and a drain region; Forming a source electrode and a drain electrode on the source and drain regions; Forming a recessed region up to the second GaN layer or the AlGaN layer based on the selective etching; And forming a gate electrode on the recessed region.

As an example related to the present specification, the gate electrode may be in contact with an upper portion of one side of the first oxide layer.

As an example related to the present specification, the forming of the gate electrode on the recessed region may include forming a second oxide layer on the recessed region; And forming a gate electrode on the second oxide layer.

As an example related to the present specification, the second GaN layer is formed by deposition equipment based on an organic metal vapor deposition method (MOCVD), and the first oxide layer is formed after the formation of the second GaN layer. It may be formed in-situ in the deposition equipment.

As an example related to the present specification, the first GaN layer, the AlGaN layer, and the second GaN layer may include an organic metal vapor deposition method (MOCVD), a molecular beam epitaxial growth method (MBE), and a helide vapor deposition method (HVPE). It may be formed based on at least one of plasma-enhanced chemical vapor deposition (PECVD), sputtering, and atomic layer deposition (ALD).

According to one embodiment disclosed herein, a semiconductor device comprising a first GaN layer, an AlGaN layer, a second GaN layer, a gate electrode, a source electrode, and a drain electrode sequentially stacked on a substrate, wherein the second GaN layer Or a semiconductor device having a normally-off characteristic, a small leakage current, and a large breakdown voltage characteristic through a gate electrode formed on a region recessed to the AlGaN layer and a first oxide film formed on the second GaN layer; It provides a manufacturing method.

In particular, according to the semiconductor device disclosed in this specification, through the gate electrode formed on the recessed region up to the second GaN layer or AlGaN layer, the depletion region is enlarged so that the threshold voltage (supply voltage) is moved in the positive direction. There is an advantage (or normally-off characteristic).

In addition, leakage current and breakdown voltage characteristics may be improved based on an in-situ oxide film grown immediately after MOCVD nitride thin film growth.

1 is an exemplary view showing a general structure of a heterojunction field effect transistor (HFET).
2A is an exemplary diagram illustrating a structure of a semiconductor device according to an exemplary embodiment disclosed herein.
2B is an exemplary view illustrating a structure of a semiconductor device according to still another embodiment disclosed herein.
3 is an exemplary view illustrating various types of recess regions according to an exemplary embodiment disclosed herein.
4 is a flowchart illustrating a method of manufacturing a semiconductor device in accordance with embodiments disclosed herein.
5A to 5H are exemplary views illustrating a method of manufacturing a semiconductor device in accordance with embodiments disclosed herein.

The technique disclosed herein can be applied to a heterojunction field effect transistor and a method of manufacturing the same. However, the technology disclosed in the present specification is not limited thereto, and may be applied to all nitride based semiconductor devices to which the technical spirit of the technology may be applied and a method of manufacturing the same. In particular, through the gate electrode formed on the region recessed to the second GaN layer or the AlGaN layer, the depletion region is enlarged to have a normally-off characteristic, and is grown in-situ immediately after growth of the MOCVD nitride thin film. situ) It can be applied to a semiconductor device and a method of manufacturing the same that the leakage current and breakdown voltage characteristics are improved based on the oxide film.

Specifically, the technology disclosed in the present disclosure relates to a nitride semiconductor power device and a method of manufacturing the same, and includes a recess structure for controlling an always-on operation at 0V generated during fabrication of a heterojunction HFET device by using an off switch. The goal may be to grow the oxide film in-situ immediately after the growth of the MOCVD nitride film to minimize leakage current increase and breakdown voltage reduction.

In addition, the semiconductor device according to the exemplary embodiment disclosed herein has an advantage of implementing a stable reliability device because the number of carrier concentrations or mobility of the 2DEG is small when the device is operated at a high temperature.

Various oxide films may be used as a method for reducing surface leakage current in a nitride semiconductor power device having a heterojunction structure.

Representative oxide film may be SiO 2 , Si 3 N 4 , HfO 2 or Al 2 O 3 and the like, PECVD, ICP-CVD, Sputter, ALD, etc. may be used as the deposition equipment.

If the oxide film is deposited directly in the equipment after MOCVD nitride film growth (eg in-situ oxide film), it can prevent the V-defect that may occur on the surface due to stress relaxation of the active layer. Contamination that can occur at the interface of the oxide film can be prevented in advance, and the possibility of residual oxide such as Ga 2 O 3 can be prevented in advance.

Meanwhile, various techniques may be used for the normally-off operation of the heterojunction structure nitride semiconductor. For example, there may be a p-GaN gate, recessed gate, MIS structure, quaternary active layer.

The technique disclosed herein aims to bring Vth to 0 V or more by applying a recessed gate structure to partially or fully etch the active layer, and by applying oxide deposition to In-situ. There may be advantages to making high quality normally-off devices.

That is, the technique disclosed in the present specification may be aimed at making a high output device by applying an in-situ oxide film and a recessed gate structure.

It is noted that the technical terms used herein are used only to describe specific embodiments and are not intended to limit the scope of the technology disclosed herein. Also, the technical terms used herein should be interpreted as being generally understood by those skilled in the art to which the presently disclosed subject matter belongs, unless the context clearly dictates otherwise in this specification, Should not be construed in a broader sense, or interpreted in an oversimplified sense. In addition, when a technical term used in this specification is an erroneous technical term that does not accurately express the concept of the technology disclosed in this specification, it should be understood that technical terms which can be understood by a person skilled in the art are replaced. Also, the general terms used in the present specification should be interpreted in accordance with the predefined or prior context, and should not be construed as being excessively reduced in meaning.

Also, the singular forms "as used herein include plural referents unless the context clearly dictates otherwise. In this specification, the terms "comprising ", or" comprising "and the like should not be construed as necessarily including the various elements or steps described in the specification, Or may be further comprised of additional components or steps.

Furthermore, terms including ordinals such as first, second, etc. used in this specification can be used to describe various elements, but the elements should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, wherein like reference numerals are used to designate identical or similar elements, and redundant description thereof will be omitted.

Further, in the description of the technology disclosed in this specification, a detailed description of related arts will be omitted if it is determined that the gist of the technology disclosed in this specification may be obscured. It is to be noted that the attached drawings are only for the purpose of easily understanding the concept of the technology disclosed in the present specification, and should not be construed as limiting the spirit of the technology by the attached drawings.

The In embodiments  Description of semiconductor devices according to

A semiconductor device according to embodiments disclosed herein may include a substrate, a first GaN layer formed on the substrate, an AlGaN layer formed on the first GaN layer, a second GaN layer formed on the AlGaN layer, A gate electrode formed on a region recessed to the second GaN layer or the AlGaN layer, a source electrode and a drain electrode formed on a partial region of the second GaN layer, and a first formed on the second GaN layer Including an oxide layer, wherein the first oxide layer may be formed between the source electrode or the drain electrode and the recessed region.

That is, the technology disclosed herein relates to a nitride semiconductor device (particularly an HFET device) and a method of manufacturing the same. Specifically, in order to prevent leakage current flowing between the source, the gate, and the drain surface, there may be a method of raising an oxide film using PECVD or sputtering or sputtering, but in particular, the technique disclosed herein is MOCVD. Immediately after the nitride film is grown, the oxide film is deposited in the device, and then a gate oxide film is opened in the device fabrication process, or a part or all of the active layer is etched to form a recess to generate a high power. Disclosed is a normally-off device.

According to the semiconductor device disclosed in the present specification and a method of manufacturing the same, in implementing a normally-off device, a surface leakage current is reduced and defects due to stress relaxation of an active layer are identified. By preventing in-situ oxide film, there may be an advantage that the effect of increasing the breakdown voltage with distance may be maximized.

2A is an exemplary diagram illustrating a structure of a semiconductor device according to an exemplary embodiment disclosed herein.

Referring to FIG. 2A, a semiconductor device 100 according to embodiments disclosed herein may include a substrate 110, a first GaN layer 120 formed on the substrate 110, and a first GaN layer. Recessed to the AlGaN layer 130 formed on the 120, the second GaN layer 140, the second GaN layer 140 or the AlGaN layer 130 formed on the AlGaN layer 130 The gate electrode 160 formed on the region R110, the source electrode 170 and the drain electrode 180 formed on the partial region of the second GaN layer 140, and the second GaN layer 140. It may include a first oxide layer 151 formed on.

The first oxide layer 151 may be formed between the source electrode 170 or the drain electrode 180 and the recessed region R110.

In addition, the semiconductor device 100 according to the exemplary embodiment disclosed herein may switch 2DEG current flowing from the drain electrode 180 to the source electrode 170 through a schottky gate electrode. Can be.

According to an embodiment, the substrate 110 may be made of various kinds of materials. For example, the substrate 110 may be at least one of an insulating substrate, a sapphire substrate, a GaN substrate, a SiC substrate, and a Si substrate. In addition, it will be apparent to those skilled in the art that various kinds of substrates may be applied to the semiconductor devices disclosed herein.

In addition, the substrate 110 may be removed after fabrication of the semiconductor device 100. Therefore, the final structure of the semiconductor device 100 may be a structure without the substrate 110.

The first GaN layer 120 may be made of GaN and may have a thickness of about 1 μm to about 10 μm.

The first GaN layer 120 may be formed in various ways (or methods). For example, the first GaN layer 120 may be formed by a method of selectively growing nitride semiconductor crystals, including organic metal vapor deposition (MOCVD), molecular beam epitaxial growth (MBE), and helide vapor deposition. It may be formed based on at least one of the method (HVPE). However, considering the crystallinity of the first GaN (120), it may be common to use the MOCVD method for manufacturing the device.

In example embodiments, the semiconductor device 100 may further include a high-resistance GaN layer (not shown) formed by implanting at least one dopant among C, Fe, and Mg dopants onto the first GaN layer 120. can do.

Here, the concentration of the at least one dopant may be 1e 17 / cm 3 ~ 1e 19 / cm 3 .

The AlGaN layer 130 may be formed on the first GaN layer 120. The AlGaN layer 130 may serve as an active layer.

According to an embodiment, the thickness of the AlGaN layer 130 may be adjusted to a range of 2 nm to 100 nm, preferably 15 nm to 30 nm.

The AlGaN layer 130 may be formed of various materials and compositions. For example, the AlGaN layer 130 may be made of Al x Ga 1 - x N. In addition, it is apparent to those skilled in the art that the AlGaN layer 130 may be formed by various materials or composition ratios.

The second GaN layer 140 is formed on the AlGaN layer 130 and may be formed by thinly growing GaN.

According to one embodiment, the thickness of the second GaN 140 may be in the range of 0nm to 100nm, preferably 2nm to 10nm. The second GaN layer 140 may serve to prevent surface leakage current.

The semiconductor device 100 according to the exemplary embodiment disclosed herein may include a gate electrode 160 formed on a region R110 recessed to the second GaN layer 140 or the AlGaN layer 130. Can be. The gate 160 may be referred to as a recessed gate.

Such a recessed gate can provide an advantage (or normally-off characteristic) in that the threshold voltage (supply voltage) is shifted in the positive direction by enlarging the depletion region near 2DEG.

Here, the depth of the recessed region R110 may be 1 nm to 1000 nm.

In example embodiments, the semiconductor device 100 may include a source electrode 170 and a drain electrode 180 formed on a portion of the second GaN layer 140.

As described above, a 2DEG current flowing from the drain electrode 180 to the source electrode 170 may be generated through the control of the schottky gate electrode 160.

In addition, according to an exemplary embodiment, the semiconductor device 100 may include a first oxide layer 151 formed on the second GaN layer 140.

The first oxide layer 151 may be formed between the source electrode 170 or the drain electrode 180 and the recessed region R110.

The first oxide layer 151 may be formed of various materials or composition ratios. For example, the first oxide layer 151 may be formed of Si x N y .

In addition, according to an embodiment, as shown in FIG. 2A, the gate electrode 160 may be in contact with an upper portion of one side of the first oxide layer 151.

In detail, the gate electrode 160 may be formed over a portion of the recess region R110 and the first oxide layer 151.

The first oxide layer 151 may be formed in-situ after the formation of the second GaN layer 140.

For example, the second GaN layer 140 may be formed by deposition equipment based on organic metal vapor deposition (MOCVD), and the first oxide layer 151 may be formed by the second GaN layer. After the formation of the 140 may be formed in-situ (in-situ) in the deposition equipment.

Specifically, the in-situ first oxide layer 151 may prevent V-defect that may occur on the surface due to stress relaxation of the active layer, and may prevent contamination in advance between the thin film and the oxide layer. In addition, it is possible to prevent the possibility of residual oxide such as Ga 2 O 3 in advance. That is, leakage current and breakdown voltage characteristics may be improved based on the in-situ oxide film.

In addition, according to an embodiment, the thickness of the first oxide layer 151 may be 1 nm to 500 nm.

In addition, the first oxide layer 151 may be formed in various ways. For example, the first oxide layer 1510 may be formed by organometallic vapor deposition (MOCVD), molecular beam epitaxial growth (MBE), or heel. It may be formed based on at least one of the ride vapor deposition (HVPE), plasma-enhanced chemical vapor deposition (PECVD), sputtering and atomic layer deposition (ALD).

2B is an exemplary view illustrating a structure of a semiconductor device according to still another embodiment disclosed herein.

Referring to FIG. 2B, the semiconductor device 100 ′ according to the exemplary embodiments disclosed herein may include a substrate 110, a first GaN layer 120 formed on the substrate 110, and the first GaN. Recesses to the AlGaN layer 130 formed on the layer 120, the second GaN layer 140, the second GaN layer 140, or the AlGaN layer 130 formed on the AlGaN layer 130. A second oxide layer 152 formed on the region R110, a gate electrode 160 formed on the second oxide layer 152, and a partial region of the second GaN layer 140. The source electrode 170, the drain electrode 180, and the first GaN layer 140 may be formed on the second GaN layer 140.

The first oxide layer 151 may be formed between the source electrode 170 or the drain electrode 180 and the recessed region R110.

The semiconductor device 100 ′ shown in FIG. 2B differs from the semiconductor device 100 shown in FIG. 2A. The second oxide layer 152 is present on the recessed region R110. The gate electrode 160 may be formed on the second oxide layer 152.

Through this, the semiconductor device 100 ′ may have a metal-insulator-semiconductor (MIS) structure. In contrast, the semiconductor device 100 disclosed in FIG. 2A may be referred to as a metal-semiconductor (MES) structure.

The second oxide layer 152 for the MIS structure may be deposited using PECVD, Sputter, or ALD.

The second oxide layer 152 may be made of various materials. For example, the second oxide layer 152 may be formed of at least one of SiO 2 , Si 3 N 4 , HfO 2 , Al 2 O 3 , ZnO, and Ga 2 O 3 .

According to one embodiment, the thickness of the second oxide layer 152 may be 2nm ~ 200nm, preferably 2nm ~ 100nm.

In addition, according to an embodiment, the second oxide layer 152 may include an organometallic vapor deposition method (MOCVD), a molecular beam epitaxial growth method (MBE), a helide vapor deposition method (HVPE), and a plasma-enhanced chemical PECVD. It may be formed based on at least one of vapor deposition, sputtering and atomic layer deposition (ALD).

3 is an exemplary view illustrating various types of recess regions according to an exemplary embodiment disclosed herein.

Referring to FIG. 3, the semiconductor devices 100a to 100c according to the exemplary embodiment disclosed herein may include a substrate 110, a first GaN layer 120 formed on the substrate 110, and a first GaN layer ( An area recessed to the AlGaN layer 130 formed on the 120, the second GaN layer 140 formed on the AlGaN layer 130, the second GaN layer 140, or the AlGaN layer 130. Second oxide layer layers 152a to 152c formed on R110a to R110c, gate electrodes 160 formed on the second oxide layer 152a to 152c, and partial regions of the second GaN layer 140. It may include a source electrode 170 and a drain electrode 180 formed on the first oxide film layer (151a ~ 151c) formed on the second GaN layer 140.

The first oxide layer 151a to 151c may be formed between the source electrode 170 or the drain electrode 180 and the recessed regions R110a to R110c.

That is, the semiconductor devices 100a to 100c may include regions recessed to the second GaN layer 140 or the AlGaN layer 130.

In addition, the recessed region may include at least one of a trench form, a V-groove form, and a semicircle form.

Referring to FIG. 3A, the semiconductor device 110a includes a trench region R110a having a trench shape.

In addition, referring to FIG. 3B, the semiconductor device 110b includes a recess region R110b having a V-groove shape.

In addition, referring to FIG. 3C, the semiconductor device 110c includes a semicircular recessed region R110c.

The In embodiments  Description of manufacturing method of semiconductor device according to

In the method of manufacturing a semiconductor device according to the embodiments disclosed herein, forming a first GaN layer on a substrate, forming an AlGaN layer on the first GaN layer, second GaN on the AlGaN layer Forming a layer, forming a first oxide layer on the second GaN layer, selectively etching the first oxide layer to define a source and drain region, a source electrode on the source and drain region, and Forming a drain electrode, forming a recessed region up to the second GaN layer or the AlGaN layer based on the selective etching, and forming a gate electrode on the recessed region .

In example embodiments, the gate electrode may be in contact with an upper portion of one side of the first oxide layer.

Further, according to one embodiment, forming a gate electrode on the recessed region may include forming a second oxide layer on the recessed region and forming a gate electrode on the second oxide layer. It may include the step of.

According to one embodiment, the second GaN layer is formed by deposition equipment based on organic metal vapor deposition (MOCVD), and the first oxide layer is formed after the formation of the second GaN layer. It may be formed in-situ in the deposition equipment.

In addition, according to an embodiment, the first GaN layer, the AlGaN layer, and the second GaN layer may include an organic metal vapor deposition method (MOCVD), a molecular beam epitaxial growth method (MBE), and a helide vapor deposition method (HVPE). It may be formed based on at least one of plasma-enhanced chemical vapor deposition (PECVD), sputtering, and atomic layer deposition (ALD).

4 is a flowchart illustrating a method of manufacturing a semiconductor device in accordance with embodiments disclosed herein.

Referring to FIG. 4, a method of manufacturing a semiconductor device according to embodiments disclosed herein may be performed by the following steps.

First, a first GaN layer may be formed on a substrate (S110).

Next, an AlGaN layer may be formed on the first GaN layer (S120).

Next, a second GaN layer may be formed on the AlGaN layer (S130).

Next, a first oxide layer may be formed on the second GaN layer (S140).

Next, the source and drain regions may be defined by selectively etching the one oxide layer (S150).

Next, a source electrode and a drain electrode may be formed on the source and drain regions (S160).

Next, a region recessed to the second GaN layer or the AlGaN layer may be formed based on the selective etching (S170).

Next, a gate electrode may be formed on the recessed region (S180).

5A to 5H are exemplary views illustrating a method of manufacturing a semiconductor device in accordance with embodiments disclosed herein.

5A to 5H, a method of fabricating a semiconductor device according to the exemplary embodiments disclosed herein uses an in-situ oxide layer, but normally opens the oxide layer under the gate region. It may be a method of forming a recess structure by etching part or all of the active layer without implementing normally-off.

A detailed process sequence will be described in detail with reference to FIGS. 5A to 5H. First, a gallium nitride thin film (or 1 GaN layer 120) may be grown (or formed) with the MOCVD thin film growth equipment on the substrate 110. (FIG. 5A).

The substrate 110 may be n-type or p-type, and the type of substrate may be Si, SiC, Sapphire, GaN substrate, or the like.

GaN constituting the first GaN layer 120 may be generally manufactured by an organometallic gas phase growth method called MOCVD.

In this case, the first GaN layer 120 may be epitaxially grown by synthesizing Ga 3 , which is a raw material of Ga and NH 3 , which is a raw material of N, at a high temperature in a reactor.

According to one embodiment, the thickness of the n-type GaN may be 1 ~ 10um.

According to another embodiment, a high-resistance GaN layer (or high-resistivity GaN) for preventing leakage current may be grown by using C, Fe, or Mg dopant on n-type GaN.

In this case, the impurity concentration of the dopant may be in the range of 1e 17 / cm 3 to 1e 19 / cm 3 , preferably 1e 17 / cm 3 to 1e 18 / cm 3 .

Next, after the GaN channel layer (or the first GaN layer 120) is grown, the AlGaN layer 130 of the active layer may be grown (FIG. 5B).

According to an embodiment, the thickness of the AlGaN layer 130 may be in the range of 2 nm to 100 nm, preferably 15 nm to 30 nm.

In addition, after the active layer is grown, a GaN cap (or a second GaN layer 140) may be grown to prevent surface leakage current (FIG. 5C).

According to one embodiment, the second GaN layer 140 may be in the range of 0nm to 100nm, preferably 2nm to 10nm.

Next, a first oxide layer 151 may be formed on the second GaN layer 140 (FIG. 5D).

The first oxide layer 151 may be made of various materials. For example, the first oxide layer 151 may be formed of Si x N y .

In this case, Si x N y constituting the first oxide layer 151 may be grown using SiH 4 and NH 3 based on MOCVD equipment.

According to one embodiment, the thickness of the first oxide layer 151 may be in the range of 2nm to 500nm, preferably 5nm to 200nm.

Next, to deposit the source electrode 170 and the drain electrode 180, a portion of the first oxide layer 151 or Si x N y may be opened to deposit an ohmic electrode (FIG. 5E). .

Next, the first oxide layer 151 is opened to form a region under the gate in a recess structure, and the second GaN layer 140 or the active layer (or AlGaN) is dried using a dry etching method. Some or all of the layer 130 may be etched (FIG. 5F), thereby forming a recessed region R110.

Next, a second oxide layer 152 for the MIS structure may be formed on the recessed region R110 (FIG. 5G).

The second oxide layer 152 may be deposited in various ways. For example, the second oxide layer 152 may be deposited using PECVD, Sputter, or ALD.

In addition, according to an embodiment, the second oxide layer 152 may be made of various materials. For example, the second oxide layer 152 may be formed of at least one material of SiO 2 , Si 3 N 4 , HfO 2 , Al 2 O 3 , ZnO, and Ga 2 O 3 .

According to an embodiment, the thickness of the second oxide layer 152 may be 2 nm to 200, and preferably 2 nm to 100 nm.

Finally, a gate electrode may be formed over the second oxide layer 152 and the first oxide layer 151 (FIG. 5H).

Through this, a MIS structure can be made and finally a recessed MIS-HFET device using an in-situ oxide film can be finally completed.

The scope of the present invention is not limited to the embodiments disclosed herein, and the present invention can be modified, changed, or improved in various forms within the scope of the present invention and the claims.

100 semiconductor element 120 first GaN layer
130: AlGaN layer 140: second GaN layer
151: first oxide film layer 152: second oxide film layer
160: gate electrode

Claims (21)

Board;
A first GaN layer formed on the substrate;
An AlGaN layer formed on the first GaN layer;
A second GaN layer formed on the AlGaN layer;
A gate electrode formed on a region recessed to the second GaN layer or the AlGaN layer;
A source electrode and a drain electrode formed on a portion of the second GaN layer; And
Including a first oxide layer formed on the second GaN layer,
The first oxide film layer,
And formed between the source electrode or the drain electrode and the recessed region. The method of claim 1, wherein the first oxide film layer,
A semiconductor device comprising Si x N y . The semiconductor device according to claim 1,
The semiconductor device is in contact with the upper portion of one side of the first oxide film layer. The method of claim 1,
Further comprising a second oxide layer formed on the recessed region,
The gate electrode
The semiconductor device is formed on the second oxide film layer. The method of claim 4, wherein the second oxide film layer,
And at least one of SiO 2 , Si 3 N 4 , HfO 2 , Al 2 O 3 , ZnO, and Ga 2 O 3 . The method of claim 1, wherein the first oxide film layer,
The semiconductor device is formed in-situ after the formation of the second GaN layer. The method according to claim 1 or 4,
The thickness of the first oxide film layer,
1 nm to 500 nm,
The thickness of the second oxide film layer is,
A semiconductor device of 2nm to 200nm. The method according to claim 1 or 4,
The first oxide film layer or the second oxide film layer,
At least one of organic metal vapor deposition (MOCVD), molecular beam epitaxial growth (MBE), helide vapor deposition (HVPE), plasma-enhanced chemical vapor deposition (PECVD), sputtering, and atomic layer deposition (ALD) The semiconductor device is formed based on. The method of claim 1, wherein the depth of the recessed area,
A semiconductor device of 1 nm to 1000 nm. The method of claim 1, wherein the recessed area,
A semiconductor device having at least one of a trench form, a V-groove form and a semicircle form. The method of claim 1, wherein the substrate,
At least one of an insulating substrate, a sapphire substrate, a GaN substrate, a SiC substrate, and a Si substrate. The method of claim 1, wherein the thickness of the first GaN layer is
A semiconductor device of 1um to 10um. The method of claim 1,
And a high-resistance GaN layer formed by implanting at least one dopant of C, Fe, and Mg dopants on the first GaN layer. The method of claim 13, wherein the concentration of the at least one dopant is
1e17 / cm3 to 1e19 / cm3. The method of claim 1, wherein the AlGaN layer,
Wherein the thickness of the semiconductor element is 2 nm to 100 nm. The thickness of the second GaN layer,
And is 2 nm to 10 nm. Forming a first GaN layer on the substrate;
Forming an AlGaN layer on the first GaN layer;
Forming a second GaN layer on the AlGaN layer;
Forming a first oxide layer on the second GaN layer;
Selectively etching the first oxide layer to define a source and a drain region;
Forming a source electrode and a drain electrode on the source and drain regions;
Forming a recessed region up to the second GaN layer or the AlGaN layer based on the selective etching; And
Forming a gate electrode on the recessed region. The method of claim 17, wherein the gate electrode,
The semiconductor device is in contact with the upper portion of one side of the first oxide film layer. The method of claim 17, wherein forming a gate electrode on the recessed region comprises:
Forming a second oxide layer on the recessed region; And
Forming a gate electrode on the second oxide layer. The method of claim 17, wherein the second GaN layer,
Formed by deposition equipment based on organometallic vapor deposition (MOCVD),
The first oxide film layer,
And forming the second GaN layer in-situ in the deposition apparatus. 18. The method of claim 17,
The first GaN layer, the AlGaN layer and the second GaN layer,
At least one of organic metal vapor deposition (MOCVD), molecular beam epitaxial growth (MBE), helide vapor deposition (HVPE), plasma-enhanced chemical vapor deposition (PECVD), sputtering, and atomic layer deposition (ALD) The semiconductor device is formed based on.
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