KR20120032908A - Light emitting device package - Google Patents

Light emitting device package Download PDF

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Publication number
KR20120032908A
KR20120032908A KR1020100094467A KR20100094467A KR20120032908A KR 20120032908 A KR20120032908 A KR 20120032908A KR 1020100094467 A KR1020100094467 A KR 1020100094467A KR 20100094467 A KR20100094467 A KR 20100094467A KR 20120032908 A KR20120032908 A KR 20120032908A
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South Korea
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light emitting
emitting device
lead frame
device chip
wire
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KR1020100094467A
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Korean (ko)
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최선
최설영
최기원
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삼성엘이디 주식회사
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Priority to KR1020100094467A priority Critical patent/KR20120032908A/en
Publication of KR20120032908A publication Critical patent/KR20120032908A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45139—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item

Abstract

PURPOSE: A light emitting device package is provided to reduce the installation area of a light emitting diode chip by arranging a Zener diode on a lead frame in which the light emitting diode is arranged. CONSTITUTION: A first lead frame(210) is located adjacent to a second lead frame(220). A light emitting device chip(230) and a Zener diode(240) are arranged on the first lead frame. A first wire(242) connects the upper surface of the light emitting chip and the second lead frame. A second wire(234) connects the upper surface of the light emitting device chip and the Zener diode. The first wire and the second wire are respectively connected to a pad(235) which is formed on the upper surface of the light emitting device chip.

Description

발광소자 패키지{Light emitting device package}A light emitting device package

본 개시는 제너 다이오드가 발광소자칩과 동일한 리드프레임에 배치된 발광소자 패키지에 관한 것이다. The present disclosure relates to a light emitting device package in which a Zener diode is disposed in the same lead frame as a light emitting device chip.

발광다이오드(Light Emitting Diode; LED)는 화합물 반도체(compound semiconductor)의 PN접합을 통해 발광원을 구성함으로써, 다양한 색의 광을 구현할 수 있는 반도체 소자를 말한다. 이러한 LED는 수명이 길고, 소형화 및 경량화가 가능하며, 광의 지향성이 강하여 저전압 구동이 가능하다는 장점이 있다. 또한, 이러한 LED는 충격 및 진동에 강하고, 예열시간과 복잡한 구동이 불필요하며, 다양한 형태로 패키징할 수 있어, 여러가지 용도로 적용이 가능하다. A light emitting diode (LED) refers to a semiconductor device capable of realizing various colors of light by forming a light emitting source through a PN junction of a compound semiconductor. These LEDs have a long life, can be miniaturized and lightweight, and has a strong directivity of light, thereby enabling low voltage driving. In addition, the LED is resistant to shock and vibration, does not require preheating time and complicated driving, and can be packaged in various forms, and thus it can be applied to various applications.

발광소자 패키지는 LED와 같은 발광소자칩을 형광체와 렌즈 등과 함께 리드 프레임 등에 실장하여 제작된다. The light emitting device package is manufactured by mounting a light emitting device chip such as an LED together with a phosphor and a lens in a lead frame.

발광 다이오드와 함께 사용되는 제너 다이오드(Zener diode)는 발광 다이오드와 병렬로 연결되어서 발광 다이오드에 역방향으로 인가되는 전류를 바이패스시켜서 발광 다이오드의 손상을 방지한다. A zener diode used together with the light emitting diode is connected in parallel with the light emitting diode to bypass current applied to the light emitting diode in a reverse direction to prevent damage to the light emitting diode.

제너 다이오드는 일반적으로 발광 다이오드와 다른 극성의 리드프레임에 배치되므로, 제너 다이오드를 발광 다이오드와 함께 실장시 발광 다이오드 칩의 실장 면적이 증가되므로 컴팩트한 발광소자의 구현에 장애가 될 수 있다. Since the Zener diode is generally disposed in a lead frame having a different polarity from that of the light emitting diode, when the Zener diode is mounted together with the light emitting diode, the mounting area of the LED chip increases, which may impede the implementation of a compact light emitting device.

제너 다이오드를 발광 다이오드와 동일한 리드프레임에 배치함으로써 발광 다이오드 칩의 실장 면적을 감소시킨 발광소자 패키지를 제공한다. A zener diode is disposed in the same lead frame as a light emitting diode, thereby providing a light emitting device package having a reduced mounting area of the light emitting diode chip.

일 실시예에 따른 발광소자 패키지는: 서로 인접되게 배치된 제1 리드프레임 및 제2 리드프레임; 및A light emitting device package according to an embodiment includes: a first lead frame and a second lead frame disposed adjacent to each other; And

상기 제1 리드프레임에 함께 배치된 발광소자칩 및 제너 다이오드;를 구비한다. And a light emitting device chip and a zener diode disposed together in the first lead frame.

상기 실시예에 따른 발광소자 패키지는, 상기 발광소자칩의 상면과 상기 제2 리드프레임을 연결되는 제1 와이어와, The light emitting device package according to the embodiment includes: a first wire connecting the upper surface of the light emitting device chip and the second lead frame;

상기 발광소자칩의 상면과 상기 제너 다이오드를 연결하는 제2 와이어를 더 구비한다. And a second wire connecting the upper surface of the light emitting device chip to the zener diode.

상기 제1 와이어와 상기 제2 와이어는 상기 발광소자칩의 상면에 형성된 패드에 각각 연결될 수 있다. The first wire and the second wire may be connected to pads formed on an upper surface of the light emitting device chip, respectively.

상기 제1 리드프레임은 상기 제2 리드프레임 보다 차지하는 영역이 더 크며, 상기 발광소자칩은 상기 제1 리드프레임과 상기 제2 리드프레임이 형성하는 평면에서 실질적으로 중앙부에 배치될 수 있다. The first lead frame may have a larger area than the second lead frame, and the light emitting device chip may be substantially disposed at a center portion in a plane formed by the first lead frame and the second lead frame.

상기 실시예에 따른 발광소자 패키지는, 상기 제1 및 제2 리드프레임의 일측을 수용하고 내부에 캐버티가 형성되는 패키지 몰드; 및The light emitting device package according to the embodiment may include a package mold accommodating one side of the first and second lead frames and having a cavity formed therein; And

상기 캐비티를 채워서 상기 발광소자칩과 상기 제너 다이오드를 보호하는 몰딩재;를 더 구비할 수 있다. And a molding material filling the cavity to protect the light emitting device chip and the zener diode.

개시된 실시예들에 따르면, 발광소자칩 및 제너다이오드가 동일한 리드프레임에 배치되어서 패키지 실장면적이 감소되어 실장면적당 발광효율이 향상된다. According to the disclosed embodiments, the light emitting device chip and the zener diode are disposed in the same lead frame, thereby reducing the package mounting area, thereby improving luminous efficiency per mounting area.

또한, 발광소자칩을 패키지의 중앙에 배치함으로써 광추출 효율이 향상된다. In addition, the light extraction efficiency is improved by arranging the light emitting device chip in the center of the package.

또한, 제너 다이오드를 별도의 리드프레임에 직접 연결하지 않고 발광소자칩의 상면에 연결함으로써 와이어 길이를 줄일 수 있어 와이어 손상을 줄일 수 있다. In addition, the wire length can be reduced by connecting the zener diode to the upper surface of the light emitting device chip without directly connecting to a separate lead frame, thereby reducing wire damage.

도 1은 본 발명의 일 실시예에 따른 발광소자 패키지의 개략적인 단면도이다.
도 2는 도 1의 평면도이다.
도 3은 본 발명의 다른 실시예에 따른 발광소자 패키지의 개략적 평면도이다. 1 is a schematic cross-sectional view of a light emitting device package according to an embodiment of the present invention.
2 is a plan view of Fig.
3 is a schematic plan view of a light emitting device package according to another embodiment of the present invention.

이하, 첨부된 도면을 참조하여 본 발명의 실시예를 상세하게 설명한다. 이 과정에서 도면에 도시된 층이나 영역들의 두께는 명세서의 명확성을 위해 과장되게 도시된 것이다. 명세서를 통하여 실질적으로 동일한 구성요소에는 동일한 참조번호를 사용하고 상세한 설명은 생략한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In this process, the thicknesses of layers or regions illustrated in the drawings are exaggerated for clarity. Throughout the specification, the same reference numerals are used for substantially the same components, and detailed descriptions thereof will be omitted.

도 1은 본 발명의 일 실시예에 따른 발광소자 패키지(100)의 개략적인 단면도이며, 도 2는 도 1의 평면도이다. 도 2에서는 편의상 패키지 몰드 및 몰딩재를 제외하였다. 1 is a schematic cross-sectional view of a light emitting device package 100 according to an embodiment of the present invention, Figure 2 is a plan view of FIG. In FIG. 2, the package mold and the molding material are excluded for convenience.

도 1 및 도 2를 참조하면, 발광소자 패키지(100)는 서로 인접하게 배치된 제1 리드프레임(110)과 제2 리드프레임(120)을 구비한다. 제1 리드프레임(110)은 제2 리드프레임(120)에 비해 더 길게 형성된다. 제1 리드프레임(110) 상에는 발광소자칩(130) 및 제너 다이오드(140)가 배치된다. 발광소자칩(130)은 일반적인 GaN 계열의 광다이오드일 수 있으며, 상세한 설명은 생략한다. 1 and 2, the light emitting device package 100 includes a first lead frame 110 and a second lead frame 120 disposed adjacent to each other. The first lead frame 110 is formed longer than the second lead frame 120. The light emitting device chip 130 and the zener diode 140 are disposed on the first lead frame 110. The light emitting device chip 130 may be a general GaN-based photodiode, and a detailed description thereof will be omitted.

발광소자 패키지(100)는 리드프레임들(110, 120)의 일측을 수용하고 내부에 캐버티를 형성하는 패키지 몰드(150)와, 패키지 몰드(150)의 캐버티를 채운 몰딩재(16)을 더 구비한다. The light emitting device package 100 includes a package mold 150 accommodating one side of the lead frames 110 and 120 and forming a cavity therein, and a molding material 16 filling the cavity of the package mold 150. It is further provided.

발광소자칩(130)은 P 극 및 N 전극이 그 상부면에 각각 형성된 수평형 구조일 수 있다. 발광소자칩(130)의 두 전극은 각각 와어어(132, 134)를 통해서 제1 리드프레임(110) 및 제2 리드프레임(120)에 연결된다. The light emitting device chip 130 may have a horizontal structure in which P electrodes and N electrodes are formed on upper surfaces thereof. Two electrodes of the light emitting device chip 130 are connected to the first lead frame 110 and the second lead frame 120 through wires 132 and 134, respectively.

제너 다이오드(140)는 하부의 제1 리드프레임(110)과, 그리고 와이어(142)를 통해서 제2 리드프레임(120)과 전기적으로 연결되어서 발광소자칩(130)에 역방향으로 전류가 인입되는 경우, 제너 다이오드(140)에 의해 전류가 바이패스(bypass)되며, 따라서 발광소자칩(130)의 손상을 방지한다. 제너 다이오드(140)는 실리콘 등으로 형성될 수 있다. The Zener diode 140 is electrically connected to the second lead frame 120 through the first lead frame 110 and the wire 142 at the bottom, so that current flows in the reverse direction to the light emitting device chip 130. In addition, current is bypassed by the zener diode 140, thereby preventing damage to the light emitting device chip 130. The zener diode 140 may be formed of silicon or the like.

와이어들(132, 134, 142)은 금(Au) 또는 구리(Cu) 등으로 이루어질 수 있다. The wires 132, 134, and 142 may be made of gold (Au), copper (Cu), or the like.

패키지 몰드(150)는 PPA (polyphtalamide) 수지 등으로 사출성형으로 형성될 수 있다. The package mold 150 may be formed by injection molding using PPA (polyphtalamide) resin or the like.

몰딩재(160)는 캐버티 내의 발광소자칩(130)과 제너 다이오드(140)를 보호한다. 몰딩재(160)는 투광성이 양호한 실리콘 수지 또는 에폭시 수지 등으로 형성될 수 있다. 몰딩재(160)에는 형광체가 수지와 함께 혼합될 수 있다. 발광소자칩(130)으로부터의 특정 광파장이 형광체에 흡수되어서 원하는 다른 파장의 광으로 변환될 수 있다. The molding material 160 protects the light emitting device chip 130 and the zener diode 140 in the cavity. The molding material 160 may be formed of a silicone resin or an epoxy resin having good light transmittance. The phosphor 160 may be mixed with the resin in the molding material 160. A specific light wavelength from the light emitting device chip 130 may be absorbed by the phosphor and converted into light of a desired other wavelength.

상기 실시예에서는 수평형 발광소자칩(130)을 사용하였으나 본 발명은 반드시 이에 한정되지 않는다. 예컨대 수직형 발광소자칩을 사용하는 경우, 제1 리드프레임(110)과 연결되는 와이어(132)를 사용하지 않는다. In the above embodiment, the horizontal light emitting device chip 130 is used, but the present invention is not limited thereto. For example, when using a vertical light emitting device chip, the wire 132 connected to the first lead frame 110 is not used.

상기 실시예에 따른 발광소자 패키지는 제너 다이오드(140)가 발광소자칩(130)과 동일한 제1 리드프레임(110)에 실장되므로, 제2 리드프레임(120)의 면적을 줄일 수 있으며, 이는 소형 패키지의 제조를 가능하게 하며, 발광소자 패키지의 면적당 광효율을 향상시킨다. In the light emitting device package according to the embodiment, since the zener diode 140 is mounted on the same first lead frame 110 as the light emitting device chip 130, the area of the second lead frame 120 can be reduced, which is small. It is possible to manufacture the package, and improve the light efficiency per area of the light emitting device package.

도 3은 본 발명의 다른 실시예에 따른 발광소자 패키지(200)의 평면도이다. 도 3에서는 편의상 패키지 몰드 및 몰딩재를 제외하였다. 도 1 및 도 2와 실질적으로 동일한 구성요소에는 동일한 명칭을 사용하고 상세한 설명은 생략한다. 3 is a plan view of a light emitting device package 200 according to another embodiment of the present invention. In FIG. 3, the package mold and the molding material are excluded for convenience. Components that are substantially the same as those in FIGS. 1 and 2 have the same names, and detailed descriptions are omitted.

도 3을 참조하면, 발광소자칩(230)이 제1 리드프레임(210)과 제2 리드프레임(220)이 형성하는 평면상에서, 중앙에 배치된다. 즉, 제1 리드프레임(210) 상에서 제2 리드프레임(220) 측으로 치우쳐 배치된다. 발광소자칩(230)은 실질적으로 패키지 몰드(도 1의 150)에 의해 형성된 캐버티의 중앙부에 형성된다. 발광소자칩(230)은 수평형 발광소자일 수 있다. 발광소자칩(230)은 와이어(232)에 의해서 제1 리드프레임(210)과 연결되며, 와이어(234)를 통해서 제2 리드프레임(220)과 연결된다. 제너 다이오드(240)를 제2 리드프레임(220)에 연결하는 와이어(242)가 발광소자칩(230)의 상면상의 패드(235)에서 와이어(234)와 함께 연결된다. Referring to FIG. 3, the light emitting device chip 230 is disposed at the center on a plane formed by the first lead frame 210 and the second lead frame 220. That is, the first lead frame 210 is disposed biased toward the second lead frame 220 side. The light emitting device chip 230 is formed in a central portion of the cavity formed by the package mold (150 in FIG. 1). The light emitting device chip 230 may be a horizontal light emitting device. The light emitting device chip 230 is connected to the first lead frame 210 by a wire 232, and is connected to the second lead frame 220 through a wire 234. The wire 242 connecting the zener diode 240 to the second lead frame 220 is connected together with the wire 234 on the pad 235 on the upper surface of the light emitting device chip 230.

도 1의 패키지 몰드(150) 및 몰딩재(160)도 도 3의 발광소자 패키지(200)에 적용되며, 상세한 설명은 생략한다. The package mold 150 and the molding material 160 of FIG. 1 are also applied to the light emitting device package 200 of FIG. 3, and a detailed description thereof will be omitted.

다른 실시예에 따른 발광소자 패키지(200)는 발광소자칩(230)이 패키지의 중앙부에 배치됨으로써 광추출효율이 향상되며, 소형 패키지의 제조를 용이하게 한다. In the light emitting device package 200 according to another exemplary embodiment, since the light emitting device chip 230 is disposed at the center of the package, light extraction efficiency is improved, and the manufacture of a small package is facilitated.

또한, 제너 다이오드(240)의 와이어(242)의 길이가 감소되므로, 제조비용 측면에서 유리하며, 또한, 와이어의 길이 감소로 와이어 손상을 줄일 수 있다. In addition, since the length of the wire 242 of the zener diode 240 is reduced, it is advantageous in terms of manufacturing cost, and the wire damage can be reduced by reducing the length of the wire.

이상에서 첨부된 도면을 참조하여 설명된 본 발명의 실시예들은 예시적인 것에 불과하며, 당해 분야에서 통상의 지식을 가진 자라면 이로부터 다양한 변형 및 균등한 타 실시예가 가능함을 이해할 수 있을 것이다. 따라서 본 발명의 진정한 보호범위는 첨부된 특허청구범위에 의해서만 정해져야 할 것이다.While the invention has been shown and described with reference to certain embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the scope of the invention as defined by the appended claims. Therefore, the true scope of protection of the present invention should be defined only by the appended claims.

Claims (6)

서로 인접되게 배치된 제1 리드프레임 및 제2 리드프레임; 및
상기 제1 리드프레임에 함께 배치된 발광소자칩 및 제너 다이오드;를 구비한 발광소자 패키지. A first lead frame and a second lead frame disposed adjacent to each other; And
A light emitting device package comprising: a light emitting device chip and a zener diode disposed together in the first lead frame. 제 1 항에 있어서,
상기 발광소자칩의 상면과 상기 제2 리드프레임을 연결되는 제1 와이어와,
상기 발광소자칩의 상면과 상기 제너 다이오드를 연결하는 제2 와이어를 구비한 발광소자 패키지. The method of claim 1,
A first wire connecting the upper surface of the light emitting device chip to the second lead frame;
And a second wire connecting the top surface of the light emitting device chip to the zener diode. 제 2 항에 있어서,
상기 제1 와이어와 상기 제2 와이어는 상기 발광소자칩의 상면에 형성된 패드에 각각 연결된 발광소자 패키지.The method of claim 2,
The first wire and the second wire is a light emitting device package each connected to a pad formed on the upper surface of the light emitting device chip. 제 1 항에 있어서,
상기 제1 리드프레임은 상기 제2 리드프레임 보다 차지하는 영역이 더 큰 발광소자 패키지.The method of claim 1,
The first lead frame has a larger area occupied by the second lead frame. 제 4 항에 있어서,
상기 발광소자칩은 상기 제1 리드프레임과 상기 제2 리드프레임이 형성하는 평면에서 실질적으로 중앙부에 배치된 발광소자 패키지.The method of claim 4, wherein
The light emitting device chip is disposed in the center portion substantially in the plane formed by the first lead frame and the second lead frame. 제 1 항에 있어서,
상기 제1 및 제2 리드프레임의 일측을 수용하고 내부에 캐버티가 형성되는 패키지 몰드; 및
상기 캐비티를 채워서 상기 발광소자칩과 상기 제너 다이오드를 보호하는 몰딩재;를 더 구비하는 발광소자 패키지. The method of claim 1,
A package mold accommodating one side of the first and second lead frames and having a cavity formed therein; And
And a molding material filling the cavity to protect the light emitting device chip and the zener diode.
KR1020100094467A 2010-09-29 2010-09-29 Light emitting device package KR20120032908A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10236280B2 (en) 2017-07-12 2019-03-19 Samsung Electronics Co., Ltd. Light emitting device package and display device using the same
CN109860165A (en) * 2018-12-29 2019-06-07 广东晶科电子股份有限公司 A kind of LED component and preparation method thereof
JP2021052143A (en) * 2019-09-26 2021-04-01 ローム株式会社 Semiconductor light emitting device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10236280B2 (en) 2017-07-12 2019-03-19 Samsung Electronics Co., Ltd. Light emitting device package and display device using the same
CN109860165A (en) * 2018-12-29 2019-06-07 广东晶科电子股份有限公司 A kind of LED component and preparation method thereof
JP2021052143A (en) * 2019-09-26 2021-04-01 ローム株式会社 Semiconductor light emitting device

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