KR20110075696A - Deposition method for trench area of semiconductor device - Google Patents
Deposition method for trench area of semiconductor device Download PDFInfo
- Publication number
- KR20110075696A KR20110075696A KR1020090132217A KR20090132217A KR20110075696A KR 20110075696 A KR20110075696 A KR 20110075696A KR 1020090132217 A KR1020090132217 A KR 1020090132217A KR 20090132217 A KR20090132217 A KR 20090132217A KR 20110075696 A KR20110075696 A KR 20110075696A
- Authority
- KR
- South Korea
- Prior art keywords
- semiconductor device
- deposition
- trench
- teos
- etching
- Prior art date
Links
- 238000000151 deposition Methods 0.000 title claims abstract description 48
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000000034 method Methods 0.000 claims abstract description 34
- 230000008021 deposition Effects 0.000 claims abstract description 23
- 238000004544 sputter deposition Methods 0.000 claims abstract description 11
- 239000002184 metal Substances 0.000 claims abstract description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 20
- 238000005530 etching Methods 0.000 claims description 11
- 239000011800 void material Substances 0.000 abstract description 4
- 239000010408 film Substances 0.000 description 28
- 239000007789 gas Substances 0.000 description 5
- 238000000992 sputter etching Methods 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 239000012705 liquid precursor Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
The present invention relates to a method for depositing a dielectric film of a semiconductor device, and more particularly, to a method of depositing a dielectric film so that voids do not occur in a trench region having a high aspect ratio by using chemical vapor deposition (CVD).
As semiconductor devices become more integrated, the importance of gap-filling and insulating dielectric films in trench regions is increasing in the manufacturing process of semiconductor devices. In particular, it is difficult to uniformly deposit a dielectric film because a gap formed in a high aspect ratio trench region causes pinch off and void.
In order to fill a large aspect ratio gap, the gap fill method through the deposition-wet etching-deposition (DWD) method of repeatedly performing high density plasma chemical vapor deposit (HDPCVD) deposition and wet etching has been used.
In general, the DWD method is to remove an overhang through wet etching after a trench gap fill through HDPCVD and to deposit a dielectric film by HDPCVD. Therefore, in general, the DWD method can improve the gap fill performance by repeatedly performing deposition and wet etching by HDPCVD.
However, in the case of applying the DWD method, there is no problem in the gap fill of the trench region having a straight slope, but there is a problem in that voids occur in the gap fill of the trench having an irregular or inverse slope profile.
1 is a cross-sectional view of a semiconductor device showing a cross section of a PMD (Preferential Metal Deposition) of a cell region of a general flash memory.
Referring to FIG. 1, there is a
In addition, the
SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an object thereof is to provide a method for depositing a trench region having a high aspect ratio with a dielectric film without voids by using a deposition-sputtering etch-deposition (DSD) method.
Dielectric film deposition method of a semiconductor device according to the present invention for realizing the object as described above, the first deposition step of depositing an oxide film on top of the semiconductor device is formed with a lower metal wiring and trench structure; Etching to remove an overhang on the trench structure; And a second deposition step of depositing and planarizing an oxide film on the semiconductor device.
In addition, the first deposition step and the second deposition step is characterized in that carried out in O 3 TEOS method.
In addition, the etching step is characterized in that carried out by a sputtering method using O 2 and Ar.
According to the dielectric film deposition method of the present invention, a trench region having a high aspect ratio can be deposited without a void by using a deposition-sputtering etch deposition (DSD) method.
Hereinafter, with reference to the accompanying drawings will be described in detail the configuration and operation of the preferred embodiment of the present invention.
The trench region gapfill method of the present invention is characterized by using a Deposition-Sputtering Etch-Deposition (DSD) method instead of the conventional DWD method.
Specifically, the dielectric film deposition method according to the present invention is a dielectric film deposition method of a semiconductor device including a trench structure, the first deposition step by O 3 TEOS method; Sputter etching using O 2 and Ar gas; And a second deposition step by O 3 TEOS method.
The biggest difference between the conventional DWD method and the DSD method of the present invention is that the O 3 TEOS method is used instead of the HDP method during deposition.
In general, the O 3 TEOS method is a method in which ozone causes a TEOS reaction with tetraesolosilicate or tetraesolesilane to deposit an oxide film. TEOS is an organic liquid precursor. In addition, a carrier gas such as nitrogen may be used to transport the TEOS mixed gas. Ozone is very reactive and does not require plasma. The reaction formula of TEOS and ozone is as follows.
Si (C 2 H 5 O 4 ) + 8O 3 → SiO 2 + 10H 2 O + 8CO 2
In addition, the advantage of the O 3 TEOS method is that the dielectric film is uniformly deposited along the curvature even when the curved profile is deposited because the step coverage is good.
Referring to FIG. 2, even when the
In addition, the O 3 TEOS film can be uniformly deposited along the profile of the overhang even when the
Unlike the conventional DWD method, the present invention is characterized in that the sputter etching is performed after depositing the O 3 TEOS film. In the case of using conventional wet etching, there is a problem that a desired profile cannot be obtained due to the isotropic etching characteristic.
Accordingly, the present invention uses sputtering etching that exhibits anisotropic etching characteristics in order to obtain a desired profile. For example, when sputtering etching using O 2 and Ar gas is performed, the overhang region of the upper portion is etched at an angle of 45 °.
As a result, according to the present invention, the gapfill performance of the trench region can be improved by eliminating an overhang that is a problem when the gap region of the trench region is filled.
Next, according to the present invention, after the sputtering etching, the gap fill is completed by depositing and planarizing the O 3 TEOS film again.
When the sputter etching is completed, the aspect ratio increases as the trench region is etched downward. Unlike the conventional HDP method, the present invention solves the gap fill problem by depositing O 3 TEOS film again. .
4 is a cross-sectional view of a semiconductor device having completed deposition and planarization of a dielectric film.
As described above, the gapfill method of the trench structure according to the present invention includes a first deposition step of depositing an O 3 TEOS film, an etching step of etching sputtering using O 2 and Ar gas, and a second deposition of depositing an O 3 TEOS film A step is made.
In addition, the present invention may deposit other films other than the O 3 TEOS film in the first deposition step or the second deposition step, if necessary.
The present invention is not limited to the above-described embodiments, and various modifications and changes can be made without departing from the technical spirit of the present invention, which will be apparent to those of ordinary skill in the art. It is.
1 is a cross-sectional view of a semiconductor device in which a trench structure is formed;
2 is a cross-sectional view of a semiconductor device in which a first deposition is completed, in which an oxide film is deposited by using an O 3 TEOS method;
3 is a cross-sectional view of a semiconductor device in which sputter etching is completed using O 2 and Ar gases;
4 is a cross-sectional view of a semiconductor device in which a first deposition is completed in which an oxide film is deposited by using an O 3 TEOS method.
* Description of the symbols for the main parts of the drawings *
1: trench area
2: overhang
10: semiconductor device
20, 20a: dielectric film
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020090132217A KR20110075696A (en) | 2009-12-28 | 2009-12-28 | Deposition method for trench area of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020090132217A KR20110075696A (en) | 2009-12-28 | 2009-12-28 | Deposition method for trench area of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20110075696A true KR20110075696A (en) | 2011-07-06 |
Family
ID=44915662
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020090132217A KR20110075696A (en) | 2009-12-28 | 2009-12-28 | Deposition method for trench area of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20110075696A (en) |
-
2009
- 2009-12-28 KR KR1020090132217A patent/KR20110075696A/en not_active Application Discontinuation
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