KR20110065753A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
KR20110065753A
KR20110065753A KR1020090122393A KR20090122393A KR20110065753A KR 20110065753 A KR20110065753 A KR 20110065753A KR 1020090122393 A KR1020090122393 A KR 1020090122393A KR 20090122393 A KR20090122393 A KR 20090122393A KR 20110065753 A KR20110065753 A KR 20110065753A
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KR
South Korea
Prior art keywords
pattern
fuse
insulating film
forming
contact plug
Prior art date
Application number
KR1020090122393A
Other languages
Korean (ko)
Inventor
장경식
Original Assignee
주식회사 하이닉스반도체
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Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020090122393A priority Critical patent/KR20110065753A/en
Publication of KR20110065753A publication Critical patent/KR20110065753A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to prevent the occurrence of highly accelerated street test failures by reducing the size of fuse patterns in a flues blowing region. CONSTITUTION: A first insulating film(320) is formed on a semiconductor substrate(300). A buffer film(330) is formed on the upper side of the first insulating film. A second insulating film(340) is formed on the front side of the first insulating film including the buffer film. The second insulating film and the first insulating film are etched, and a conductive film is buried to form a contact plug(350). A fuse pattern in which a part thereof overlaps with the contact plug is formed.

Description

Method for Manufacturing Semiconductor Device {Method for Manufacturing Semiconductor Device}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a technique for improving a failure of a highly accelerated stress test (HAST) failure caused by a fuse residue during a repair process of a fuse.

In recent years, with the rapid spread of information media such as computers, semiconductor devices are also rapidly developing. In terms of its function, the semiconductor device is required to operate at a high speed and to have a large storage capacity. Accordingly, the manufacturing technology of semiconductor devices has been developed to improve the degree of integration, reliability, and response speed.

The semiconductor device mainly includes a fabrication (FAB) process of repeatedly forming a circuit pattern set on a silicon substrate to form cells having an integrated circuit, and packaging the substrate on which the cells are formed in a chip unit. Packaging and assembly process. In addition, a process for inspecting electrical characteristics of cells formed on the substrate is performed between the fabrication process and the assembly process.

The inspection step is a step of determining whether the cells formed on the substrate have an electrically good state or a bad state. By removing the cells having a defective state before performing the assembly process through the inspection process, it is possible to reduce the effort and cost consumed in the assembly process. In addition, the cells having the defective state can be found early and can be reproduced through a repair process.

Here, the repair process will be described in more detail as follows.

Redundancy cells are added to replace defective devices or circuits in the design of devices for the purpose of improving the yield of devices in the event of a defect in the semiconductor device manufacturing process, and connecting such redundant cells to the integrated circuit. In order to design a fuse together, the repair process is a process in which a cell, which has been found to be defective through an inspection process, is connected to a spare cell embedded in a chip using the fuse to be regenerated. That is, by cutting only specific fuses, location information of cells to be repaired is generated.

Hereinafter, a repair method of a semiconductor device according to the prior art will be briefly described.

First, an interlayer insulating film having a flattened surface is deposited on a fuse area of a semiconductor substrate, and then a plurality of fuse patterns are formed on the insulating interlayer. Next, an insulating film is deposited on the resultant of the semiconductor substrate to cover the fuse patterns. Subsequently, a partial thickness of the insulating layer is repaired and etched to form a repair trench for leaving an insulating layer having a predetermined thickness on the blowing area, that is, the fuse pattern.

Thereafter, a known inspection and repair process including a fuse blowing process of cutting a specific fuse by irradiating a laser to the fuse region of the semiconductor substrate is sequentially performed.

Here, after forming a repair trench for leaving an insulating film having a predetermined thickness on the fuse pattern, a fuse blowing process is performed. At this time, if the thickness of the insulating film remaining on the fuse pattern is thick, when the fuse blows by the e-beam, the thermal energy is concentrated in the fuse, and when the critical point is reached, the explosion explodes upward. If the fuse is to be disconnected while the thickness of the insulating film is thick, the bottom crack (Crack) occurs before the explosion occurs to the upper metal residue (Residue) is generated in the crack causing the failure. On the contrary, when the thickness of the insulating film remaining on the fuse pattern is thin, thermal energy should be focused on the fuse, but heat energy is exposed and dissipated in the air, thereby causing a blown fuse.

In order to improve this, a metal bare fuse which does not need to adjust the thickness of the insulating film remaining on the fuse pattern has been introduced. However, these metal bare fuses also have a metal residue when blowing using a laser to cause a fuse failure. In addition, since both the top and sidewalls of the metal bare fuse are exposed, oxygen or moisture penetrates the exposed fuse during a subsequent process (wafer package process), thereby causing volume expansion and oxidation of the fuse. As a result, there is a problem that the yield of the semiconductor device is reduced.

1 is a plan view illustrating a method of manufacturing a semiconductor device according to the prior art, (i) is a view before a cutting process of a fuse, and (ii) is a view after a cutting process of a fuse.

1, a conductive pattern 110 formed on a semiconductor substrate 100, a contact plug 130 connected to the conductive pattern 110, and a copper (Cu) pattern 140 connected to the contact plug 130. It is shown. Here, the remaining copper (Cu) pattern 145 or the residue after blowing in the blowing area (region A) of the copper (Cu) pattern 140 due to high temperature and high humidity during the HAST test process during the subsequent process The copper (Cu) pattern 145 is oxidized to cause a defect of the semiconductor device. (A 'region)

2A and 2B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art, in which FIG. 2A is a view before a cutting process of a fuse and FIG. 2B is a view after a cutting process of a fuse.

2A and 2B, a conductive layer (not shown) is formed on the semiconductor substrate 100.

After the photosensitive film is formed on the conductive layer, a photosensitive film pattern (not shown) is formed by an exposure and development process using a conductive pattern mask. The conductive layer is etched using the photoresist pattern as a mask to form a conductive pattern 110. In this case, the conductive pattern 110 is one of the lower layers.

The first insulating layer 120 is formed on the entire surface including the lower layer 110.

Next, after forming a photoresist film on the first insulating film 120, a photoresist pattern (not shown) is formed by an exposure and development process using a contact plug mask. Using the photoresist pattern as a mask, the first insulating layer 120 is etched until the lower layer 110 is exposed to form a contact plug region (not shown). The conductive layer is filled in the contact plug region to form the contact plug 130.

Next, after the copper layer (not shown) is formed on the entire surface including the contact plug 130, the copper layer is etched to form a copper (Cu) pattern 140 connected to the contact plug 130. In this case, the copper (Cu) pattern 140 is preferably in the form of a pad.

After the third insulating layer 150 is formed on the entire surface including the copper pattern 140, planar etching is performed until the copper pattern 140 is exposed.

Next, after the capping nitride layer 160 is formed on the entire surface including the copper pattern 140, a predetermined region of the copper pattern 140 is laser blown 170.

Subsequently, after laser blowing a predetermined region of the copper pattern 140, a residue of the copper pattern remains. This is a problem that the copper pattern 145 is oxidized due to the high temperature and high humidity conditions during the HAST test process during the subsequent process, thereby causing a defect of the semiconductor device.

In order to solve the above-mentioned conventional problems, the present invention is to reduce the size of the fuse pattern of the fuse blowing area, the failure of the HAST (Highly Accelerated Stress Test) fail caused by the residue of the remaining fuse pattern after the fuse blowing Of the semiconductor device to prevent a defect in which the lower layer is damaged by thermal energy by depositing a buffer insulating layer so as not to transfer thermal energy to the lower layer during blowing of the fuse pattern. It provides a manufacturing method.

The present invention includes forming a first insulating film on a semiconductor substrate, forming a buffer film on the first insulating film, forming a second insulating film on the entire surface including the buffer film, the second and the second film. 1. After fabricating the insulating layer, embedding a conductive layer to form a contact plug, forming a fuse pattern partially overlapping the contact plug, and blowing the fuse pattern. Provide a method.

Preferably, the fuse pattern is formed of copper (Cu).

Preferably, after the forming of the fuse pattern, the third insulating film is formed, and further includes a planarization etching process until the fuse pattern is exposed.

The method may further include forming a capping nitride layer after the planarization etching process.

Preferably, the fuse pattern is formed to partially overlap the contact plug between the contact plugs.

Preferably, the fuse pattern is formed smaller than the blowing scheduled region.

Preferably, the method may further include forming a conductive pattern between the semiconductor substrate and the first insulating layer.

Preferably, the contact plug overlaps the buffer layer and the conductive pattern with a partial region.

Preferably, after the forming of the fuse pattern, blowing the fuse pattern.

The present invention is to reduce the size of the fuse pattern of the fuse blowing area to prevent the failure of the HAST (Highly Accelerated Stress Test) fail caused by the residue of the remaining fuse pattern after the fuse blowing, and the blowing of the fuse pattern By depositing a buffer insulating layer so as not to transfer the thermal energy to the lower layer during blowing, there is an advantage to prevent a defect that the lower layer is damaged by the thermal energy.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a plan view illustrating a method of manufacturing a semiconductor device according to the present invention, (i) is a view before a cutting process of a fuse, and (ii) is a view after a cutting process of a fuse.

Referring to FIG. 3, a conductive pattern 310 formed on the semiconductor substrate 300 and a contact plug 350 connected to the conductive pattern 310 are formed, but the damage of the contact plug 350 and the lower layer is prevented. A copper (Cu) pattern 360 connected to the buffer layer 330 and the contact plug 350 is illustrated. Here, the copper pattern 360 is formed to be smaller than the conventional copper pattern so that only a portion between the contact plug 350 and the contact plug 350 overlaps, and preferably not larger than the blowing scheduled region (B region). This is to remove all of the copper pattern 360 in the subsequent blowing process (B ′ region).

4A and 4B are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention. FIG. 4A is a view before a cutting process of a fuse, and FIG. 4B is a view after a cutting process of a fuse.

4A and 4B, a conductive layer (not shown) is formed on the semiconductor substrate 300.

Next, after forming a photosensitive film on a conductive layer, a photosensitive film pattern (not shown) is formed by the exposure and image development process using a conductive pattern mask. The conductive layer is etched using the photoresist pattern as a mask to form a conductive pattern 310. At this time, the conductive pattern 310 is preferably one layer of the lower layer.

The first insulating layer 320 is formed on the entire surface including the conductive pattern 310.

Next, a buffer (330) film is formed on the first insulating film 320. In this case, the buffer layer 330 is formed by reducing the length of the copper pattern and reducing the size in order to reduce the remaining copper pattern or residue after blowing of the copper (Cu) pattern in a subsequent process. The size and length of this reduced copper pattern is exposed to the beam (beam) of the lower contact plug or lower layer due to a process such as Mis-Align. Thermal energy generated in the laser blowing process is transmitted to the lower layer by the beam, and a defect in which the lower layer melts occurs. Accordingly, a high resistance buffer film 330 is formed around the copper pattern to absorb thermal energy.

Next, after forming the second insulating film 340 on the entire surface including the buffer film 330, a photosensitive film is formed on the second insulating film 340. Thereafter, a photoresist pattern (not shown) is formed by an exposure and development process using a contact plug mask. The second insulating layer 340 and the first insulating layer 320 are etched until the conductive pattern 310 is exposed using the photoresist pattern as a mask to form a contact plug region (not shown). A contact plug 350 is formed by filling a conductive layer in the contact plug region.

Next, after the copper layer (not shown) is formed on the entire surface including the contact plug 350, the copper layer is etched to form a copper (Cu) pattern 360 connected to the contact plug 350. At this time, the copper pattern 360 is formed so as to overlap only a portion between the contact plug 350 and the contact plug 350, it is preferable to form smaller than the conventional copper pattern. Here, the copper pattern 360 is formed smaller than the blowing area, it is preferable that all the copper pattern 360 is removed during blowing.

Next, after the third insulating film 370 is formed on the entire surface including the copper pattern 360, the third insulating film 370 is planarized etched until the copper pattern 360 is exposed.

Thereafter, the capping nitride layer 380 is formed on the entire surface including the copper pattern 360, and then the copper pattern 360 is laser blown 390 to remove all of the copper pattern 360. By removing all of the copper patterns 360, a failure of the HAST (Highly Accelerated Stress Test) fail caused by the residues of the remaining fuses may be prevented.

As described above, the present invention is to reduce the size of the fuse pattern of the fuse blowing area to prevent the failure of the HAST (Highly Accelerated Stress Test) fail caused by the residue of the remaining fuse pattern after the fuse blowing, the By depositing a buffer insulating layer so as not to transfer thermal energy to the lower layer during blowing of the fuse pattern, there is an advantage to prevent a defect in which the lower layer is damaged by the thermal energy.

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

1 is a plan view showing a method for manufacturing a semiconductor device according to the prior art.

2A and 2B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

3 is a plan view showing a method of manufacturing a semiconductor device according to the present invention.

4A and 4B are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

Claims (9)

Forming a first insulating film on the semiconductor substrate; Forming a buffer film on the first insulating film; Forming a second insulating film on the entire surface including the buffer film; Etching the second and first insulating layers, and then filling a conductive layer to form a contact plug; And Forming a fuse pattern partially overlapping the contact plug; Wherein the semiconductor device is a semiconductor device. The method of claim 1, The fuse pattern is a method of manufacturing a semiconductor device, characterized in that formed of copper (Cu). The method of claim 1, After the forming of the fuse pattern, forming the third insulating layer, and further including a planarization etching process until the fuse pattern is exposed. The method of claim 3, wherein After the planarization etching process, further comprising the step of forming a capping nitride (Capping Nitride). The method of claim 1, The fuse pattern may be formed to partially overlap the contact plug between the contact plugs. The method of claim 1, The fuse pattern may be formed smaller than the blowing scheduled region. The method of claim 1, And forming a conductive pattern between the semiconductor substrate and the first insulating film. The method of claim 1, And the contact plug overlaps the buffer layer and the conductive pattern with a partial region. The method of claim 1, And after the forming of the fuse pattern, blowing the fuse pattern.
KR1020090122393A 2009-12-10 2009-12-10 Method for manufacturing semiconductor device KR20110065753A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113394195A (en) * 2020-03-13 2021-09-14 长鑫存储技术有限公司 Semiconductor structure, forming method thereof and fuse array

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113394195A (en) * 2020-03-13 2021-09-14 长鑫存储技术有限公司 Semiconductor structure, forming method thereof and fuse array
WO2021180124A1 (en) * 2020-03-13 2021-09-16 长鑫存储技术有限公司 Semiconductor structure and method for forming same, and fuse array

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