KR20110023533A - Latency circuit for generating latency signal using 1-division or 2-division method and semiconductor memory device having the same - Google Patents

Latency circuit for generating latency signal using 1-division or 2-division method and semiconductor memory device having the same Download PDF

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KR20110023533A
KR20110023533A KR1020090081485A KR20090081485A KR20110023533A KR 20110023533 A KR20110023533 A KR 20110023533A KR 1020090081485 A KR1020090081485 A KR 1020090081485A KR 20090081485 A KR20090081485 A KR 20090081485A KR 20110023533 A KR20110023533 A KR 20110023533A
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South Korea
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signal
latency
clock
output
read command
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KR1020090081485A
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Korean (ko)
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권상혁
정병훈
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삼성전자주식회사
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Priority to KR1020090081485A priority Critical patent/KR20110023533A/en
Priority to US12/697,547 priority patent/US8045406B2/en
Publication of KR20110023533A publication Critical patent/KR20110023533A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2272—Latency related aspects
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used

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  • Computer Hardware Design (AREA)
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Abstract

The present invention relates to a latency circuit for generating a 1-division type or a 2-division type latency signal according to a cascade latency, and a semiconductor memory device having the same. The latency circuit includes a latency control clock generator and a latency signal generator. The latency control clock generation unit receives an external clock to generate a divided signal divided by two, and generates at least one latency control clock from the two divided signals. The latency signal generator generates a latency signal in response to the latency control signal generated from the at least one latency control clock and the cascade latency information, and the internal read command signal generated from the read command. The latency circuit generates a latency signal using a divided frequency control clock, but when it is set to a low frequency operation such as CAS latency 5, a latency signal is generated using an inverted latency control clock. Eliminate

Description

Latency circuit for generating latency signal of 1 division type or 2 division type according to CAS latency, and semiconductor memory device having same {Latency circuit for generating latency signal using 1-division or 2-division method and semiconductor memory device having the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a latency circuit for generating a latency signal of one division method or two division method according to cas latency, and a semiconductor memory device having the same.

BACKGROUND OF THE INVENTION A semiconductor memory device used as a main memory in a computer system inputs data into or outputs data from a memory cell. The data input / output speed of a semiconductor memory device is a very important factor in determining the operating speed of a computer system. In order to improve the operation speed of the semiconductor memory device, a synchronous dynamic random access memory device (SDRAM) in which internal circuits are controlled in synchronization with a clock signal generated from a computer system has been used.

In general, a synchronous semiconductor memory device (SDRAM) uses a column address strobe (CAS) function to increase an operating frequency. The cas latency represents the number of cycles of an external clock until data is output to the outside after a read command is applied to the synchronous semiconductor memory device. The synchronous semiconductor memory device reads data internally in response to a read command, and then outputs data after a clock cycle corresponding to cas latency. For example, when the cas latency is 8, data is output to the outside in synchronization with the external clock 8 clock cycles after the external clock to which the read command is applied.

The latency circuit generates a latency signal, which is an output control signal, to control the output data to be output after a set clock cycle in the synchronous semiconductor memory device. In other words, the latency circuit serves as an output control circuit. The data output buffer of the synchronous semiconductor memory device outputs data in response to the output clock signal while the latency signal is activated. Therefore, the latency circuit must provide the latency signal after a read command is applied, but before a predetermined cycle of the output clock signal according to the cascade latency.

The latency signal is generated because the internal read command signal generated by decoding the read command is latched by the output clock signal and the clock signals which delay the read command. Typically, the pulse width of the internal read command signal corresponds to one period of the external clock, and the output clock signal is generated in response to a delay locked loop (DLL) clock that is generated through a delay locked loop. Have the same frequency.

As the frequency of the external clock increases, the margin between the internal read command signal and the output clock signal decreases. That is, when the frequency of the external clock is increased, the pulse width of the internal read command signal may be reduced, and the phase of the output clock signal may be ahead of the internal read command signal. In addition, since the internal read command signal is the external clock domain and the output clock signal is the delay locked loop clock domain, skew between the two domains is affected by clock frequency, ambient pressure, and temperature.

If the margin between the internal read command signal and the output clock signal decreases or if the phase of the output clock advances the pulse width of the internal read command signal, the internal read command signal is not latched normally. Missing problems can occur.

In order to solve this problem, a method of generating a latency signal by latching an internal read command signal using two divided output clock signals has been adopted. Accordingly, the latency signal can be stably generated with respect to the high frequency external clock.

On the other hand, when the latency signal is generated by being fixedly latched to two divided output clock signals, if the semiconductor memory device is set to low frequency operation such as, for example, cascade latency 5, the latency signal is generated with one clock cycle loss. That is, in case of the cascade latency of 5, an output clock signal divided by one instead of two divided output clock signals is more suitable for generating a latency signal.

Accordingly, there is a need for a latency circuit that can selectively utilize one-division or two-division output clock signals in accordance with cas latency.

SUMMARY OF THE INVENTION An object of the present invention is to provide a latency circuit that generates a latency signal of one division method or two division method in accordance with cas latency.

Another object of the present invention is to provide a semiconductor memory device including the latency circuit.

In order to achieve the above object, a latency circuit according to an aspect of the present invention, receiving an external clock to generate a divided signal divided by m (m is a natural number of two or more), and generates at least one latency control clock from the divided signal A latency control clock generator, a latency control signal generated from at least one or more of the latency control clock and the cascade latency information, and a latency signal generator for generating a latency signal in response to an internal read command signal generated from a read command.

According to embodiments of the present disclosure, the latency signal generator may be configured to output or invert at least one latency control clock in response to the latency control signal as it is, and latch an internal read command in response to at least one latency control clock. A first shift register for generating a first latch signal, at least one switch for selectively transmitting the first latch signal according to cas latency information, and a first latch transmitted through the at least one switch in response to an output of the controller The second shift register may latch a signal to generate a second latch signal.

According to embodiments of the present invention, in response to the cascade latency information, the latency signal generator outputs a second latch signal as it is and provides it as a latency signal or delays the second latch signal by one clock of an external clock as a latency signal. It may further include a control unit for providing.

According to embodiments of the present disclosure, the controller may include a buffer for inputting at least one latency control clock in response to activation of the latency control signal, and an inverter for inputting at least one latency control clock in response to deactivation of the latency control signal. The latency control signal may be set to be inactivated when the cascade latency information is set to low frequency operation of the semiconductor memory device.

According to the embodiments of the present disclosure, the latency clock generator may include a delay lock loop for generating a phase lock signal synchronized with the external clock by inputting an external clock, a clock divider for splitting the phase lock signal by two, and generating a divided signal; Inputs the divided signal and compensates the delay time by the delay lock loop to generate an output signal synchronized with the external clock, and inputs the output signal of the delay lock loop copy unit, and an internal read command signal from the read command. And an internal read command signal generation copy unit configured to generate at least one latency control clock by compensating for a delay caused by the internal read command signal generator that generates.

In order to achieve the above object, the semiconductor memory device according to another aspect of the present invention, the internal read command signal generator for generating an internal read command signal in response to a read command synchronized with an external clock, and receives an external clock m (m is a natural number of 2 or more) a latency control clock generator for generating a divided divided signal and generating at least one latency control clock from the divided signal, a latency control signal generated from at least one latency control clock and cascade latency information, And a latency signal generator for generating a latency signal in response to the internal read command signal, and an output unit for controlling data output in response to the latency signal.

According to embodiments of the present invention, the latency control clock generation unit inputs an external clock to adjust a phase of a delayed synchronization loop and a phase locked signal generated in synchronization with the external clock, and phase shifting the phase shifting signal to a clock divider. A delayed synchronous loop for generating the divided signal by dividing the phase-controlled phase-synchronized signal by two, inputting the divided signal, and compensating the delay time by the delayed synchronous loop to generate an output signal synchronized with an external clock. The copy unit may include an internal read command signal generation copy unit configured to input an output signal of the delay sync loop copy unit and compensate for the delay caused by the internal read command signal generator to generate at least one latency control clock.

According to embodiments of the present invention, the semiconductor memory device may further include a delay copy circuit for delaying the phase lock signal by a predetermined time in order to synchronize the phase lock signal with the latency signal. In response to the output, it is possible to control the data output of the output unit.

According to the above-described latency circuit of the present invention, the PREAD replica has a constant margin with respect to the internal read command signal and generates a latency control clock using divided signals having a period twice as long as the external clock. This solves the problem of the internal read command signal not being latched normally due to an increase in the frequency or a change in the PVT.

In addition, the latency circuit generates a latency signal using a divided frequency latency control clock, but when it is set to a low frequency operation such as CAS latency 5, a latency signal is generated using an inverted latency control clock so that one cycle of the external clock is generated. Eliminate losses

In addition, the latency circuit generates a latency signal by using the divided division latency control clock, but when the cas latency is set to an odd multiple, the output signal of the shift register unit is output as it is, and the cas latency is set to an even multiple. The delay signal of the shift register section is delayed by one clock of the external clock and provided as a latency signal, so that the amount of delay of the latency signal according to cas latency can be adjusted.

In addition, since the latency circuit activates the latency signal before the operation of the data output buffer according to the cascade latency, it enables a read preamble set to prevent data collision.

Since the latency circuit provided to the output unit is generated after a predetermined time delay from the phase synchronization signal, a delay copy circuit for delaying the signal by a predetermined delay time in order to synchronize the phase synchronization signal with the latency signal is provided. And generating latency control clocks and latency signals based on the phase-inverted phase-locked signal to advance by half the period of the external clock. Accordingly, by reducing the number of delay stages in the delay copy circuit for delaying the phase locked signal, it is possible to improve the noise characteristics of the delay copy circuit and to prevent excessive current consumption from flowing in the delay copy circuit.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings that illustrate preferred embodiments of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

1 is a diagram illustrating a latency circuit according to an embodiment of the present invention. Referring to FIG. 1, the latency circuit 100 may include an internal read command signal generator 110, a latency control clock generator 120, and a latency signal generator 130.

The internal read command signal generator 110 receives a read command (READ COMMAND) and receives a decoder 111 for decoding the read command and a signal DREAD output from the decoder 111, and receives an internal read command signal PREAD. It is provided with a signal generator 112 for generating and outputting. The internal read command signal PREAD output from the signal generator 112 is provided to the latency signal generator 130. The latency control clock generator 120 generates a plurality of latency control clocks PLATCLK [1: n] _E and PLATCLK [1: n] _O and provides them to the latency signal generator 130.

The latency signal generator 130 receives an internal read command signal PREAD, a plurality of latency control clocks PLATCLK [1: n] _E, PLATCLK [1: n] _O, and a latency control signal CL_CTRL. The internal read command signal PREAD is shifted and output according to the control of the plurality of latency control clocks PLATCLK [1: n] _E and PLATCLK [1: n] _O and the latency control signal CL_CTRL. The signal shifted from the internal read command signal PREAD is a latency signal LATENCY, which is used to control the data output.

The latency control clock generation unit 120 includes a delay synchronization loop (DLL, 121), a clock divider 122, and a copy unit (hereinafter referred to as "DLL replica") 123 of the delay synchronization loop 121, A copy unit (hereinafter referred to as a "PREAD replica") 124 of the internal read command signal generator 110, an odd / even splitter (ODD / EVEN Splitter) 125, and a delay block 126 are included. The latency control clock generator 120 may improve the conventional problem in which the internal read command signal PREAD is not normally latched due to an increase in the frequency of the external clock CLK or a PVT change. By using to generate a latency control clock (PLATCLK1_E) having a constant margin for the internal read command signal (PREAD). The latency control clock generator 120 generates the latency control clocks PLATCLK [1: n] _E and PLATCLK [1: n] _O by using the clock divider 122 to external clock CLK. Latency control clocks PLATCLK [1: n] _E and PLATCLK [1: n] _O are generated using the divided signals having a period of twice.

The delay synchronization loop 121 receives an external clock CLK and outputs a phase synchronization signal PDLL0. The phase synchronization signal PDLL0 is provided to the clock divider 122, and the clock divider 122 outputs the divided signal by m-dividing the phase synchronization signal PDLL0 (m is an integer of 2 or more). Preferably, the clock divider 122 is a circuit for dividing an input signal into two, and the divided signal consists of an even divided signal DIVCLK_E and an odd divided signal DIVCLK_O having opposite phases to each other.

The divided signal of any one of the even and odd divided signals is input to the DLL replica 123. In FIG. 1, an even divided signal DIVCLK_E is input to the DLL replica 123 as an example. The DLL replica 123 delays the even division signal DIVCLK_E to a predetermined phase. That is, the delay time by the delay synchronization loop 121, for example, the time equal to tSAC, is compensated by the DLL replica 123, so that the part whose phase is changed by the phase synchronization loop 121 can be recovered again. Accordingly, the output signal DOUT0_REP of the DLL replica 123 is synchronized with the external clock CLK.

The output signal DOUT0_REP of the DLL replica 123 is input to the PREAD replica 124. The PREAD replica 124 delays the output signal DOUT0_REP of the DLL replica 123 by a predetermined phase to generate a first latency control clock PLATCLK1_E for even. The PREAD replica 124 compensates for the phase delayed by the internal read command signal generator 110, and the predetermined phase value delayed by the PREAD replica 124 includes an external clock CLK and an internal read command signal. The value depends on the phase difference of (PREAD). That is, the predetermined phase value is determined by the phase difference between the edge of the external clock CLK to which the read command READ COMMAND is input and the internal read command signal PREAD generated by the internal read command signal generator 110. do. Preferably, the predetermined phase value is set to have a value slightly smaller than the phase difference between the external clock CLK and the internal read command signal PREAD.

The first latency control clock PLATCLK1_E for even output from the PREAD replica 124 is provided to the odd / even separator 125. The odd / even separator 125 receives the first latency control clock PLATCLK1_E for the even and further generates the first latency control clock PLATCLK1_O for the odds using the input signal. Preferably, the odd first latency control clock PLATCLK1_O is a signal having a phase opposite to the even first latency control clock PLATCLK1_E. The odd / even separator 125 provides the first latency control clock PLATCLK1_E for odds and the first latency control clock PLATCLK1_O for odds to the latency signal generator 130.

On the other hand, the divided signal DIVCLK_E (O) is also provided to the delay block 126. The delay block 126 may provide a second latency control clock to an nth latency control clock PLATCLK [2: n] _E (O) to the latency signal generator 130.

That is, the delay block 126 receives the even division signal DIVCLK_E and delays the first division block to generate the second latency control clock to nth latency control clock PLATCLK [2: n] _E for the even. And a second delay block configured to receive the odd division signal DIVCLK_O and delay it to generate the second latency control clock to the nth latency control clock PLATCLK [2: n] _O. Detailed operation of the delay block 126 will be described later.

The latency signal generator 130 receives the internal read command signal PREAD from the internal read command signal generator 110 and the first latency control clocks PLATCLK1_E and PLATCLK1_O from the latency control clock generator 120. The second latency control clock to the nth latency control clock PLATCLK [2: n] _E (O) are input, and the latency control signal CL_CTRL generated from the cas latency information set in the mode register is received. Although not illustrated, the latency signal generator 130 may include a first shift register unit for shifting the internal read command signal PREAD using the even latency control clock PLATCLK [1: n] _E, and an odd signal. The second shift register unit may shift the internal read command signal PREAD using the latency control clock PLATCLK [1: n] _O. Each of the first shift register unit and the second shift register unit may include a plurality of shift registers.

The latency circuit 100 configured as described above has a constant margin for the first latency control clocks PLATCLK1_E and PLATCLK1_O generated by the latency control clock generator 120 with respect to the internal read command signal PREAD. Have Therefore, even if the frequency of the external clock CLK of the semiconductor memory device increases or the PVT condition changes, the internal read command signal PREAD may be stably latched by the edges of the first latency control clocks PLATCLK1_E and PLATCLK1_O. . After the internal read command signal PREAD is stably latched, subsequent latching operations can be stably performed by appropriately adjusting the delay amount of the delay block 126.

In addition, since the latency control clock PLATCLK [1: n] _E (O) generated by the latency control clock generator 120 is generated using a two-divided signal, it is necessary to latch the internal read command signal PREAD. Thus, a frequency margin can be secured.

FIG. 2 is a diagram for explaining another example of generating the first latency control clocks shown in FIG. 1. Referring to FIG. 2, a DLL replica and a PREAD replica may be separately provided for each of the two-dividing signals DIVCLK_E and DIVCLK_O to remove the odd / even separator 125 of FIG. 1. The clock divider 122 generates the two-division signals DIVCLK_E and DIVCLK_O, the even division signal DIVCLK_E is input to the first DLL replica 123_1, and the odd division signal DIVCLK_O is the second DLL ripple. It is input to the camera 123_2. The output signal DOUT0_REP_E of the first DLL replica 123_1 is input to the first PREAD replica 124_1, and the output signal DOUT0_REP_O of the second DLL replica 123_2 is the second PREAD replica 124_2. Is entered.

The first PREAD replica 124_1 delays the output signal DOUT0_REP_E of the first DLL replica 123_1 to a predetermined value to generate a first latency control clock PLATCLK1_E for even. The second PREAD replica 124_2 delays the output signal DOUT0_REP_O of the second DLL replica 123_2 to a predetermined value to generate the first latency control clock PLATCLK1_O for the odd. The delayed predetermined value is a value depending on the phase difference between the external clock CLK and the internal read command signal PREAD, and compensates for the phase delayed by the internal read command signal generator 110.

The even first latency control clock PLATCLK1_E and the odd first latency control clock PLATCLK1_O are provided to the latency signal generator 130. The latency signal generator 130 latches the internal read command signal PREAD using the first latency control clocks PLATCLK1_E and PLATCLK1_O.

3 is a diagram illustrating the latency signal generator 130 and the delay block 126 of FIG. 1. Referring to FIG. 3, the latency signal generator 130 may include a first shift register 131, a second shift register 132, a first adjuster 133, a second adjuster 134, and a logic device. (135). In addition, the delay block 126 includes a first delay block 126_1 and a second delay block 126_2.

The internal read command signal PREAD and the latency control signal CL_CTRL are input to the first shift register 131 and the second shift register 132, respectively. An even first latency control clock PLATCLK1_E and an even second latency control clock to an nth latency control clock PLATCLK [2: n] _E are input to the first shift register unit 131. The first delay block 126_1 receives the even division signal DIVCLK_E and generates the second latency control clock to nth latency control clock PLATCLK [2: n] _E for even. An odd first latency control clock PLATCLK1_O and an odd second latency control clock to an nth latency control clock PLATCLK [2: n] _O are input to the second shift register unit 132. The second delay block 126_2 receives the odd frequency division signal DIVCLK_O and generates the second latency control clock to nth latency control clock PLATCLK [2: n] _O for the odd.

Each of the first shift register 131 and the second shift register 132 includes a plurality of shift registers. As an example, the first shift register 131 may include n shift registers. As the clock stage of each of the n shift registers, an even first latency control clock and an nth latency control clock PLATCLK [1: n] _E are respectively input.

When the internal read command signal PREAD is input to the input terminal of the first shift register, the first shift register shifts the internal read command signal PREAD in synchronization with the first latency control clock PLATCLK1_E for output. The output signal of the first shift register is input to the input terminal of the second shift register connected in series with the first shift register. The second shift register shifts the input signal in synchronization with the even second latency control clock PLATCLK2_E. The output signal of the second shift register is input to the input terminal of the third shift register. Through this process, an output signal of the nth shift register is generated.

The operation of the second shift register unit 132 is also similar to the operation of the first shift register unit 131 described above. An odd first latency control clock to an nth latency control clock PLATCLK [1: n] _O are respectively input to a clock terminal of each of the n shift registers provided in the second shift register unit 132. Each shift register shifts and outputs the internal read command signal PREAD in synchronization with the respective latency control clock.

The first control unit 133 receives the output signal of the first shift register unit 131 and, if a predetermined condition is satisfied, delays the input signal by one clock of the external clock CLK and outputs the delayed signal. As an example, when the cascade latency CL of the semiconductor memory device is set to an odd multiple of the external clock CLK, the first adjusting unit 133 outputs the output signal of the first shift register unit 131 as it is to display the latency signal. Provided as (LATENCY). When the CAS latency CL is set to an even multiple of the external clock CLK, the first adjusting unit 133 delays the output signal of the first shift register unit 131 by one clock of the external clock CLK, thereby providing a latency signal. Provided as (LATENCY).

The reason for this configuration is that the internal read command signal PREAD is shifted using the latency control clock having twice the period compared to the external clock CLK in accordance with one embodiment of the present invention. Therefore, it is necessary to additionally adjust the shifting corresponding to one clock of the external clock CLK.

The first adjuster 133 may include one shift register and a logic element, for example, an OR gate. The odd division signal DIVCLK_O may be input to the clock terminal of the shift register. The phase difference between the rising edge of the odd divided signal CLKDQ_O and the rising edge of the even divided signal DIVCLK_E has a difference corresponding to one clock of the external clock CLK. Therefore, the delay amount of the latency signal LATENCY can be adjusted by such a configuration.

The second adjustment unit 134 also operates similarly to the operation of the first adjustment unit 133 described above. That is, the second adjusting unit 134 receives the signal output from the second shift register unit 132 and, if a predetermined condition is satisfied, delays the input signal by one clock of the external clock CLK and outputs the signal. do. An even divided signal DIVCLK_E may be input to the clock terminal of the shift register provided in the second controller 134.

The logic element 135 may be formed as an OR-gate, and outputs any one of a signal output from the first controller 133 and a signal output from the second controller 134 as a latency signal LATENCY. do. That is, when the first shift register unit 131 is activated, the signal output from the first adjusting unit 133 is output as a latency signal LATENCY, and when the second shift register unit 132 is activated, the second adjustment unit is output. The signal output from the unit 134 is output as the latency signal LATENCY.

4 illustrates a first shift register 131, a second shift register 132, a first adjuster 133, a second adjuster 134, a first delay block 126_1, and a second shift register 131 of FIG. 3. A circuit diagram illustrating the delay block 126_2 in detail. Referring to FIG. 4, the first shift register unit 131 includes a plurality of shift registers SR1_E to SR5_E, a plurality of switches SW1 to SW4, and a first control unit 401. The SR1_E shifter register latches the internal read command signal PREAD in response to the first latency control clock PLATCLK1_E for output and outputs the first latch signal LAT_1st. The first latch signal LAT_1st is connected to the SW1 to SW4 switches, and each of the SW1 to SW4 switches corresponds to the first latch response information CL5, 6, CL7, 8, CL9, 10, and CL11 in response to the corresponding latch latency information CL5, 6, CL7, 8, CL9, 10, and CL11. The signal LAT_1st is transferred to the SR2_E to SR5_E shifter registers.

 The SR2_E shifter register latches and outputs the first latch signal LAT_1st in response to the second latency control clock PLATCLK2_E for even when the cas latency information is 11 (CL11). The output of the SR2_E shifter register is input to the SR3_E shifter register.

The SR3_E shifter register inputs the output of the SR2_E shifter register or the first latch signal LAT_1st. The SR3_E shifter register latches and outputs the output of the SR2_E shifter register in response to the even third latency control clock (PLATCLK3_E) when the CAS latency information is 11 (CL11), and the CAS latency information is 9 or 10 (CL9). 10, the first latch signal LAT_1st is latched and output in response to the even third latency control clock PLATCLK3_E. The output of the SR3_E shifter register is input to the SR4_E shifter register.

The SR4_E shifter register inputs the output of the SR3_E shifter register or the first latch signal LAT_1st. The SR4_E shifter register latches and outputs the output of the SR3_E shifter register in response to the fourth latency control clock PLATCLK4_E for even when the cas latency information is 9, 10, or 11 (CL9, 10, CL11). The SR4_E shifter register latches and outputs the first latch signal LAT_1st in response to the fourth latency control clock PLATCLK4_E for even when the cas latency information is 7 or 8 (CL7, 8). The second latch signal LAT_2nd, which is an output of the SR4_E shifter register, is input to the SR5_E shifter register.

The SR5_E shifter register inputs the output of the SR4_E shifter register or the first latch signal LAT_1st. The SR5_E shifter register outputs the SR4_E shifter register in response to the fifth latency control clock (PLATCLK5_E) for even when the cas latency information is 7, 8, 9, 10, or 11 (CL7, 8, CL9, 10, CL11). Latch to output. The SR5_E shifter register latches and outputs the first latch signal LAT_1st in response to the fifth latency control clock PLATCLK5_E for even when the cas latency information is 6 (CL6). The SR5_E shifter register is configured to respond to the inverted signal of the even fifth latency control clock PLATCLK5_E, that is, the fifth latency control clock PLATCLK5_O for the first latch signal when the cas latency information is 5 (CL5). LAT_1st) is latched and output. The third latch signal LAT_3rd, which is an output of the SR5_E shifter register, is an output of the first shift register 131 and is transmitted to the first adjusting unit 133.

In response to the latency control signal CL_CTRL, the first control unit 401 transfers the even fifth latency control clock PLATCLK5_E to the SR5_E shifter register. Determines whether to pass to the register. The first control unit 401 includes a buffer 411 and an inverter 412 for inputting the fifth latency control clock PLATCLK5_E for the even, and the buffer 411 responds to a logic high level of the latency control signal CL_CTRL. Is enabled, and the inverter 412 is enabled in response to a logic low level of the latency control signal CL_CTRL. The latency control signal CL_CTRL is at a logic low level when the semiconductor memory device is set to low frequency operation such as, for example, cascade latency 5, and at a logic high level when the semiconductor memory device is set to cascade latency 6 or more.

The first delay block 126_1 includes a plurality of delay elements DELAY connected in series, and inputs an even division signal DIVCLK_E to be delayed by a predetermined time by an even fifth latency control clock PLATCLK5_E and an even fourth latency. The control clock PLATCLK4_E, the third latency control clock PLATCLK3_E for even and the second latency control clock PLATCLK2_E for even are generated.

The first adjusting unit 133 is configured to shift the clock corresponding to one clock of the external clock CLK according to the case where the cascade latency CL of the semiconductor memory device is set to an odd multiple of the external clock CLK and an even multiple of the external clock CLK. Make further adjustments to the The first adjusting unit 133 includes switches SW5 and SW6, a shift register SR6_E, and a logic circuit OR1. The SW5 switch transmits a third latch signal LAT_3rd, which is an output of the first shift register unit 131, to the gate OR1 when the cascading latency information is odd (CL5, 7, 9, 11). The SW6 switch transfers the third latch signal LAT_3rd to the SR6_E shift register when the cas latency information is even (CL6, 8, 10). The SR6_E shift register latches and outputs the third latch signal LAT_3rd in response to the odd division signal DIVCLK_O. The logic circuit OR1 is configured as an OR gate, and a latency signal is a signal obtained by delaying the third latch signal LAT_3rd by one clock of an external clock through the third latch signal LAT_3rd or the SR6_E shift register transmitted through the SW5 switch. Print as (LATENCY).

The second shifter register 132, the second delay block 126_2, and the second adjuster 134 may include the first shifter register 131, the first delay block 126_1, and the first adjuster 133. ) Is similar to the configuration and operation. However, the second shifter register unit 132 and the second delay block 126_2 are different in that they are operated in response to the odd latency control clocks PLATCLK [1: 5] _O. 134 differs in that it is operated in response to the even division signal DIVCLK_E. In order to avoid duplication of description, detailed descriptions of the second shifter register unit 132, the second delay block 126_2, and the second adjustment unit 134 are omitted.

FIG. 5 is a timing diagram illustrating an operation when the latency circuit 100 of FIG. 1 operates at the cascade latency 5. FIG. Referring to FIG. 5 in conjunction with FIG. 4, the switches SW1 to SW4 are selectively turned on / off in response to the cascade latency information CL5 and displayed in the first arrow direction (−−… −−>). A signal transmission path is generated. The phase synchronization signal PDLL0 is generated by receiving the external clock CLK (ⓐ). Each edge of the external clock CLK is numbered to indicate a corresponding relationship between each edge of the external clock CLK and the remaining signals. The phase synchronization signal PDLL0 is divided into two to generate an even division signal DIVCLK_E (ⓑ).

The even division signal DIVCLK_E generates an output signal DOUT0_REP of the DLL replica 123 synchronized with the external clock CLK through the DLL replica 123 (©). The output signal DOUT0_REP of the DLL replica 123 determines whether the internal read command signal PREAD is to be latched by the even latency control clock or the odd latency control clock. When the output signal DOUT0_REP of the DLL replica 123 is the rising edge at the next clock at the time when READ) is input, for example, the second edge CLK 2 of the external clock CLK, It is latched by the idle latency control clock. On the other hand, when the output signal DOUT0_REP of the DLL replica 123 is the falling edge, it may be latched by the odd latency control clock. The output signal DOUT0_REP of the DLL replica 123 is generated as the first latency control clock PLATCLK1_E for even through the PREAD replica 124 (ⓔ).

The read command READ input at the first edge CLK 1 of the external clock CLK is generated as the internal read command signal PREAD (ⓕ). The internal read command signal PREAD is latched by the even first latency control clock PLATCLK1_E and is generated as the first latch signal LAT_1st ().

The first latch signal LAT_1st is transferred to the SR5_E shift register through the SW4 switch and inverts the fifth latency control clock PLATCLK5_E for even by the logic low level latency control signal CTRL set at the cascade latency 5. The signal is passed to the SR5_E shift register. The fifth latency control clock PLATCLK5_E for the even input to the first controller 401 has the same waveform as the even division signal DIVCLK_E. The SR5_E shift register latches the first latch signal LAT_1st in response to an inverted signal of the even fifth latency control clock PLATCLK5_E to output the third latch signal LAT_3rd. The third latch signal LAT_3rd is generated as a latency signal through the SW5 switch, the logic circuit OR1, and the logic element 135 (ⓘ).

When set to CAS latency 5, the latency signal LATENCY is activated for two clock cycles two clocks after the read command input CLK 1 (CLK 3). Accordingly, the data output buffer in the semiconductor device outputs data in accordance with the sixth edge CLK 6 of the external clock CLK in response to the activation of the latency signal LAYENCY (not shown). As the latency signal LATENCY is previously activated during the third to fifth edges CLK 3 to CLK 5 of the external clock CLK, a read preamble set to prevent data collision is enabled. do.

FIG. 6 is a timing diagram illustrating an operation when the latency circuit 100 of FIG. 1 operates at the cascade latency 8. FIG. Referring to FIG. 6 in conjunction with FIG. 4, the switches SW1 to SW4 are selectively turned on / off in response to the cascade latency information CL8 so that the signal transmission path indicated in the first arrow direction (--->) is shown. Is generated. Since the operation timing of generating the first latch signal LAT_1st by latching the read command READ input at the first edge CLK 1 of the external clock CLK is the same as the steps ⓐ to ⓖ of FIG. 4 described above, Omitted to avoid duplication of description. The fourth latency control for even if the predetermined time delay is delayed from the fifth latency control clock PLATCLK5_E and the fifth latency control clock PLATCLK5_E for the first time through the first delay block 126_1 for inputting the even division signal DIVCLK_E. The clock PLATCLK4_E is generated.

The first latch signal LAT_1 st is transferred to the SR4_E shift register through the SW3 switch. The SR4_E shift register latches the first latch signal LAT_1st in response to the fourth latency control clock PLATCLK4_E for output to output the second latch signal LAT_2nd. The SR5_E shifter register latches the second latch signal LAT_2nd in response to the fifth latency control clock PLATCLK5_E for output and outputs the third latch signal LAT_3rd. The third latch signal LAT_3rd is provided to the SR6_E shifter register through the SW6 switch. The SR6_E shift register latches and outputs the third latch signal LAT_3rd in response to the odd division signal DIVCLK_O. The output of the SR6_E shift register is generated as a latency signal LATENCY through the logic circuit OR1 and the logic element 135 (ⓝ).

When set to CAS latency 8, the latency signal LATENCY is activated for two clock cycles six clocks after the read command input CLK 1 (CLK 3). Accordingly, the data output buffer in the semiconductor device outputs data in accordance with the ninth edge CLK 9 of the external clock CLK in response to activation of the latency signal LAYENCY (not shown). As the latency signal LATENCY is pre-activated during the seventh to ninth edges CLK 7 to CLK 9 of the external clock CLK, the read signal can be read preamble.

5 and 6 illustrate examples in which the internal read command signal PREAD is latched by an even latency control clock. On the other hand, when the output signal DOUT0_REP of the DLL replica 123 is the falling edge, the internal read command signal PREAD is latched by the odd latency control clock. Waveforms when latched by the odd latency control clock are obvious from the waveforms shown in FIGS. 5 and 6, and thus description thereof is omitted.

7 is a diagram illustrating a semiconductor memory device 200 according to another embodiment of the present invention. The above-mentioned elements among the elements shown in FIG. 7 operate similarly to those mentioned above, and thus detailed description thereof will be omitted.

The phase lock loops DLL and 221 in the latency control clock generator 220 of the semiconductor memory device 200 generate a phase lock signal PDLL0, and the phase lock signal PDLL0 is connected to the external clock CLK. This is a synchronized signal. The latency signal generator 230 receives an internal read command signal PREAD from the internal read command signal generator 210 and at least one latency control clock PLATCLK [1: n] from the latency control clock generator 220. _E (O)) is input. The latency signal generator 230 shifts the internal read command signal PREAD according to the control of the plurality of latency control clocks and outputs it as a latency signal LATENCY. The latency signal LATENCY is used to control data output. do. The latency signal LATENCY is provided to the output unit DDRMUX 250 via a predetermined logic circuit unit 240. The output unit 250 receives a latency signal LATENCY through the logic circuit unit 240.

On the other hand, when the output unit 250 controls the data output, stability should be ensured even when the PVT changes. To this end, the output unit 250 synchronizes the phase synchronization signal PDLL0 with the latency signal LATENCY. However, in the case of generating the latency signal LATENCY based on the phase synchronization signal PDLL0, a signal path including the latency control clock generator 120, the latency signal generator 130, and the logic circuit 240 is provided. ), The latency signal LATENCY provided to the output unit 250 is generated after a predetermined time delay from the phase synchronization signal PDLL0. Accordingly, the semiconductor memory device 200 delays the signal by a predetermined delay time in order for the output unit 250 to synchronize the phase synchronization signal PDLL0 with the latency signal LATENCY. It is provided.

The delay copy circuit 260 may require delay stages consisting of inverters connected in series, for example. When the number of delay stages increases, a problem arises in that excessive current consumption flows in the delay radiation circuit 260 or has a characteristic vulnerable to noise. To solve this problem, the phase of the phase synchronization signal PDLL0 input to the clock divider 122 is adjusted to set the phase-adjusted signal to be divided. As illustrated in FIG. 8, the phase controller for adjusting the phase of the phase synchronization signal PDLL0 may be disposed outside the clock divider 122 or may be included in the clock divider 122.

Referring to FIG. 8, the phase adjuster 227 inputs a phase synchronization signal PDLL0 to output a signal PDLL0B that is out of phase with the phase synchronization signal PDLL0. The clock divider 122 'inputs the phase-adjusted signal PDLL0B, divides it, and outputs an even division signal DIVCLK_E'. The even divided signal DIVCLK_E 'is out of phase with the even divided signal DIVCLK_E output from the aforementioned clock divider 122.

FIG. 9 is a circuit diagram illustrating the phase adjuster 127 and the clock divider 122 'of FIG. 8. Referring to FIG. 9, the phase adjuster 127 is configured as an inverter. The inverter receives the phase synchronization signal PDLL0 and inverts the phase to output it. The phase inverted phase synchronization signal PDLL0B is provided to the clock divider 222. The clock divider 122 ′ generates an even divided signal DIVCLK_E ′ and an odd divided signal DIVCLK_O ′ that are divided into two based on the phase inverted phase synchronization signal PDLL0B.

FIG. 10 is a timing diagram illustrating an operation of the phase adjuster 127 and the clock divider 122 'of FIG. 9. Referring to FIG. 10, the phase inverted phase synchronization signal PDLL0B is 180 degrees out of phase with respect to the phase synchronization signal PDLL0, which is half the cycle of the external clock, 1/2 CLK. Accordingly, the even divided signal DIVCLK_E which divides the phase synchronization signal PDLL0 by two is activated to a high level at a time point, whereas the even divided signal DIVCLK_E 'which divided the phase inverted phase synchronization signal PDLL0B by two is divided. Is activated at a high level at time b. That is, the phase of the even division signal DIVCLK_E 'is 180 degrees ahead.

Although not shown in the timing diagram of FIG. 10, it is not necessary to invert the phase of the phase synchronization signal PDLL0 in adjusting the phase of the phase synchronization signal PDLL0. The phase of the phase synchronization signal PDLL0 may be adjusted to be smaller or larger than 180 degrees.

FIG. 11 is a partial block diagram of the semiconductor memory device 200 described in order to reduce the number of delay stages in the delay copy circuit of FIG. 7 using the phase adjuster 127 of FIG. 8. Referring to FIG. 11, the phase synchronization signal PDLL0 output from the delay synchronization loop 121 is provided to the delay copy circuit 260. The phase adjuster 127 inverts the phase of the phase synchronization signal PDLL0 and outputs the phase inverted phase synchronization signal PDLL0B. The clock divider 122 ′ generates an even divided signal DIVCLK_E ′ and an odd divided signal DIVCLK_O ′ that are divided into two based on the phase inverted phase synchronization signal PDLL0B. The two divided even divided signal DIVCLK_E 'and the odd divided signal DIVCLK_O' are advanced by a half cycle of the external clock CLK, that is, 1/2 CLK, relative to the phase synchronization signal PDLL0. The latency signal LAYENCY generated by using the latency control clocks PLATCLK [1: n] _E and PLATCLK [1: n] _O generated based on the evenly divided even divided signal DIVCLK_E 'is also an external clock. Half a cycle of CLK), that is, 1/2 CLK.

Accordingly, the delay amount of the delay copy circuit 260 for delaying the phase synchronization signal PDLL0 can be reduced. Since the delay amount is reduced, the number of delay stages in the delay copy circuit 260 can be reduced. As a result, the noise characteristic of the delayed radiation circuit 260 can be improved, and excessive current consumption can be prevented from flowing to the delayed radiation circuit 260.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

1 is a diagram illustrating a latency circuit according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining another example of generating the first latency control clocks shown in FIG. 1.

3 is a diagram illustrating a latency signal generator and a delay block of FIG. 1.

FIG. 4 is a circuit diagram specifically illustrating a first shift register part, a second shift register part, a first adjuster, a second adjuster, a first delay block, and a second delay block of FIG. 3.

FIG. 5 is a timing diagram illustrating an operation when the latency circuit of FIG. 1 operates with cas latency 5.

FIG. 6 is a timing diagram illustrating an operation when the latency circuit of FIG. 1 operates with cas latency 8.

7 is a diagram illustrating a semiconductor memory device according to another embodiment of the present invention.

FIG. 8 is a diagram for explaining a phase adjusting unit for synchronizing a phase synchronizing signal to a latency signal at the output of FIG. 7.

FIG. 9 is a circuit diagram illustrating a phase adjuster and a clock divider of FIG. 8.

FIG. 10 is a timing diagram illustrating an operation of a phase adjuster and a clock divider of FIG. 9.

FIG. 11 is a partial block diagram illustrating a semiconductor memory device in which the number of delay stages in the delay copy circuit of FIG. 7 is reduced by using the phase adjuster of FIG. 8.

Explanation of symbols on the main parts of the drawings

100: latency circuit 110: internal read command signal generator

111: decoder 112: PREAD generator

120: latency control clock generator 121: delay synchronization loop

122: clock divider 123: DLL replica

124: PREAD replica 125: Aether / even separator

126: delay block 130: latency signal generator

200: semiconductor memory device 250: output unit

260: delayed copy circuit 401, 402: control unit

Claims (10)

A latency control clock generator configured to receive an external clock and generate a divided signal divided by m (m is a natural number of 2 or more), and generate at least one latency control clock from the divided signal; And And a latency signal generator for generating a latency signal in response to the latency control signal generated from the at least one latency control clock and cas latency information, and an internal read command signal generated from a read command. The method of claim 1, wherein the latency signal generator A controller configured to output the at least one latency control clock as it is or invert the output in response to the latency control signal; A first shift register configured to latch the internal read command to generate a first latch signal in response to the at least one latency control clock; At least one switch for selectively transferring the first latch signal according to the cas latency information; And And a second shift register configured to generate a second latch signal by latching the first latch signal transmitted through the at least one switch in response to an output of the controller. The method of claim 2, wherein the latency signal generator And a controller configured to output the second latch signal as the latency signal in response to the cas latency information or to delay the second latch signal by one clock of the external clock to provide the latency signal. Latency circuit characterized by. The method of claim 2, wherein the control unit A buffer configured to input the at least one latency control clock in response to activation of the latency control signal; And An inverter configured to input the at least one latency control clock in response to deactivation of the latency control signal; And the latency control signal is inactivated when the cas latency information is set to low frequency operation of a semiconductor memory device. The method of claim 1, wherein the latency clock generator A delay synchronization loop configured to input the external clock to generate a phase synchronization signal synchronized with the external clock; A clock divider which divides the phase synchronization signal into two to generate the divided signal; A delay lock loop copying unit configured to input the divided signal and compensate an delay time caused by the delay lock loop to generate an output signal synchronized with the external clock; And An internal read command signal inputting an output signal of the delayed synchronization loop copy unit and compensating for a delay by an internal read command signal generator that generates the internal read command signal from the read command to generate the at least one latency control clock A latency circuit comprising a generation radiation unit. An internal read command signal generator configured to generate an internal read command signal in response to a read command synchronized with an external clock; A latency control clock generator configured to receive the external clock and generate a divided signal divided by m (m is a natural number of 2 or more), and generate at least one latency control clock from the divided signal; A latency signal generator configured to generate a latency signal in response to the latency control signal generated from the at least one latency control clock and cas latency information, and the internal read command signal; And And an output unit configured to control data output in response to the latency signal. The method of claim 6, wherein the latency signal generator A controller configured to output the at least one latency control clock as it is or invert the output in response to the latency control signal; A first shift register configured to latch the internal read command to generate a first latch signal in response to the at least one latency control clock; At least one switch for selectively transferring the first latch signal according to the cas latency information; And And a second shift register configured to generate a second latch signal by latching the first latch signal transmitted through the at least one switch in response to an output of the controller. The method of claim 7, wherein the latency signal generator And a controller configured to output the second latch signal as the latency signal in response to the cas latency information or to delay the second latch signal by one clock of the external clock to provide the latency signal. Latency circuit characterized by. The method of claim 6, wherein the latency control clock generator A delay synchronization loop configured to input the external clock to generate a phase synchronization signal synchronized with the external clock; A phase adjusting unit which adjusts a phase of the phase synchronizing signal and transfers it to a clock divider; The clock divider for dividing the phase-controlled phase-locked signal by two to generate the divided signal; A delay lock loop copying unit configured to input the divided signal and compensate an delay time caused by the delay lock loop to generate an output signal synchronized with the external clock; And And an internal read command signal generation copy unit configured to input an output signal of the delayed synchronization loop copy unit and compensate for a delay caused by the internal read command signal generator to generate the at least one latency control clock. Device. The semiconductor memory device of claim 9, wherein the semiconductor memory device comprises: And delay delay circuit for delaying the phase synchronization signal a predetermined time to synchronize the phase synchronization signal with the latency signal. And the data output unit of the output unit in response to the output of the latency signal and the delay copy circuit.
KR1020090081485A 2006-10-31 2009-08-31 Latency circuit for generating latency signal using 1-division or 2-division method and semiconductor memory device having the same KR20110023533A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140007040A (en) * 2012-07-04 2014-01-16 에스케이하이닉스 주식회사 Latency control circuit and semiconductor device including the circuit
KR20170108454A (en) * 2016-03-17 2017-09-27 에스케이하이닉스 주식회사 Latency control device ans semiconductor device including the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140007040A (en) * 2012-07-04 2014-01-16 에스케이하이닉스 주식회사 Latency control circuit and semiconductor device including the circuit
KR20170108454A (en) * 2016-03-17 2017-09-27 에스케이하이닉스 주식회사 Latency control device ans semiconductor device including the same

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