KR20110023533A - Latency circuit for generating latency signal using 1-division or 2-division method and semiconductor memory device having the same - Google Patents
Latency circuit for generating latency signal using 1-division or 2-division method and semiconductor memory device having the same Download PDFInfo
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- KR20110023533A KR20110023533A KR1020090081485A KR20090081485A KR20110023533A KR 20110023533 A KR20110023533 A KR 20110023533A KR 1020090081485 A KR1020090081485 A KR 1020090081485A KR 20090081485 A KR20090081485 A KR 20090081485A KR 20110023533 A KR20110023533 A KR 20110023533A
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- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
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- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
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- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
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- G—PHYSICS
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- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/22—Control and timing of internal memory operations
- G11C2207/2272—Latency related aspects
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
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Abstract
The present invention relates to a latency circuit for generating a 1-division type or a 2-division type latency signal according to a cascade latency, and a semiconductor memory device having the same. The latency circuit includes a latency control clock generator and a latency signal generator. The latency control clock generation unit receives an external clock to generate a divided signal divided by two, and generates at least one latency control clock from the two divided signals. The latency signal generator generates a latency signal in response to the latency control signal generated from the at least one latency control clock and the cascade latency information, and the internal read command signal generated from the read command. The latency circuit generates a latency signal using a divided frequency control clock, but when it is set to a low frequency operation such as CAS latency 5, a latency signal is generated using an inverted latency control clock. Eliminate
Description
BACKGROUND OF THE
BACKGROUND OF THE INVENTION A semiconductor memory device used as a main memory in a computer system inputs data into or outputs data from a memory cell. The data input / output speed of a semiconductor memory device is a very important factor in determining the operating speed of a computer system. In order to improve the operation speed of the semiconductor memory device, a synchronous dynamic random access memory device (SDRAM) in which internal circuits are controlled in synchronization with a clock signal generated from a computer system has been used.
In general, a synchronous semiconductor memory device (SDRAM) uses a column address strobe (CAS) function to increase an operating frequency. The cas latency represents the number of cycles of an external clock until data is output to the outside after a read command is applied to the synchronous semiconductor memory device. The synchronous semiconductor memory device reads data internally in response to a read command, and then outputs data after a clock cycle corresponding to cas latency. For example, when the cas latency is 8, data is output to the outside in synchronization with the
The latency circuit generates a latency signal, which is an output control signal, to control the output data to be output after a set clock cycle in the synchronous semiconductor memory device. In other words, the latency circuit serves as an output control circuit. The data output buffer of the synchronous semiconductor memory device outputs data in response to the output clock signal while the latency signal is activated. Therefore, the latency circuit must provide the latency signal after a read command is applied, but before a predetermined cycle of the output clock signal according to the cascade latency.
The latency signal is generated because the internal read command signal generated by decoding the read command is latched by the output clock signal and the clock signals which delay the read command. Typically, the pulse width of the internal read command signal corresponds to one period of the external clock, and the output clock signal is generated in response to a delay locked loop (DLL) clock that is generated through a delay locked loop. Have the same frequency.
As the frequency of the external clock increases, the margin between the internal read command signal and the output clock signal decreases. That is, when the frequency of the external clock is increased, the pulse width of the internal read command signal may be reduced, and the phase of the output clock signal may be ahead of the internal read command signal. In addition, since the internal read command signal is the external clock domain and the output clock signal is the delay locked loop clock domain, skew between the two domains is affected by clock frequency, ambient pressure, and temperature.
If the margin between the internal read command signal and the output clock signal decreases or if the phase of the output clock advances the pulse width of the internal read command signal, the internal read command signal is not latched normally. Missing problems can occur.
In order to solve this problem, a method of generating a latency signal by latching an internal read command signal using two divided output clock signals has been adopted. Accordingly, the latency signal can be stably generated with respect to the high frequency external clock.
On the other hand, when the latency signal is generated by being fixedly latched to two divided output clock signals, if the semiconductor memory device is set to low frequency operation such as, for example,
Accordingly, there is a need for a latency circuit that can selectively utilize one-division or two-division output clock signals in accordance with cas latency.
SUMMARY OF THE INVENTION An object of the present invention is to provide a latency circuit that generates a latency signal of one division method or two division method in accordance with cas latency.
Another object of the present invention is to provide a semiconductor memory device including the latency circuit.
In order to achieve the above object, a latency circuit according to an aspect of the present invention, receiving an external clock to generate a divided signal divided by m (m is a natural number of two or more), and generates at least one latency control clock from the divided signal A latency control clock generator, a latency control signal generated from at least one or more of the latency control clock and the cascade latency information, and a latency signal generator for generating a latency signal in response to an internal read command signal generated from a read command.
According to embodiments of the present disclosure, the latency signal generator may be configured to output or invert at least one latency control clock in response to the latency control signal as it is, and latch an internal read command in response to at least one latency control clock. A first shift register for generating a first latch signal, at least one switch for selectively transmitting the first latch signal according to cas latency information, and a first latch transmitted through the at least one switch in response to an output of the controller The second shift register may latch a signal to generate a second latch signal.
According to embodiments of the present invention, in response to the cascade latency information, the latency signal generator outputs a second latch signal as it is and provides it as a latency signal or delays the second latch signal by one clock of an external clock as a latency signal. It may further include a control unit for providing.
According to embodiments of the present disclosure, the controller may include a buffer for inputting at least one latency control clock in response to activation of the latency control signal, and an inverter for inputting at least one latency control clock in response to deactivation of the latency control signal. The latency control signal may be set to be inactivated when the cascade latency information is set to low frequency operation of the semiconductor memory device.
According to the embodiments of the present disclosure, the latency clock generator may include a delay lock loop for generating a phase lock signal synchronized with the external clock by inputting an external clock, a clock divider for splitting the phase lock signal by two, and generating a divided signal; Inputs the divided signal and compensates the delay time by the delay lock loop to generate an output signal synchronized with the external clock, and inputs the output signal of the delay lock loop copy unit, and an internal read command signal from the read command. And an internal read command signal generation copy unit configured to generate at least one latency control clock by compensating for a delay caused by the internal read command signal generator that generates.
In order to achieve the above object, the semiconductor memory device according to another aspect of the present invention, the internal read command signal generator for generating an internal read command signal in response to a read command synchronized with an external clock, and receives an external clock m (m is a natural number of 2 or more) a latency control clock generator for generating a divided divided signal and generating at least one latency control clock from the divided signal, a latency control signal generated from at least one latency control clock and cascade latency information, And a latency signal generator for generating a latency signal in response to the internal read command signal, and an output unit for controlling data output in response to the latency signal.
According to embodiments of the present invention, the latency control clock generation unit inputs an external clock to adjust a phase of a delayed synchronization loop and a phase locked signal generated in synchronization with the external clock, and phase shifting the phase shifting signal to a clock divider. A delayed synchronous loop for generating the divided signal by dividing the phase-controlled phase-synchronized signal by two, inputting the divided signal, and compensating the delay time by the delayed synchronous loop to generate an output signal synchronized with an external clock. The copy unit may include an internal read command signal generation copy unit configured to input an output signal of the delay sync loop copy unit and compensate for the delay caused by the internal read command signal generator to generate at least one latency control clock.
According to embodiments of the present invention, the semiconductor memory device may further include a delay copy circuit for delaying the phase lock signal by a predetermined time in order to synchronize the phase lock signal with the latency signal. In response to the output, it is possible to control the data output of the output unit.
According to the above-described latency circuit of the present invention, the PREAD replica has a constant margin with respect to the internal read command signal and generates a latency control clock using divided signals having a period twice as long as the external clock. This solves the problem of the internal read command signal not being latched normally due to an increase in the frequency or a change in the PVT.
In addition, the latency circuit generates a latency signal using a divided frequency latency control clock, but when it is set to a low frequency operation such as
In addition, the latency circuit generates a latency signal by using the divided division latency control clock, but when the cas latency is set to an odd multiple, the output signal of the shift register unit is output as it is, and the cas latency is set to an even multiple. The delay signal of the shift register section is delayed by one clock of the external clock and provided as a latency signal, so that the amount of delay of the latency signal according to cas latency can be adjusted.
In addition, since the latency circuit activates the latency signal before the operation of the data output buffer according to the cascade latency, it enables a read preamble set to prevent data collision.
Since the latency circuit provided to the output unit is generated after a predetermined time delay from the phase synchronization signal, a delay copy circuit for delaying the signal by a predetermined delay time in order to synchronize the phase synchronization signal with the latency signal is provided. And generating latency control clocks and latency signals based on the phase-inverted phase-locked signal to advance by half the period of the external clock. Accordingly, by reducing the number of delay stages in the delay copy circuit for delaying the phase locked signal, it is possible to improve the noise characteristics of the delay copy circuit and to prevent excessive current consumption from flowing in the delay copy circuit.
DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings that illustrate preferred embodiments of the present invention.
Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.
1 is a diagram illustrating a latency circuit according to an embodiment of the present invention. Referring to FIG. 1, the
The internal read
The
The latency control
The
The divided signal of any one of the even and odd divided signals is input to the
The output signal DOUT0_REP of the
The first latency control clock PLATCLK1_E for even output from the
On the other hand, the divided signal DIVCLK_E (O) is also provided to the
That is, the
The
The
In addition, since the latency control clock PLATCLK [1: n] _E (O) generated by the latency
FIG. 2 is a diagram for explaining another example of generating the first latency control clocks shown in FIG. 1. Referring to FIG. 2, a DLL replica and a PREAD replica may be separately provided for each of the two-dividing signals DIVCLK_E and DIVCLK_O to remove the odd /
The first PREAD replica 124_1 delays the output signal DOUT0_REP_E of the first DLL replica 123_1 to a predetermined value to generate a first latency control clock PLATCLK1_E for even. The second PREAD replica 124_2 delays the output signal DOUT0_REP_O of the second DLL replica 123_2 to a predetermined value to generate the first latency control clock PLATCLK1_O for the odd. The delayed predetermined value is a value depending on the phase difference between the external clock CLK and the internal read command signal PREAD, and compensates for the phase delayed by the internal read
The even first latency control clock PLATCLK1_E and the odd first latency control clock PLATCLK1_O are provided to the
3 is a diagram illustrating the
The internal read command signal PREAD and the latency control signal CL_CTRL are input to the
Each of the
When the internal read command signal PREAD is input to the input terminal of the first shift register, the first shift register shifts the internal read command signal PREAD in synchronization with the first latency control clock PLATCLK1_E for output. The output signal of the first shift register is input to the input terminal of the second shift register connected in series with the first shift register. The second shift register shifts the input signal in synchronization with the even second latency control clock PLATCLK2_E. The output signal of the second shift register is input to the input terminal of the third shift register. Through this process, an output signal of the nth shift register is generated.
The operation of the second
The
The reason for this configuration is that the internal read command signal PREAD is shifted using the latency control clock having twice the period compared to the external clock CLK in accordance with one embodiment of the present invention. Therefore, it is necessary to additionally adjust the shifting corresponding to one clock of the external clock CLK.
The
The
The
4 illustrates a
The SR2_E shifter register latches and outputs the first latch signal LAT_1st in response to the second latency control clock PLATCLK2_E for even when the cas latency information is 11 (CL11). The output of the SR2_E shifter register is input to the SR3_E shifter register.
The SR3_E shifter register inputs the output of the SR2_E shifter register or the first latch signal LAT_1st. The SR3_E shifter register latches and outputs the output of the SR2_E shifter register in response to the even third latency control clock (PLATCLK3_E) when the CAS latency information is 11 (CL11), and the CAS latency information is 9 or 10 (CL9). 10, the first latch signal LAT_1st is latched and output in response to the even third latency control clock PLATCLK3_E. The output of the SR3_E shifter register is input to the SR4_E shifter register.
The SR4_E shifter register inputs the output of the SR3_E shifter register or the first latch signal LAT_1st. The SR4_E shifter register latches and outputs the output of the SR3_E shifter register in response to the fourth latency control clock PLATCLK4_E for even when the cas latency information is 9, 10, or 11 (CL9, 10, CL11). The SR4_E shifter register latches and outputs the first latch signal LAT_1st in response to the fourth latency control clock PLATCLK4_E for even when the cas latency information is 7 or 8 (CL7, 8). The second latch signal LAT_2nd, which is an output of the SR4_E shifter register, is input to the SR5_E shifter register.
The SR5_E shifter register inputs the output of the SR4_E shifter register or the first latch signal LAT_1st. The SR5_E shifter register outputs the SR4_E shifter register in response to the fifth latency control clock (PLATCLK5_E) for even when the cas latency information is 7, 8, 9, 10, or 11 (CL7, 8, CL9, 10, CL11). Latch to output. The SR5_E shifter register latches and outputs the first latch signal LAT_1st in response to the fifth latency control clock PLATCLK5_E for even when the cas latency information is 6 (CL6). The SR5_E shifter register is configured to respond to the inverted signal of the even fifth latency control clock PLATCLK5_E, that is, the fifth latency control clock PLATCLK5_O for the first latch signal when the cas latency information is 5 (CL5). LAT_1st) is latched and output. The third latch signal LAT_3rd, which is an output of the SR5_E shifter register, is an output of the
In response to the latency control signal CL_CTRL, the
The first delay block 126_1 includes a plurality of delay elements DELAY connected in series, and inputs an even division signal DIVCLK_E to be delayed by a predetermined time by an even fifth latency control clock PLATCLK5_E and an even fourth latency. The control clock PLATCLK4_E, the third latency control clock PLATCLK3_E for even and the second latency control clock PLATCLK2_E for even are generated.
The
The
FIG. 5 is a timing diagram illustrating an operation when the
The even division signal DIVCLK_E generates an output signal DOUT0_REP of the
The read command READ input at the
The first latch signal LAT_1st is transferred to the SR5_E shift register through the SW4 switch and inverts the fifth latency control clock PLATCLK5_E for even by the logic low level latency control signal CTRL set at the
When set to
FIG. 6 is a timing diagram illustrating an operation when the
The first latch signal LAT_1 st is transferred to the SR4_E shift register through the SW3 switch. The SR4_E shift register latches the first latch signal LAT_1st in response to the fourth latency control clock PLATCLK4_E for output to output the second latch signal LAT_2nd. The SR5_E shifter register latches the second latch signal LAT_2nd in response to the fifth latency control clock PLATCLK5_E for output and outputs the third latch signal LAT_3rd. The third latch signal LAT_3rd is provided to the SR6_E shifter register through the SW6 switch. The SR6_E shift register latches and outputs the third latch signal LAT_3rd in response to the odd division signal DIVCLK_O. The output of the SR6_E shift register is generated as a latency signal LATENCY through the logic circuit OR1 and the logic element 135 (ⓝ).
When set to
5 and 6 illustrate examples in which the internal read command signal PREAD is latched by an even latency control clock. On the other hand, when the output signal DOUT0_REP of the
7 is a diagram illustrating a
The phase lock loops DLL and 221 in the latency control clock generator 220 of the
On the other hand, when the
The
Referring to FIG. 8, the phase adjuster 227 inputs a phase synchronization signal PDLL0 to output a signal PDLL0B that is out of phase with the phase synchronization signal PDLL0. The clock divider 122 'inputs the phase-adjusted signal PDLL0B, divides it, and outputs an even division signal DIVCLK_E'. The even divided signal DIVCLK_E 'is out of phase with the even divided signal DIVCLK_E output from the
FIG. 9 is a circuit diagram illustrating the
FIG. 10 is a timing diagram illustrating an operation of the
Although not shown in the timing diagram of FIG. 10, it is not necessary to invert the phase of the phase synchronization signal PDLL0 in adjusting the phase of the phase synchronization signal PDLL0. The phase of the phase synchronization signal PDLL0 may be adjusted to be smaller or larger than 180 degrees.
FIG. 11 is a partial block diagram of the
Accordingly, the delay amount of the
Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.
1 is a diagram illustrating a latency circuit according to an embodiment of the present invention.
FIG. 2 is a diagram for explaining another example of generating the first latency control clocks shown in FIG. 1.
3 is a diagram illustrating a latency signal generator and a delay block of FIG. 1.
FIG. 4 is a circuit diagram specifically illustrating a first shift register part, a second shift register part, a first adjuster, a second adjuster, a first delay block, and a second delay block of FIG. 3.
FIG. 5 is a timing diagram illustrating an operation when the latency circuit of FIG. 1 operates with
FIG. 6 is a timing diagram illustrating an operation when the latency circuit of FIG. 1 operates with
7 is a diagram illustrating a semiconductor memory device according to another embodiment of the present invention.
FIG. 8 is a diagram for explaining a phase adjusting unit for synchronizing a phase synchronizing signal to a latency signal at the output of FIG. 7.
FIG. 9 is a circuit diagram illustrating a phase adjuster and a clock divider of FIG. 8.
FIG. 10 is a timing diagram illustrating an operation of a phase adjuster and a clock divider of FIG. 9.
FIG. 11 is a partial block diagram illustrating a semiconductor memory device in which the number of delay stages in the delay copy circuit of FIG. 7 is reduced by using the phase adjuster of FIG. 8.
Explanation of symbols on the main parts of the drawings
100: latency circuit 110: internal read command signal generator
111: decoder 112: PREAD generator
120: latency control clock generator 121: delay synchronization loop
122: clock divider 123: DLL replica
124: PREAD replica 125: Aether / even separator
126: delay block 130: latency signal generator
200: semiconductor memory device 250: output unit
260: delayed
Claims (10)
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KR1020090081485A KR20110023533A (en) | 2009-08-31 | 2009-08-31 | Latency circuit for generating latency signal using 1-division or 2-division method and semiconductor memory device having the same |
US12/697,547 US8045406B2 (en) | 2006-10-31 | 2010-02-01 | Latency circuit using division method related to CAS latency and semiconductor memory device |
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KR1020090081485A KR20110023533A (en) | 2009-08-31 | 2009-08-31 | Latency circuit for generating latency signal using 1-division or 2-division method and semiconductor memory device having the same |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20140007040A (en) * | 2012-07-04 | 2014-01-16 | 에스케이하이닉스 주식회사 | Latency control circuit and semiconductor device including the circuit |
KR20170108454A (en) * | 2016-03-17 | 2017-09-27 | 에스케이하이닉스 주식회사 | Latency control device ans semiconductor device including the same |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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KR20140007040A (en) * | 2012-07-04 | 2014-01-16 | 에스케이하이닉스 주식회사 | Latency control circuit and semiconductor device including the circuit |
KR20170108454A (en) * | 2016-03-17 | 2017-09-27 | 에스케이하이닉스 주식회사 | Latency control device ans semiconductor device including the same |
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