KR102031201B1 - Latency control circuit and semiconductor memory device including the same - Google Patents
Latency control circuit and semiconductor memory device including the same Download PDFInfo
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- KR102031201B1 KR102031201B1 KR1020120149966A KR20120149966A KR102031201B1 KR 102031201 B1 KR102031201 B1 KR 102031201B1 KR 1020120149966 A KR1020120149966 A KR 1020120149966A KR 20120149966 A KR20120149966 A KR 20120149966A KR 102031201 B1 KR102031201 B1 KR 102031201B1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/225—Clock input buffers
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/22—Control and timing of internal memory operations
- G11C2207/2254—Calibration
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/22—Control and timing of internal memory operations
- G11C2207/2272—Latency related aspects
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
- H03K5/1565—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern the output pulses having a constant duty cycle
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Abstract
A circuit for controlling latency and a semiconductor memory device including the same, comprising: an internal command generator for generating an internal command in response to an external command, and an external clock delayed by an operation delay amount of the internal command generator; A clock delay unit for generating the command, a command synchronizer for generating a synchronization command by sequentially synchronizing an internal command with an internal clock and an external clock to compensate for an operation delay amount of the internal command generator, and a synchronization command based on an external clock. Provided is a latency control circuit having a latency shifting unit configured to shift by a set number of latency.
Description
BACKGROUND OF THE
BACKGROUND OF THE INVENTION A semiconductor memory device used as a main memory in a computer system inputs data into or outputs data from a memory cell. The data input / output speed of a semiconductor memory device is a very important factor in determining the operating speed of a computer system. In order to improve the operation speed of the semiconductor memory device, a synchronous dynamic random access memory device (SDRAM) in which internal circuits are controlled in synchronization with a clock signal generated from a computer system has been used.
In general, a synchronous semiconductor memory device (SDRAM) uses a column address strobe (CAS) function to increase an operating frequency. The cas latency represents the number of cycles of an external clock until a data is output to the outside after a read command is applied to the synchronous semiconductor memory device. The synchronous semiconductor memory device reads data internally in response to a read command, and then outputs data after a clock cycle corresponding to cas latency. For example, when the cas latency is 8, data is output to the outside in synchronization with the external clock 8 clock cycles after the external clock to which the read command is applied.
The latency control circuit generates a latency control signal that is an output control signal in order to control the output data to be output after a set clock cycle in the synchronous semiconductor memory device. In other words, the latency control circuit serves as an output control circuit. The data output buffer of the synchronous semiconductor memory device outputs data in response to an output clock signal while the latency control signal is activated. Therefore, the latency control circuit must provide the latency control signal after a read command is applied, but before a predetermined cycle of the output clock signal according to the cas latency.
The latency control signal is generated because the internal read command signal generated by decoding the read command is latched by the output clock signal and the clock signals delaying the read command. Typically, the pulse width of the internal read command signal corresponds to one period of the external clock, and the output clock signal is generated in response to a delay locked loop (DLL) clock generated through a delay locked loop, and Have the same frequency.
1 is a block diagram illustrating a latency control circuit of a semiconductor memory device according to the prior art.
Referring to FIG. 1, a latency control circuit of a semiconductor memory device according to the related art includes a delay locked
The
The
The
The command
The
The
FIG. 2 is a timing diagram illustrating an operation and a problem of a latency control circuit of the semiconductor memory device according to the related art shown in FIG. 1.
Referring to FIG. 2, the latency control circuit of the semiconductor memory device according to the related art decreases the latency margin as the operating frequency of the clock CLK applied from the outside increases.
First, the operation of a latency control circuit of a semiconductor memory device according to the related art in a state where an operating frequency of an external clock CLK is relatively low is as follows.
The clock CLK and the external clock ICLK applied from the outside have a phase difference by the buffering delay amount tD1.
The externally applied command CMD and the external command ICMD have a phase difference by the buffering delay amount tD1.
The external clock ICLK and the delay locked clock DLLCLK have a phase difference by the variable delay amount tD3.
The external command ICMD and the internal command ICMD_A have a phase difference by the operation delay amount tD2 of the internal
The internal command ICMD_A and the variable delay command ICMD_R have a phase difference by the variable delay amount tD3.
The latency control signal LT_CON is generated by shifting the variable delay command ICMD_R by the CAS latency CL or the CAS write latency CWL based on the delay lock clock DLLCLK. At this time, shifting the variable delay command ICMD_R based on the delay locked clock DLLCLK detects and transmits the logic level of the variable delay command ICMD_R in the logic 'high' section of the delay locked clock DLLCLK. It means the way.
Accordingly, as shown in the drawing, the frequency of the clock CLK applied from the outside becomes a low frequency so that the logic 'high' section of the delay lock clock DLLCLK and the variable delay command ICMD_R In a state where logic 'low' sections overlap sufficiently, a latency shift operation may be performed without any problem.
The operation of the latency control circuit of the semiconductor memory device according to the related art in the state in which the operating frequency of the clock CLK applied from the outside is relatively high is as follows.
The clock CLK and the external clock ICLK applied from the outside have a phase difference by the buffering delay amount tD1.
The externally applied command CMD and the external command ICMD have a phase difference by the buffering delay amount tD1.
The external clock ICLK and the delay locked clock DLLCLK have a phase difference by the variable delay amount tD3.
The external command ICMD and the internal command ICMD_A have a phase difference by the operation delay amount tD2 of the internal
The internal command ICMD_A and the variable delay command ICMD_R have a phase difference by the variable delay amount tD3.
The latency control signal LT_CON is generated by shifting the variable delay command ICMD_R by the CAS latency CL or the CAS write latency CWL based on the delay lock clock DLLCLK. At this time, shifting the variable delay command ICMD_R based on the delay locked clock DLLCLK detects and transmits the logic level of the variable delay command ICMD_R in the logic 'high' section of the delay locked clock DLLCLK. It means the way.
However, as shown in the drawing, the frequency of the clock CLK applied from the outside becomes high frequency, so that the logic 'high' section of the delay lock clock DLLCLK and the variable delay command ICMD_R In a state where logic 'low' sections do not overlap sufficiently, a latency shift operation may not be performed normally.
As described above, as the frequency of the clock CLK applied from the outside increases, the margin between the variable delay command ICMD_R applied to the
In this way, if the margin between the variable delay command ICMD_R and the delay locked clock DLLCLK becomes small or the phase of the delay locked clock DLLCLK is earlier than the pulse width of the variable delay command ICMD_R, the variable delay command Since the ICMD_R is not normally latched, a problem may occur in which proper shifting may not be performed according to the CAS latency or the CAS write latency CWL.
The present invention relates to a circuit for controlling latency that can stably perform a latency shifting operation regardless of a change in frequency, and a semiconductor memory device including the same.
That is, the present invention relates to a circuit for controlling latency that can stably perform a latency shifting operation even when a clock frequency is relatively low as well as a relatively high frequency, and a semiconductor memory device including the same.
According to an aspect of the present invention for achieving the above object, an internal command generation unit for generating an internal command in response to an external command; A clock delay unit configured to delay an external clock by an operation delay amount of the internal command generator to generate an internal clock; A command synchronizer configured to sequentially synchronize the internal command with the internal clock and the external clock to compensate for an operation delay amount of the internal command generator; And a latency shifting unit configured to shift the synchronization command by a set number of times of latency based on the external clock.
According to another aspect of the present invention for achieving the problem to be solved, variable delay the external clock to achieve a delay between the clock and the external clock generated by reflecting the delay amount of the clock delay path in the delay lock clock A delay lock loop outputting the delay lock clock as the delay lock clock; An internal command generator for generating an internal command in response to the external command; A clock delay unit configured to delay the external clock by an operation delay amount of the internal command generator to generate an internal clock; A command synchronizer configured to sequentially synchronize the internal command with the internal clock and the external clock to compensate for an operation delay amount of the internal command generator; A command variable delay unit for delaying the synchronization command by a variable delay amount of the delay locked loop; A latency shifting unit configured to generate a latency control signal by shifting the output command of the variable delay unit based on the delay locked clock by a set latency; And an output controller configured to control data output in response to the latency control signal and the delay locked clock.
According to another aspect of the present invention for achieving the above object, the external clock is variable to achieve a delay between the external clock and the feedback clock generated by reflecting the delay amount of the clock delay path in the delay lock clock A delay locked loop for delaying and outputting the delay locked clock; A duty compensator for correcting the duty ratio of the delay locked clock and outputting the duty ratio as a duty correction clock; An internal command generator for generating an internal command in response to the external command; A command variable delay unit generating a variable delay command by delaying the internal command by a variable delay amount of the delay locked loop; A clock delay unit configured to delay the duty compensation clock by an amount of a delay obtained by subtracting an operation delay amount of the duty correction unit from an operation delay amount of the internal command generator; A command synchronizing unit generating a synchronizing command by sequentially synchronizing the variable delay command with the internal clock and the duty compensation clock to compensate for an operation delay amount of the internal command generating unit; A latency shifting unit configured to generate a latency control signal by shifting the synchronization command by a set latency based on the duty compensation clock; And an output controller configured to control data output in response to the latency control signal and the duty cycle correction clock.
The present invention described above adds a circuit for compensating for the delay amount of the command decoder which is an asynchronous element to the clock during the command transfer path, so that the interval between the clock and the command used for latency shifting is always based on the clock period. It is effective to maintain a constant interval.
Accordingly, there is an effect that the latency shifting operation can be stably performed regardless of the frequency of the clock, that is, the clock frequency is relatively low as well as relatively high.
1 is a block diagram illustrating a latency control circuit of a semiconductor memory device according to the prior art.
FIG. 2 is a timing diagram illustrating an operation and a problem of a latency control circuit of the semiconductor memory device according to the related art shown in FIG. 1.
3 is a block diagram illustrating a latency control circuit according to an embodiment of the present invention.
4 is a diagram illustrating in detail a clock delay unit and a command synchronizer among components of a latency control circuit according to the embodiment of the present invention shown in FIG. 3.
FIG. 5 is a timing diagram illustrating an operation of a latency control circuit according to the embodiment of the present invention shown in FIG. 3.
6 is a block diagram illustrating a semiconductor memory device including a latency control circuit according to a first embodiment of the present invention.
FIG. 7 is a detailed diagram illustrating a clock delay unit and a command synchronizer among components of a semiconductor memory device including a latency control circuit according to the first embodiment of the present invention illustrated in FIG. 6.
FIG. 8 is a timing diagram illustrating an operation of a semiconductor memory device including a latency control circuit according to the first embodiment of the present invention illustrated in FIG. 6.
9 is a block diagram illustrating a semiconductor memory device including a latency control circuit according to a second embodiment of the present invention.
FIG. 10 is a detailed diagram illustrating a clock delay unit and a command synchronizer among components of a semiconductor memory device including a latency control circuit according to the second embodiment of the present invention illustrated in FIG. 9.
Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be configured in various different forms, only this embodiment is intended to complete the disclosure of the present invention and to those skilled in the art the scope of the present invention It is provided to inform you completely.
3 is a block diagram illustrating a latency control circuit according to an embodiment of the present invention.
Referring to FIG. 3, a latency control circuit according to an embodiment of the present invention may include an
The
The
The
The
The
4 is a diagram illustrating in detail a clock delay unit and a command synchronizer among components of a latency control circuit according to the embodiment of the present invention shown in FIG. 3.
Referring to FIG. 4, the
Specifically, since the first internal clock DCLK [1] of the N internal clocks DCLK [1: N] is assumed to be the same clock as the external clock ICLK, the delay element included in the
In this case, the N-1
The
FIG. 5 is a timing diagram illustrating an operation of a latency control circuit according to the embodiment of the present invention shown in FIG. 3.
Referring to FIG. 5, in the latency control circuit according to an exemplary embodiment of the present invention, the interval between the synchronization command ICMD_S and the external clock ICLK applied to the
It can be seen that the external clock ICLK is delayed in steps to generate a total of three internal clocks DCLK [1: 3] at intervals equal to the operation delay amount tD2 of the
The internal command ICMD_A output from the
Subsequently, the first synchronization command FCM [1] is output as the second synchronization command FCM [2] in response to the second internal clock DCLK [2]. That is, in the period in which the first synchronization command FCM [1] is input, the second synchronization command FCM [2] for one period 1tck at the time corresponding to the rising edge of the second internal clock DCLK [2]. Is output as
Finally, the second synchronization command FCM [2] is output as the third synchronization command ICMD_S in response to the first internal clock DCLK [1]. That is, during the period in which the second synchronization command FCM [2] is input, the third synchronization command ICMD_S is output for one period 1tck at the time corresponding to the rising edge of the first internal clock DCLK [1]. do.
In this case, since the first internal clock DCLK [1] has the same phase as the external clock ICLK, it can be seen that the third synchronization command ICMD_S is synchronized with the external clock ICLK.
Accordingly, it can be seen that the interval between the synchronization command ICMD_S applied to the
In summary, in the latency control circuit according to the embodiment of the present invention, an operation for compensating an operation delay amount of the
6 is a block diagram illustrating a semiconductor memory device including a latency control circuit according to a first embodiment of the present invention.
Referring to FIG. 6, a semiconductor memory device including a latency control circuit according to a first embodiment of the present invention may include a delay locked
The
The
The
The
The
The command
The
The
FIG. 7 is a detailed diagram illustrating a clock delay unit and a command synchronizer among components of a semiconductor memory device including a latency control circuit according to the first embodiment of the present invention illustrated in FIG. 6.
Referring to FIG. 7, the
Specifically, since the first internal clock DCLK [1] of the N internal clocks DCLK [1: N] is assumed to be the same clock as the external clock ICLK, the delay elements included in the
In this case, the N-1
The
FIG. 8 is a timing diagram illustrating an operation of a semiconductor memory device including a latency control circuit according to the first embodiment of the present invention illustrated in FIG. 6.
Referring to FIG. 8, in the semiconductor memory device including the latency control circuit according to the first embodiment of the present invention, an interval between the variable delay command ICMD_R and the delay locked clock DLLCLK applied to the
It can be seen that the external clock ICLK is delayed in steps to generate a total of three internal clocks DCLK [1: 3] at intervals equal to the operation delay amount tD2 of the
The internal command ICMD_A output from the
Subsequently, the first synchronization command FCM [1] is output as the second synchronization command FCM [2] in response to the second internal clock DCLK [2]. That is, in the period in which the first synchronization command FCM [1] is input, the second synchronization command FCM [2] for one period 1tck at the time corresponding to the rising edge of the second internal clock DCLK [2]. Is output as
Finally, the second synchronization command FCM [2] is output as the third synchronization command ICMD_S in response to the first internal clock DCLK [1]. That is, during the period in which the second synchronization command FCM [2] is input, the third synchronization command ICMD_S is output for one period 1tck at the time corresponding to the rising edge of the first internal clock DCLK [1]. do.
In this case, since the first internal clock DCLK [1] has the same phase as the external clock ICLK, it can be seen that the third synchronization command ICMD_S is synchronized with the external clock ICLK.
The delay lock clock DLLCLK is a clock generated by delaying the external clock ICLK by the variable delay amount tD3, and the variable delay command ICMD_R delays the third synchronization command ICMD_S by the variable delay amount tD3. The third synchronization command ICMD_S and the delay lock clock DLLCLK are also synchronized.
Accordingly, it can be seen that the interval between the variable delay command ICMD_R and the delay locked clock DLLCLK applied to the
In summary, the latency control circuit according to the above-described embodiment of the present invention has an operation for compensating an operation delay amount of the
9 is a block diagram illustrating a semiconductor memory device including a latency control circuit according to a second embodiment of the present invention.
Referring to FIG. 9, a semiconductor memory device including a latency control circuit according to a second embodiment of the present invention includes a delay locked
The
The
The
The command
The duty
When the external command ICMD output through the
That is, in the general semiconductor memory device, after determining that the clock enable command is CKE through the
As such, the purpose of turning on / off the operation of the
In addition, the
Referring to this matter, the
The
The
The
FIG. 10 is a detailed diagram illustrating a clock delay unit and a command synchronizer among components of a semiconductor memory device including a latency control circuit according to the second embodiment of the present invention illustrated in FIG. 9.
Referring to FIG. 10, the
Specifically, since the first internal clock DCLK [1] of the N internal clocks DCLK [1: N] is assumed to be the same clock as the duty correction clock DCCCLK, a delay included in the
In this case, the N-1
The
FIG. 11 is a timing diagram illustrating an operation of a semiconductor memory device including a latency control circuit according to the second embodiment of the present invention illustrated in FIG. 9.
Referring to FIG. 11, in a semiconductor memory device including a latency control circuit according to a second embodiment of the present invention, an interval between a variable delay command ICMD_R and a duty compensation clock DCCCLK applied to the
The duty correction clock DCCCLK may be delayed in steps to generate a total of three internal clocks DCLK [1: 3] at intervals equal to the operation delay amount tD2 of the
The variable delay command ICMD_R output from the command
Subsequently, the first synchronization command FCM [1] is output as the second synchronization command FCM [2] in response to the second internal clock DCLK [2]. That is, in the period in which the first synchronization command FCM [1] is input, the second synchronization command FCM [2] for one period 1tck at the time corresponding to the rising edge of the second internal clock DCLK [2]. Is output as
Finally, the second synchronization command FCM [2] is output as the third synchronization command ICMD_S in response to the first internal clock DCLK [1]. That is, during the period in which the second synchronization command FCM [2] is input, the third synchronization command ICMD_S is output for one period 1tck at the time corresponding to the rising edge of the first internal clock DCLK [1]. do.
At this time, since the first internal clock DCLK [1] has the same phase as the duty correction clock DCCCLK, it can be seen that the third synchronization command ICMD_S is synchronized with the duty compensation clock DCCCLK.
Accordingly, it can be seen that the interval between the variable delay command ICMD_R applied to the
In summary, in the latency control circuit according to the embodiment of the present invention, an operation for compensating an operation delay amount of the
The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill.
100, 600, 900: delay locked loop
110, 310, 610, 910: internal command generation unit
320, 620, 920: clock delay unit
340, 640, 940: command synchronization unit
150, 650, 950: command variable delay unit
160, 360, 660, 960: latency shifting part
170, 370, 670, 970: buffer part
180, 680, 980: output control unit
990: duty control unit
Claims (23)
A clock delay unit configured to delay an external clock by an operation delay amount of the internal command generator to generate an internal clock;
A command synchronizer configured to sequentially synchronize the internal command with the internal clock and the external clock to compensate for an operation delay amount of the internal command generator; And
Latency shifting unit for shifting the synchronization command by a set number of latency based on the external clock
Latency control circuit having a.
The clock delay unit,
Delaying the external clock stepwise to generate the internal clock of N, wherein N is a natural number greater than 2, wherein a phase difference between the external clock and the Nth internal clock corresponds to an amount of operation delay of the internal command generator; Latency control circuit.
The command synchronization unit,
The first internal clock-the external in such a manner that the internal command is synchronized with the Nth internal clock of the N internal clocks, and the command synchronized with the Nth internal clock is synchronized with the N-1th internal clock again. A latency control circuit that generates a synchronization command by sequentially synchronizing to have the same phase as a clock.
The command synchronization unit,
In response to the Nth internal clock applied to the clock input terminal of the first flip-flop, the internal command applied to the signal input terminal is transmitted to the signal output terminal, and the N-1th internal clock applied to the clock input terminal of the second flip-flop is provided. And the N flip-flops are provided in such a manner as to transmit a command on the signal output terminal of the first flip-flop applied to the signal input terminal in response to the signal output terminal.
The set latency count is
The latency control circuit, characterized in that the number of times the number is subtracted from the target latency.
The internal command generation unit,
A command decoding unit which generates the internal command by decoding the external command; And
And an additional latency shifting unit configured to shift the internal command decoded based on the external clock by an additional number of latency.
A command buffer unit which buffers a command applied from the outside and transfers the command to the internal command generation unit as the external command; And
And a clock buffer unit configured to buffer an externally applied clock and provide the additional latency shifting unit, the clock delay unit, and the latency shifting unit as the external clock.
An internal command generator for decoding an external command to generate an internal command;
A clock delay unit configured to delay the external clock by an operation delay amount of the internal command generator to generate an internal clock;
A command synchronizer configured to sequentially synchronize the internal command with the internal clock and the external clock to compensate for an operation delay amount of the internal command generator;
A command variable delay unit for delaying the synchronization command by a variable delay amount of the delay locked loop;
A latency shifting unit configured to generate a latency control signal by shifting the output command of the variable delay unit based on the delay locked clock by a set latency; And
An output control unit controlling data output in response to the latency control signal and the delay lock clock
A semiconductor memory device having a.
The clock delay unit,
Delaying the external clock stepwise to generate the internal clock of N, wherein N is a natural number greater than 2, wherein a phase difference between the external clock and the Nth internal clock corresponds to an amount of operation delay of the internal command generator; A semiconductor memory device.
The command synchronization unit,
The first internal clock-the external in such a manner that the internal command is synchronized with the Nth internal clock of the N internal clocks, and the command synchronized with the Nth internal clock is synchronized with the N-1th internal clock again. And having the same phase as a clock to sequentially generate the synchronization command.
The command synchronization unit,
In response to the Nth internal clock applied to the clock input terminal of the first flip-flop, the internal command applied to the signal input terminal is transmitted to the signal output terminal, and the N-1th internal clock applied to the clock input terminal of the second flip-flop is provided. N flip-flops are provided in such a manner as to transmit a command on the signal output terminal of the first flip-flop applied to the signal input terminal in response to the signal output terminal.
The set latency count is
And a number of times the N is subtracted from a target latency number.
The internal command generation unit,
A command decoding unit which generates the internal command by decoding the external command; And
And an additional latency shifting unit configured to shift the internal command decoded based on the external clock by an additional number of latency.
A command buffer unit which buffers a command applied from the outside and transfers the command to the internal command generation unit as the external command; And
And a clock buffer unit configured to buffer an externally applied clock to provide the delay locked loop, the additional latency shifting unit, and the clock delay unit as the external clock.
A duty compensator for correcting the duty ratio of the delay locked clock and outputting the duty ratio as a duty correction clock;
An internal command generator for decoding an external command to generate an internal command;
A command variable delay unit generating a variable delay command by delaying the internal command by a variable delay amount of the delay locked loop;
A clock delay unit configured to delay the duty compensation clock by an amount of a delay obtained by subtracting an operation delay amount of the duty correction unit from an operation delay amount of the internal command generator;
A command synchronizing unit generating a synchronizing command by sequentially synchronizing the variable delay command with the internal clock and the duty compensation clock to compensate for an operation delay amount of the internal command generating unit;
A latency shifting unit configured to generate a latency control signal by shifting the synchronization command by a set latency based on the duty compensation clock; And
An output control unit controlling data output in response to the latency control signal and the duty cycle correction clock;
A semiconductor memory device having a.
The clock delay unit,
Delaying the duty-correction clock stepwise to generate the internal clocks of N, wherein N is a natural number greater than 2, wherein a phase difference between the duty-correction clock and the N-th internal clock is determined by an operation delay of the internal command generator. And a delay amount corresponding to a delay amount obtained by subtracting an operation delay amount of the duty corrector.
The command synchronization unit,
Synchronizing the variable delay command to the Nth internal clock of the N internal clocks, and synchronizing the command synchronized to the Nth internal clock to the N-1th internal clock again. And having the same phase as the duty-correction clock to sequentially synchronize to generate the synchronization command.
The command synchronization unit,
In response to the N-th internal clock applied to the clock input terminal of the first flip-flop, the variable delay command applied to the signal input terminal is transmitted to the signal output terminal, and the N-th internal part is applied to the clock input terminal of the second flip-flop. N flip-flops are provided in such a manner as to transfer a command on the signal output terminal of the first flip-flop applied to the signal input terminal in response to a clock to the signal output terminal.
The set latency count is
And a number of times the N is subtracted from a target latency number.
The internal command generation unit,
A command decoding unit which generates the internal command by decoding the external command; And
And an additional latency shifting unit configured to shift the internal command decoded based on the external clock by an additional number of latency.
A command buffer unit which buffers a command applied from the outside and transfers the command to the internal command generation unit as the external command; And
And a clock buffer unit configured to buffer an externally applied clock and provide the external clock to the delay locked loop and the additional latency shifting unit as the external clock.
And in response to the external command buffered through the command buffer unit being a clock enable command, the operation of the duty compensator is controlled on / off.
The duty compensator,
A duty ratio adjusting unit receiving the delay lock clock to adjust a duty ratio thereof, the duty ratio of which is controlled on / off in response to the clock enable command; And
And a clock driver configured to drive the output clock of the duty ratio controller as the duty compensation clock to transmit the clock delay unit, the command synchronizer, the latency shifting unit, and the output controller.
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