KR20100078496A - Method for fabricating capacitor of semiconductor device - Google Patents

Method for fabricating capacitor of semiconductor device Download PDF

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KR20100078496A
KR20100078496A KR1020080136775A KR20080136775A KR20100078496A KR 20100078496 A KR20100078496 A KR 20100078496A KR 1020080136775 A KR1020080136775 A KR 1020080136775A KR 20080136775 A KR20080136775 A KR 20080136775A KR 20100078496 A KR20100078496 A KR 20100078496A
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layer
forming
lower electrode
titanium
titanium oxide
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KR1020080136775A
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Korean (ko)
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송한상
박종범
박종국
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02186—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing titanium, e.g. TiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02189—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing zirconium, e.g. ZrO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H01L21/02329—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen
    • H01L21/02332—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen into an oxide layer, e.g. changing SiO to SiON
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers

Abstract

PURPOSE: A method for fabricating the capacitor of a semiconductor device is provided to suppress the deterioration of a dielectric layer during an upper electrode deposition process by preventing the penetration of ammonia into a lower titanium oxide layer using a capping layer. CONSTITUTION: A metal lower electrode is formed on a semiconductor substrate. A dielectric layer including a titanium oxide layer(435) is formed on the lower electrode. A capping layer(450) includes titanium nitride. The capping layer covers the dielectric layer and protects the titanium oxide layer from a reduction reaction. Titanium nitride is deposited on the capping layer in order to form an upper electrode(470).

Description

반도체 소자의 커패시터 형성 방법{Method for fabricating capacitor of semiconductor device}Method for fabricating capacitor of semiconductor device

본 발명은 반도체 소자에 관한 것으로, 특히, 정전 용량을 확보할 수 있는 커패시터(capacitor) 형성 방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to a method of forming a capacitor capable of securing a capacitance.

반도체 메모리(memory) 소자의 집적도가 증가하고 디자인 룰(design rule)이 급격히 축소됨에 따라, 단위 메모리 셀(cell) 면적이 크게 감소하고 있어 제한된 면적 내에 보다 큰 커패시턴스(capacitance)를 확보할 수 있는 커패시터 형성 방법의 개발이 요구되고 있다. 셀 트랜지스터(cell transistor) 및 셀 커패시터(cell capacitor)가 단위 메모리 셀(memory cell)을 구성하는 디램(DRAM) 소자에서, 신뢰성 있는 기억 소자의 동작을 위해 25fF/셀 이상의 정전용량 값이 요구되고 있다. As the integration density of semiconductor memory devices increases and design rules sharply decrease, the unit memory cell area is greatly reduced, so that a capacitor having greater capacitance within a limited area can be obtained. The development of the formation method is called for. In DRAM devices, in which cell transistors and cell capacitors constitute a unit memory cell, capacitance values of 25 fF / cell or more are required for reliable memory device operation. .

60㎚ 급 이하의 디램 공정에서 이러한 정전용량을 확보하기 위한 등가산화막의 두께는 8Å 이하로 요구되고 있다. 등가산화막 두께(Tox)를 감소시키기 위해 유전상수 k가 보다 큰 물질을 유전층으로 이용하고자 하는 시도들이 이루어지고 있다. 그런데, 상부 전극을 증착하는 과정 중에 수반되는 환원 반응에 의해 이러한 유전층의 물성이 열화되고 있어, 커패시터의 정전용량 증가에 제약이 되고 있다. In the DRAM process of 60 nm or less, the equivalent oxide film for securing such capacitance is required to be 8 kPa or less. Attempts have been made to use a material having a larger dielectric constant k as the dielectric layer in order to reduce the equivalent oxide thickness T ox . However, the physical properties of the dielectric layer are deteriorated by the reduction reaction accompanying the process of depositing the upper electrode, which is a limitation in increasing the capacitance of the capacitor.

본 발명은 상부 전극 증착 시 환원 반응에 의한 유전층의 특성 열화를 억제할 수 있는 반도체 소자의 커패시터 형성 방법을 제시하고자 한다.An object of the present invention is to provide a method of forming a capacitor of a semiconductor device capable of suppressing deterioration of characteristics of a dielectric layer due to a reduction reaction during deposition of an upper electrode.

본 발명의 일 관점은, 반도체 기판 상에 금속 하부 전극을 형성하는 단계; 상기 하부 전극 상에 티타늄산화물(TiO2)층을 포함하는 유전층을 형성하는 단계; 상기 유전층을 덮어 상기 티타늄산화물(TiO2)층을 환원 반응으로부터 보호하는 캡층(capping layer)을 티타늄산질화물(TiON)을 포함하여 형성하는 단계; 및 상기 캡층 상에 티타늄질화물(TiN)을 증착하여 상부 전극을 형성하는 단계를 포함하는 반도체 소자의 커패시터 형성 방법을 제시한다. One aspect of the invention, forming a metal lower electrode on a semiconductor substrate; Forming a dielectric layer including a titanium oxide (TiO 2 ) layer on the lower electrode; Forming a capping layer including titanium oxynitride (TiON) covering the dielectric layer to protect the titanium oxide (TiO 2 ) layer from a reduction reaction; And depositing titanium nitride (TiN) on the cap layer to form an upper electrode.

상기 금속 하부 전극을 형성하는 단계는 상기 반도체 기판 상에 절연층을 형성하는 단계; 상기 절연층을 관통하는 하부 전극용 콘택을 도전성 폴리실리콘(polysilicon)을 포함하여 형성하는 단계; 상기 절연층 상에 상기 하부 전극용 콘택에 정렬되는 오프닝홀(opening hole)을 가지는 몰드(mold)층을 형성하는 단계; 상기 오프닝홀의 프로파일(profile)을 따르는 금속층을 형성하는 단계; 및 상기 금속층을 화학기계적연마(CMP)로 평탄화하여 상기 하부 전극으로 분리하는 단계를 포함하여 수행될 수 있다. The forming of the metal lower electrode may include forming an insulating layer on the semiconductor substrate; Forming a contact for the lower electrode penetrating the insulating layer, including conductive polysilicon; Forming a mold layer on the insulating layer, the mold layer having an opening hole aligned with the contact for the lower electrode; Forming a metal layer along a profile of the opening hole; And planarizing the metal layer by chemical mechanical polishing (CMP) to separate the metal layer into the lower electrode.

상기 유전층을 형성하는 단계는 상기 티타늄산화물(TiO2)층의 하부층으로 지 르코늄산화물(ZrO2)층을 원자층증착(ALD)하는 단계를 더 포함할 수 있다. The forming of the dielectric layer may further include atomic layer deposition (ALD) of a zirconium oxide (ZrO 2 ) layer as a lower layer of the titanium oxide (TiO 2 ) layer.

상기 티타늄산화물(TiO2)층은 Ti[N(CH3)2]4 또는 Ti[OCH(CH3)2]4를 티타늄 소스로 이용하고 오존(O3)을 산화제로 이용하여 원자층증착(ALD)될 수 있다. The titanium oxide (TiO 2 ) layer is formed by atomic layer deposition using Ti [N (CH 3 ) 2 ] 4 or Ti [OCH (CH 3 ) 2 ] 4 as a titanium source and ozone (O 3 ) as an oxidant. ALD).

상기 캡층을 형성하는 단계는 질소 가스 또는 질소 가스 및 산소 가스의 혼합 가스의 플라즈마(plasma)를 이용하여 상기 티타늄산화물(TiO2)층의 표면을 질화시켜 상기 티타늄산질화물(TiON)층을 형성하는 단계를 포함할 수 있다. In the forming of the cap layer, the surface of the titanium oxide (TiO 2 ) layer is nitrided using a plasma of nitrogen gas or a mixed gas of nitrogen gas and oxygen gas to form the titanium oxynitride (TiON) layer. It may include a step.

본 발명의 실시예는 상부 전극 증착 시 환원 반응에 의한 유전층의 특성 열화를 억제할 수 있는 반도체 소자의 커패시터 형성 방법을 제시할 수 있다. Embodiments of the present invention may provide a method of forming a capacitor of a semiconductor device capable of suppressing deterioration of characteristics of a dielectric layer due to a reduction reaction during deposition of an upper electrode.

본 발명의 실시예는 티타늄산화물(TiO2)층을 유전층으로 증착 후, 인시튜(insitu)로 플라즈마 표면 처리(plasma treatment)를 실시하여 TiO2 표면을 티타늄산질화물(TiON)로 개질 시킨다. TiON층은 유전층의 캡층(capping layer)으로 작용하여 티타늄질화물(TiN)의 상부 전극 증착시 암모니아(NH3)분위기에 의해 일부가 환원 되어 TiN으로 질화 되게 된다. 이와 같이 TiON층이 질화되므로, 하부의 TiO2층에 대한 환원 반응은 TiON 캡층에 의해 방지 및 억제되게 된다. 따라서, TiO2층의 물성 변화를 방지하여 커패시터 유전층의 전기적 특성 열화를 방지 할 수 있다. According to an embodiment of the present invention, the titanium oxide (TiO 2 ) layer is deposited as a dielectric layer, and then plasma surface treatment is performed in situ to modify the TiO 2 surface with titanium oxynitride (TiON). The TiON layer acts as a capping layer of the dielectric layer and is partially reduced by the ammonia (NH 3 ) atmosphere when the upper electrode is deposited with titanium nitride (TiN) to be nitrided into TiN. Since the TiON layer is nitrided as described above, the reduction reaction to the lower TiO 2 layer is prevented and suppressed by the TiON cap layer. Therefore, it is possible to prevent a change in the physical properties of the TiO 2 layer to prevent deterioration of electrical characteristics of the capacitor dielectric layer.

도 1 내지 도 4는 본 발명의 실시예에 따른 반도체 소자의 커패시터 형성 방법을 보여주는 단면도들이다. 1 to 4 are cross-sectional views illustrating a method of forming a capacitor of a semiconductor device according to an embodiment of the present invention.

도 1을 참조하면, 반도체 기판(100) 상에 디램 소자의 메모리 셀(memory cell)을 구성하는 셀 트랜지스터(cell transistor)를 형성하는 과정을 수행한다. 예컨대, 반도체 기판(100)에 얕은트렌치소자분리(STI: Shallow Trench Isolation) 과정을 수행하고, 활성 영역 상에 트랜지스터(도시되지 않음)를 구현한 후, 트랜지스터를 덮는 절연층(200)을 하부층으로 형성한다. 절연층(200)을 관통하는 연결 콘택(contact)을 위한 콘택홀(contact hole: 201)을 형성한 후, 콘택홀(201)을 채우는 도전성 폴리실리콘(polysilicon)을 증착하여 하부 전극용 콘택(storage node contact: 250)을 형성한다. Referring to FIG. 1, a process of forming a cell transistor constituting a memory cell of a DRAM device on a semiconductor substrate 100 is performed. For example, after performing shallow trench isolation (STI) on the semiconductor substrate 100 and implementing a transistor (not shown) on the active region, the insulating layer 200 covering the transistor is a lower layer. Form. After forming a contact hole 201 for a connection contact penetrating the insulating layer 200, a conductive polysilicon filling the contact hole 201 is deposited to deposit a lower electrode. node contact: 250).

하부 전극용 콘택(250)을 상에 식각 정지층(etch stop layer: 310)을 형성하고, 커패시터의 하부 전극에 오목한 실린더(cylinder) 형상을 부여하기 위한 몰드층(mold layer: 330)을 희생층으로 형성한다. 식각 정지층(310)은 몰드층(330)의 패터닝(patterning)을 위한 선택적 식각 시 식각 종료점으로 작용하게, 몰드층(330)을 이루는 실리콘 산화물(SiO2)층과 식각 선택비를 가지는 절연 물질, 예컨대, 실리콘 질화물(Si3N4)을 포함하여 형성될 수 있다. An etch stop layer 310 is formed on the lower electrode contact 250, and a mold layer 330 is formed to impart a concave cylinder shape to the lower electrode of the capacitor. To form. The etch stop layer 310 is an insulating material having an etch selectivity with a silicon oxide (SiO 2 ) layer constituting the mold layer 330 to serve as an etch termination point during the selective etching for the patterning of the mold layer 330. For example, it may be formed including silicon nitride (Si 3 N 4 ).

몰드층(330)을 관통하는 오프닝홀(opening hole: 301)을 선택적 식각 과정으로 형성한다. 이러한 오프닝홀(301)의 프로파일(profile)을 따라 오목한 부분을 가지는 실린더(cylinder) 형상의 하부 전극(410)을 형성한다. 하부 전극(410)을 위한 금속층, 예컨대, 티타늄질화물(TiN)층을 증착하고, 화학기계적연마(CMP)를 이용한 평탄화 과정으로 노드 분리(node separation)를 수행하여 하부 전극(410)을 형성한다. 하부 전극(410)은 MIM(Metal Insulator Metal) 구조의 커패시터 구조에 따라 금속층을 포함하여 형성될 수 있다. 하부 전극(410)은 대략 100Å 내지 300Å 정도 두께로 TiN층을 증착하여 형성될 수 있다. TiN층은 티타늄(Ti)층을 장벽 금속층으로 수반할 수 있으며, 증착된 Ti층은 하부의 폴리실리콘 하부 전극용 콘택(250)과 실리사이드(silicide) 반응하여 티타늄실리사이드(TiSix)의 계면층(415)을 형성할 수 있다. 이러한 계면층(415)에 의해 접촉 저항의 감소를 구현할 수 있다. An opening hole 301 penetrating the mold layer 330 is formed by a selective etching process. A cylindrical lower electrode 410 having a concave portion is formed along the profile of the opening hole 301. A metal layer, for example, a titanium nitride (TiN) layer, is deposited for the lower electrode 410, and node separation is performed by planarization using chemical mechanical polishing (CMP) to form the lower electrode 410. The lower electrode 410 may be formed including a metal layer according to a capacitor structure of a metal insulator metal (MIM) structure. The lower electrode 410 may be formed by depositing a TiN layer having a thickness of about 100 μs to 300 μs. The TiN layer may be accompanied by a titanium (Ti) layer as a barrier metal layer, and the deposited Ti layer is silicide-reacted with the contact polysilicon lower electrode contact 250 at the bottom to form an interface layer of titanium silicide (TiSi x ). 415 may be formed. The interface layer 415 may reduce the contact resistance.

하부 전극(410)은 루테늄(Ru)을 포함하여 형성될 수 있으며, 또한, TaN, W, WN, Ru, RuO2, Ir, IrO2, Pt, Ru 및 RuO2의 이중층 Ir 및 IrO2의 이중층, SrRuO3 등과 같은 금속층 또는 금속산화물층을 포함하여 형성될 수 있다. 이러한 하부 전극(410)은, 디램 소자의 커패시터의 정전용량의 증대를 위해, 실린더(cylinder) 형상을 가지거나 필라(pillar) 형상을 가질 수 있다. 실린더 형상의 하부 전극(410)의 경우 몰드층(330)의 제거를 통해 외측벽을 노출시키는 경우와, 몰드층(330)을 유지하여 오목한 형상(concave)을 이용하는 경우로 적용될 수 있다. The lower electrode 410 may be formed including ruthenium (Ru), and further, a double layer of TaN, W, WN, Ru, RuO 2 , Ir, IrO 2 , Pt, Ru, and RuO 2 bilayer Ir and IrO 2 . It may be formed including a metal layer or a metal oxide layer, such as SrRuO3. The lower electrode 410 may have a cylinder shape or a pillar shape to increase the capacitance of the capacitor of the DRAM device. In the case of the cylindrical lower electrode 410, the outer wall may be exposed through the removal of the mold layer 330, and the case of using the concave may be maintained by maintaining the mold layer 330.

도 2를 참조하면, 하부 전극(410) 상에 유전층(430)을 증착한다. 유전층(430)은 상대적으로 높은 유전 상수 k를 가지는 티타늄산화물(TiO2)층(435)을 포함하여 형성될 수 있다. 티타늄산화물층(435)의 하부층으로 지르코늄산화물(ZrO2)층(431)을 더 형성하여 이중층으로 유전층(430)을 구성할 수 있다. 지르코늄산화물 층(431)은 원자층증착(ALD)으로 대략 40Å 내지 120Å 두께로 형성될 수 있다. 이때, 반도체 기판(100)의 온도를 지르코늄산화물의 결정화온도 이하인 대략 200℃ 내지 350℃ 정도로 유지하여, 과다한 결정화에 따른 유전율 감소를 억제한다. Referring to FIG. 2, a dielectric layer 430 is deposited on the lower electrode 410. The dielectric layer 430 may be formed to include a titanium oxide (TiO 2 ) layer 435 having a relatively high dielectric constant k. A dielectric layer 430 may be configured as a double layer by further forming a zirconium oxide (ZrO 2 ) layer 431 as a lower layer of the titanium oxide layer 435. The zirconium oxide layer 431 may be formed to have a thickness of about 40 kV to about 120 kW by atomic layer deposition (ALD). At this time, the temperature of the semiconductor substrate 100 is maintained at about 200 ° C. to 350 ° C., which is below the crystallization temperature of the zirconium oxide, to suppress the decrease in permittivity due to excessive crystallization.

증착 반응 챔버(chamber)는 0.1torr 내지 1torr 압력으로 유지되며, 반응 챔버에 지르코늄 소스(Zr source)로 테트라키스에틸메틸아미노지르코늄(Zr(NEtMe)4)과 같은 지르코늄 전구체를 공급할 수 있다. 운반 가스로 아르곤(Ar) 가스가 이용되며, 산화제로 오존(O3)이 이용된다. 퍼지 가스(purge gas)로 질소 가스(N2)가 이용된다. 지르코늄 소스는 운반 가스(Ar)의 유량을 20sccm 내지 250 sccm으로 유지하여 0.1초 내지 10초 정도 흐르게 한다. 이후에, 질소 가스의 유량을 50sccm 내지 400sccm으로 유지하여 3초 내지 10초 정도 퍼지한다. 산화제인 O3 가스의 유량을 200sccm 내지 500sccm으로 유지하여 3초 내지 10초 흘려주어 흡착된 지르코늄 소스를 산화시킨다. 이후에 N2 가스의 유량은 50~200sccm으로 유지하여 3초 내지 10초 퍼지한다. 이러한 과정을 반복하여 지르코늄산화물층(431)을 원자층증착(ALD)한다. The deposition reaction chamber is maintained at a pressure of 0.1torr to 1torr, and a zirconium precursor such as tetrakisethylmethylaminozirconium (Zr (NEtMe) 4 ) may be supplied to the reaction chamber as a zirconium source. Argon (Ar) gas is used as a carrier gas, and ozone (O 3 ) is used as an oxidizing agent. Nitrogen gas (N 2 ) is used as a purge gas. The zirconium source maintains a flow rate of the carrier gas (Ar) at 20 sccm to 250 sccm to flow for 0.1 to 10 seconds. Thereafter, the flow rate of nitrogen gas is maintained at 50 sccm to 400 sccm and purged for about 3 to 10 seconds. The flow rate of O 3 gas, which is an oxidant, is maintained at 200 sccm to 500 sccm, and then flowed for 3 to 10 seconds to oxidize the adsorbed zirconium source. Thereafter, the flow rate of the N 2 gas is maintained at 50 to 200 sccm and purged for 3 to 10 seconds. This process is repeated to zirconium oxide layer 431 atomic layer deposition (ALD).

지르코늄산화물층(431) 상에 티타늄산화물층(435)을 ALD 증착한다. 이때, 티타늄 소스로 Ti[N(CH3)2]4 또는 Ti[OCH(CH3)2]4를 사용하고, 운반 가스로 Ar을 사용하며, 산화제로는 O3을 이용하고, 퍼지 가스로 N2를 사용한다. 반도체 기판(100)의 온도를 200℃ 내지 500℃로 유지하고, 반응 챔버의 압력은 0.1torr 내지 1torr로 유지하여 TiO2를 40Å 내지 100Å 두께로 증착 한다. 티타늄 소스를 운반 가스(Ar)의 유량을 100sccm 내지 500sccm으로 유지하여 0.1초 내지 10초 정도 흘려준다. N2 가스의 유량은 100sccm 내지 500sccm으로 유지하여 3초 내지 10초 퍼지한다. 산화제인 O3 가스의 유량은 300sccm 내지 1000sccm으로 유지하여 3초 내지 10초 흘려주어 흡착된 티타늄 소스를 산화시킨다. N2 가스의 유량은 100sccm 내지 500sccm으로 유지하여 3초 내지 10초 퍼지한다. 이러한 과정을 반복하여 티타늄산화물층(435)을 원자층증착(ALD)한다. The titanium oxide layer 435 is ALD deposited on the zirconium oxide layer 431. At this time, Ti [N (CH 3 ) 2 ] 4 or Ti [OCH (CH 3 ) 2 ] 4 is used as the titanium source, Ar is used as the carrier gas, O 3 is used as the oxidant, and purge gas is used. N 2 is used. The temperature of the semiconductor substrate 100 is maintained at 200 ° C to 500 ° C, and the pressure of the reaction chamber is maintained at 0.1torr to 1torr to deposit TiO 2 to a thickness of 40 Pa to 100 Pa. The titanium source is maintained at a flow rate of the carrier gas Ar at 100 sccm to 500 sccm, and then flowed for about 0.1 to 10 seconds. The flow rate of the N 2 gas is maintained at 100 sccm to 500 sccm and purged for 3 to 10 seconds. The flow rate of the O 3 gas, which is an oxidant, is maintained at 300 sccm to 1000 sccm, and flows for 3 to 10 seconds to oxidize the adsorbed titanium source. The flow rate of the N 2 gas is maintained at 100 sccm to 500 sccm and purged for 3 to 10 seconds. By repeating this process, the titanium oxide layer 435 is atomic layer deposited (ALD).

이와 같은 티타늄산화물층(435) 상에 직접적으로 상부 전극인 티타늄질화물(TiN)층을 증착할 경우, 티타늄질화물층의 질화를 위해 제공되는 암모니아(NH3)와 TiO2가 환원 반응을 일으키게 된다. 이러한 환원 반응에 의해 티타늄산화물층(435)은 환원되어 유전율의 감소가 유발되므로, 커패시터의 전기적 특성의 열화가 유발될 수 있다. 본 발명의 실시예에서는 이러한 환원 반응을 억제하기 위해서, 티타늄산화물층(435) 상에 환원 반응을 억제하는 캡층(capping layer)을 도입한다. In the case of depositing a titanium nitride (TiN) layer as an upper electrode directly on the titanium oxide layer 435, ammonia (NH 3 ) and TiO 2 provided for nitriding the titanium nitride layer cause a reduction reaction. Because of the reduction reaction, the titanium oxide layer 435 is reduced to cause a decrease in dielectric constant, which may cause deterioration of electrical characteristics of the capacitor. In an embodiment of the present invention, a capping layer that suppresses a reduction reaction is introduced on the titanium oxide layer 435 in order to suppress such a reduction reaction.

도 3을 참조하면, 티타늄산화물층(435) 상에 티타늄산질화물(TiON)층을 형성하여 환원 반응을 억제하는 캡층(capping layer: 450)으로 이용한다. 캡층(450)으로 티타늄산질화물(TiON)층을 형성하는 과정은 티타늄산화물층(435)을 ALD 증착하는 과정에 인시튜로 수행될 수 있다. 즉, 티타늄산화물층(435)을 ALD 증착한 후, 증착된 티타늄산화물층(435) 표면을 질화시켜 티타늄산질화물(TiON)층을 표면층으로 형성한다. 티타늄산화물이 ALD 증착된 공정 챔버 내에 질소 가스(N2) 또는 질소 가스와 산소 가스(O2)의 혼합 가스와 같은 질화 가스를 제공한 후 50W 내지 300W의 고주파 파워(power)로 플라즈마 여기시킨다. 이러한 질화 플라즈마에 의해 티타늄산화물층(435)의 표면이 질화되어 티타늄산질화물(TiON)층의 캡층(450)이 형성된다. 이러한 플라즈마 표면 질화 처리는 대략 200℃ 내지 500℃ 온도에서 수행되며, 표면 질화 처리에 의해 형성되는 티타늄산질화물(TiON)층은 1Å 내지 10Å의 두께를 가지게 형성된다. Referring to FIG. 3, a titanium oxynitride (TiON) layer is formed on the titanium oxide layer 435 and used as a capping layer 450 to suppress a reduction reaction. The process of forming the titanium oxynitride (TiON) layer with the cap layer 450 may be performed in situ in the process of ALD deposition of the titanium oxide layer 435. That is, after ALD deposition of the titanium oxide layer 435, the surface of the deposited titanium oxide layer 435 is nitrided to form a titanium oxynitride (TiON) layer. The titanium oxide is provided with a nitride gas such as nitrogen gas (N 2 ) or a mixture of nitrogen gas and oxygen gas (O 2 ) in an ALD deposited process chamber, and then plasma excited with high frequency power of 50W to 300W. The surface of the titanium oxide layer 435 is nitrided by such a nitride plasma to form a cap layer 450 of a titanium oxynitride (TiON) layer. The plasma surface nitriding treatment is performed at a temperature of about 200 ° C. to 500 ° C., and the titanium oxynitride (TiON) layer formed by the surface nitriding treatment is formed to have a thickness of about 1 Pa to 10 Pa.

도 4를 참조하면, 캡층(450) 상에 티타늄질화물(TiN)의 상부 전극(470)을 증착한다. 티타늄질화물(TiN)의 증착은 사염화티타늄(TiCl4)과 같은 티타늄 소스와 암모니아(NH3)와 같은 질화 소스를 이용한 화학기상증착(CVD)으로 수행될 수 있다. 이때, 질화 소스로 제공되는 암모니아는 하부의 캡층(450)의 티타늄산질화물(TiON)을 티타늄질화물(TiN)로 환원시키는 환원 반응을 유도할 수 있다. 캡층(450)의 티타늄산질화물(TiON)이 TiN으로 환원되지만, 상부 전극(470)이 TiN으로 이루어지므로 환원된 캡층(450)의 TiN은 상부 전극(470)의 일부로 작용할 수 있다. 한편, 캡층(450)에 의해 하부의 티타늄산화물층(435)으로의 암모니아의 침투가 억제되므로, 티타늄산화물층(435)에의 환원 반응은 억제되거나 방지될 수 있다. 따라서, 티타늄질화물(TiN)의 상부 전극(470)의 도입에 의해 티타늄산화물층(435)이 환원 반응에 의해 열화되는 것을 억제할 수 있다. 이에 따라, 유전층(430)의 환원 반응에 의한 전기적 특성의 열화를 방지하여, 보다 높은 정전용량을 가지는 커패시터를 구현할 수 있다. Referring to FIG. 4, an upper electrode 470 of titanium nitride (TiN) is deposited on the cap layer 450. The deposition of titanium nitride (TiN) may be performed by chemical vapor deposition (CVD) using a titanium source such as titanium tetrachloride (TiCl 4 ) and a nitride source such as ammonia (NH 3 ). At this time, the ammonia provided as the nitride source may induce a reduction reaction of reducing titanium oxynitride (TiON) of the lower cap layer 450 to titanium nitride (TiN). The titanium oxynitride (TiON) of the cap layer 450 is reduced to TiN, but since the upper electrode 470 is made of TiN, the reduced TiN of the cap layer 450 may serve as a part of the upper electrode 470. On the other hand, since the infiltration of ammonia into the lower titanium oxide layer 435 by the cap layer 450 is suppressed, the reduction reaction to the titanium oxide layer 435 can be suppressed or prevented. Therefore, the titanium oxide layer 435 can be suppressed from being degraded by the reduction reaction by the introduction of the upper electrode 470 of titanium nitride (TiN). Accordingly, deterioration of electrical characteristics due to the reduction reaction of the dielectric layer 430 may be prevented, and a capacitor having a higher capacitance may be implemented.

도 1 내지 도 4는 본 발명의 실시예에 따른 반도체 소자의 커패시터 형성 방법을 보여주는 단면도들이다. 1 to 4 are cross-sectional views illustrating a method of forming a capacitor of a semiconductor device according to an embodiment of the present invention.

Claims (5)

반도체 기판 상에 금속 하부 전극을 형성하는 단계;Forming a metal lower electrode on the semiconductor substrate; 상기 하부 전극 상에 티타늄산화물(TiO2)층을 포함하는 유전층을 형성하는 단계;Forming a dielectric layer including a titanium oxide (TiO 2 ) layer on the lower electrode; 상기 유전층을 덮어 상기 티타늄산화물(TiO2)층을 환원 반응으로부터 보호하는 캡층(capping layer)을 티타늄산질화물(TiON)을 포함하여 형성하는 단계; 및Forming a capping layer including titanium oxynitride (TiON) covering the dielectric layer to protect the titanium oxide (TiO 2 ) layer from a reduction reaction; And 상기 캡층 상에 티타늄질화물(TiN)을 증착하여 상부 전극을 형성하는 단계를 포함하는 반도체 소자의 커패시터 형성 방법. And depositing titanium nitride (TiN) on the cap layer to form an upper electrode. 제1항에 있어서, The method of claim 1, 상기 금속 하부 전극을 형성하는 단계는Forming the metal lower electrode 상기 반도체 기판 상에 절연층을 형성하는 단계;Forming an insulating layer on the semiconductor substrate; 상기 절연층을 관통하는 하부 전극용 콘택을 도전성 폴리실리콘(polysilicon)을 포함하여 형성하는 단계;Forming a contact for the lower electrode penetrating the insulating layer, including conductive polysilicon; 상기 절연층 상에 상기 하부 전극용 콘택에 정렬되는 오프닝홀(opening hole)을 가지는 몰드(mold)층을 형성하는 단계;Forming a mold layer on the insulating layer, the mold layer having an opening hole aligned with the contact for the lower electrode; 상기 오프닝홀의 프로파일(profile)을 따르는 금속층을 형성하는 단계; 및Forming a metal layer along a profile of the opening hole; And 상기 금속층을 화학기계적연마(CMP)로 평탄화하여 상기 하부 전극으로 분리 하는 단계를 포함하는 반도체 소자의 커패시터 형성 방법. And planarizing the metal layer by chemical mechanical polishing (CMP) to separate the metal layer into the lower electrode. 제1항에 있어서, The method of claim 1, 상기 유전층을 형성하는 단계는Forming the dielectric layer 상기 티타늄산화물(TiO2)층의 하부층으로 지르코늄산화물(ZrO2)층을 원자층증착(ALD)하는 단계를 더 포함하는 반도체 소자의 커패시터 형성 방법. And atomic layer deposition (ALD) the zirconium oxide (ZrO 2 ) layer as a lower layer of the titanium oxide (TiO 2 ) layer. 제1항에 있어서, The method of claim 1, 상기 티타늄산화물(TiO2)층은 The titanium oxide (TiO 2 ) layer is Ti[N(CH3)2]4 또는 Ti[OCH(CH3)2]4를 티타늄 소스로 이용하고 오존(O3)을 산화제로 이용하여 원자층증착(ALD)되는 반도체 소자의 커패시터 형성 방법. A method for forming a capacitor of a semiconductor device using atomic layer deposition (ALD) using Ti [N (CH 3 ) 2 ] 4 or Ti [OCH (CH 3 ) 2 ] 4 as a titanium source and ozone (O 3 ) as an oxidant . 제4항에 있어서, The method of claim 4, wherein 상기 캡층을 형성하는 단계는Forming the cap layer is 질소 가스 또는 질소 가스 및 산소 가스의 혼합 가스의 플라즈마(plasma)를 이용하여 상기 티타늄산화물(TiO2)층의 표면을 질화시켜 상기 티타늄산질화물(TiON)층을 형성하는 단계를 포함하는 반도체 소자의 커패시터 형성 방법. Nitriding the surface of the titanium oxide (TiO 2 ) layer using a plasma of nitrogen gas or a mixed gas of nitrogen gas and oxygen gas to form the titanium oxynitride (TiON) layer. How to form a capacitor.
KR1020080136775A 2008-12-30 2008-12-30 Method for fabricating capacitor of semiconductor device KR20100078496A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9520460B2 (en) 2013-09-05 2016-12-13 Samsung Electronics Co., Ltd. MIM capacitors with diffusion-blocking electrode structures and semiconductor devices including the same
US9997591B2 (en) 2015-09-09 2018-06-12 Samsung Electronics Co., Ltd. Capacitor and a semiconductor device including the same
KR20210035693A (en) * 2019-09-23 2021-04-01 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Method to reduce breakdown failure in a mim capacitor
US11430729B2 (en) 2020-09-16 2022-08-30 Taiwan Semiconductor Manufacturing Company, Ltd. MIM capacitor with a symmetrical capacitor insulator structure

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9520460B2 (en) 2013-09-05 2016-12-13 Samsung Electronics Co., Ltd. MIM capacitors with diffusion-blocking electrode structures and semiconductor devices including the same
US9997591B2 (en) 2015-09-09 2018-06-12 Samsung Electronics Co., Ltd. Capacitor and a semiconductor device including the same
KR20210035693A (en) * 2019-09-23 2021-04-01 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Method to reduce breakdown failure in a mim capacitor
US11152455B2 (en) 2019-09-23 2021-10-19 Taiwan Semiconductor Manufacturing Company, Ltd. Method to reduce breakdown failure in a MIM capacitor
US11594593B2 (en) 2019-09-23 2023-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method to reduce breakdown failure in a MIM capacitor
US11430729B2 (en) 2020-09-16 2022-08-30 Taiwan Semiconductor Manufacturing Company, Ltd. MIM capacitor with a symmetrical capacitor insulator structure

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