KR20100034332A - Method for manufacturing of crystalline substrate, crystalline substrate manufactured thereby, light emitting device including crystalline substrate and manufacturing method thereof - Google Patents

Method for manufacturing of crystalline substrate, crystalline substrate manufactured thereby, light emitting device including crystalline substrate and manufacturing method thereof Download PDF

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KR20100034332A
KR20100034332A KR1020080093400A KR20080093400A KR20100034332A KR 20100034332 A KR20100034332 A KR 20100034332A KR 1020080093400 A KR1020080093400 A KR 1020080093400A KR 20080093400 A KR20080093400 A KR 20080093400A KR 20100034332 A KR20100034332 A KR 20100034332A
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layer
dislocation
single crystal
forming
substrate
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KR101146819B1 (en
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박태영
박성주
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광주과학기술원
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Priority to PCT/KR2009/005384 priority patent/WO2010036002A2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02387—Group 13/15 materials
    • H01L21/02389—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02417—Chalcogenide semiconducting materials not being oxides, e.g. ternary compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02647—Lateral overgrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02647—Lateral overgrowth
    • H01L21/0265—Pendeoepitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds

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Abstract

PURPOSE: A manufacturing method of crystalline substrate, a crystalline substrate manufactured using the same, a light emitting device including a crystalline substrate, and a manufacturing method thereof are provided to obtain a uniform surface of a gallium nitride single crystal substrate using an electric potential prevention layer. CONSTITUTION: A lower epi layer(12) is formed on a base substrate(10). A part of an electric potential region within the lower epi layer is selectively removed. Accordingly, an electric potential prevention layer is formed within the electric potential region. A top epi layer(18) is formed on the lower epi layer. The electric potential region is selectively removed using the dry etch or the wet etch process.

Description

Method for manufacturing a single crystal substrate, a single crystal substrate manufactured by the same, a light emitting device including the single crystal substrate, and a method for manufacturing the same

The present invention relates to a light emitting device and a single crystal substrate provided therein, and more particularly, to a method of manufacturing a single crystal substrate, a single crystal substrate produced by the same, a light emitting device including the single crystal substrate and a method of manufacturing the same.

The light emitting device is a device using a phenomenon of emitting light when a forward current flows through a PN junction diode of a compound semiconductor, and is mainly used as a light source of a display device. Such a light emitting device does not require a filament such as a light bulb, exhibits excellent characteristics such as being resistant to vibration, having a long lifetime, and having a fast reaction speed.

In order to manufacture a light emitting device having high efficiency, a high quality single crystal substrate having uniform and few defects is required. However, in the conventional substrate, defects such as dislocations exist in the substrate, and the dislocations continuously propagate as crystal growth is performed. In addition, since new potentials are continuously generated and generated, a problem arises in that the surface of the substrate is rough and the quality is poor.

SUMMARY OF THE INVENTION An object of the present invention for solving the above problems is to provide a method of manufacturing a single crystal substrate with minimized defects, a single crystal substrate manufactured thereby, a light emitting device including the single crystal substrate, and a method of manufacturing the same.

SUMMARY OF THE INVENTION The present invention for achieving the above-described first object includes the steps of growing a lower epitaxial layer on a base substrate, selectively removing at least a portion of the dislocation regions in the lower epilayer, dislocation preventing elements in the removed dislocation regions. And forming an upper epitaxial layer on the lower epitaxial layer on which the dislocation preventing element is formed.

Selectively removing at least a portion of the dislocation region may be performed using dry etching or wet etching. The dislocation prevention element may be formed by forming a dislocation prevention layer on the lower epitaxial layer and then planarizing until the lower epitaxial layer is exposed. The dislocation prevention element can be planarized using chemical mechanical polishing or etch back method.

The dislocation prevention element may be formed by forming a photoresist pattern on the lower epi layer outside the removed dislocation region, forming a dislocation prevention film, and then removing the photoresist pattern. The dislocation prevention element may be a metal layer or an inorganic layer. The metal layer may be an Ag layer, an Au layer, or a Pt layer, and the inorganic layer may be a SiN layer, an SiO 2 layer, an HfO 2 layer, or a TiO 2 layer.

The upper epitaxial layer may be formed using MOCVD, MBE, HVPE, or SVPE. The upper epi layer may be a SiC layer, a ZnO layer, a Si layer, a GaAs layer, an NCO layer, a BN layer, an AlN layer, or a GaN layer.

The present invention for achieving the above-described second object is a base substrate, a lower epi layer disposed on the base substrate, having a plurality of grooves on the upper surface, a potential preventing element and the potential preventing element and the potential preventing element located in the groove A single crystal substrate having an upper epi layer disposed on a lower epi layer is provided.

The present invention for achieving the above-mentioned third object is to grow a lower buffer layer on a base substrate, to selectively remove at least a portion of the dislocation regions in the lower buffer layer, to form a dislocation prevention element in the removed dislocation regions A light emitting device comprising the steps of: forming an upper buffer layer on the lower buffer layer on which the potential protection element is formed; forming an active layer on the upper buffer layer; and forming a second type single crystal semiconductor layer on the active layer. It provides a manufacturing method.

The present invention for achieving the above-described fourth object is located on the base substrate, the lower buffer layer having a plurality of grooves in the upper surface, the potential preventing element located in the groove, on the potential preventing element and the lower buffer layer Provided is a light emitting device including an upper buffer layer positioned, an active layer formed on the upper buffer layer, and a second type single crystal semiconductor layer formed on the active layer.

The dislocation region existing in the substrate was etched and removed to form a dislocation preventing element in the groove formed thereby. As a result, it is possible to prevent the potential present in the substrate from being blocked by the dislocation preventing element and propagating to the upper single crystal epilayer. In addition, since the upper single crystal epitaxial layer grows laterally by the grooves formed by removing the dislocation regions, dislocations can be prevented from growing vertically. Therefore, defects in the substrate can be minimized, and since the upper epitaxial layer is grown at a portion with low dislocations, a gallium nitride single crystal substrate having a smooth and uniform surface can be obtained. Accordingly, the efficiency of the light emitting device having such a single crystal substrate can be improved.

As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description.

However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention. Hereinafter, the same reference numerals are used for the same components in the drawings, and duplicate descriptions of the same components are omitted.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1A to 1G are schematic views showing a method of manufacturing a gallium nitride single crystal substrate according to an embodiment of the present invention.

Referring to FIG. 1A, the lower epitaxial layer 12 may be grown on the base substrate 10. The base substrate 10 may be a sapphire substrate or a silicon substrate. The lower epitaxial layer 12 may be a SiC layer, a ZnO layer, a Si layer, a GaAs layer, an NCO layer, a BN layer, an AlN layer, or a GaN layer. Due to the lattice constant difference between the lower epitaxial layer 12 and the base substrate 10, dislocations having different crystallinities may be formed in the lower epitaxial layer 12. Such dislocations can impair the quality of the single crystal substrate.

Referring to FIG. 1B, the selectivity ratio between the region where the potential is formed and the region where the potential is not formed differs due to the difference in crystallinity. Accordingly, at least a portion of the dislocation region in the lower epitaxial layer 12 is selectively removed using an etchant that selectively removes the region where the dislocation is formed. Selectively removing the dislocation region in the lower epitaxial layer 12 may be performed using dry etching or wet etching. When using dry etching, the etchant may be an etching gas such as CF4, CH4, C2 or F6, and when using wet etching, the etchant may be an etchant such as HCl, KOH, NaOH, HF, or H 2 SO 4 . have. As described above, a plurality of grooves 13 may be formed on the upper surface of the lower epitaxial layer 12 by selectively removing the dislocation region on the lower epitaxial layer 12.

Referring to FIG. 1C, the photoresist layer 14 may be formed on a separate auxiliary substrate 20. The auxiliary substrate 20 may be Al 2 O 3 , SiC, ZnO, Si, GaAs, NCO, BN, AlN or GaN substrate. The release layer 21 may be positioned between the auxiliary substrate 20 and the photoresist layer 14. The release layer 21 may facilitate separation of the photoresist layer 14 and the auxiliary substrate 20. The release layer 21 may be a material that can be cured by one selected from ultraviolet curing, room temperature curing, low temperature curing, and catalytic curing. The release layer 21 may be a silicon-based polymer material layer having a glass transition temperature (Tg) of 25 ° C. or less.

After contacting the lower epitaxial layer 12 having the plurality of grooves 13 and the photoresist layer 14 formed on the auxiliary substrate 20, heat and pressure may be applied. The heat may be applied at a temperature of 40 ℃ to 300 ℃, the pressure may be applied from 10pis to 1200pis. When the heat is applied as described above, the release layer 21 may be softened by a temperature higher than the glass conductivity. Therefore, the photoresist layer 14 can be easily peeled off from the auxiliary substrate 20. In addition, by applying the pressure, the photoresist layer 14 peeled from the auxiliary substrate 20 may be bonded to the lower epitaxial layer 12 without being separated. In this case, the photoresist layer 14 may be selectively attached to a portion in contact with the lower epitaxial layer 12.

Then, the heat and pressure are removed, and the auxiliary substrate 20 is separated from the base substrate 10. In this case, the photoresist layer 14 may be selectively attached to a portion in contact with the lower epitaxial layer 12.

 That is, since the unetched portion of the lower epitaxial layer 12 contacts the photoresist layer 14, the photoresist pattern 15 may be formed, and the plurality of grooves 13 in which the dislocation region is removed. ) Is not in contact with the photoresist layer 14, the photoresist pattern 15 may not be formed.

Referring to FIG. 1D, a dislocation prevention layer 16 covering the photoresist pattern 15 and the groove 13 of the lower epitaxial layer 12 may be formed. The dislocation prevention layer 16 may not contact the unetched portion of the lower epitaxial layer 12 by the photoresist pattern 13, and the plurality of grooves 13 in which the dislocation region is selectively removed. Can be contacted. The potential barrier 16 may be an inorganic layer or a metal layer. The inorganic film may be SiN, SiO 2 , HfO 2 or TiO 2 . The metal film may be Ag, Au, or Pt.

Referring to FIG. 1E, the photoresist pattern 15 formed on the lower epitaxial layer 12 is removed. As a result, the dislocation prevention layer 16 formed on the upper and side surfaces of the photoresist pattern 15 may be removed, and the dislocation prevention element 17 may remain only in the groove 13.

Referring to FIG. 1F, the upper epitaxial layer 18 may be formed on the lower epitaxial layer 12 on which the dislocation preventing element 17 is formed. The upper epitaxial layer 18 may be a single crystal growth layer. The single crystal growth layer may be a SiC layer, a ZnO layer, a Si layer, a GaAs layer, an NCO layer, a BN layer, an AlN layer, or a GaN layer. The upper epitaxial layer 18 may be formed using a recrystallization method. The recrystallization method may be MOCVD (Metal Organic Chemical Vapor Deposition), MBE (molecular beam deposition), HVPE (hydride or halide vapor phase epitaxy) or SVPE (sublimation vapor phase epitaxy).

For example, in the case where the upper epitaxial layer 18 is formed of a GaN layer using MOCVD, the base substrate 10 equipped with the dislocation preventing element 17 is accommodated in a reaction vessel, and a trimethl gallium (TMGa) and NH are used. 3 can be injected. Thereafter, heat may be applied to the lower epitaxial layer 12 to thermally decompose the TMGa. Among the pyrolyzed elements, Ga may be combined with N of NH 3 to form an upper epitaxial layer 18 made of GaN. The heat can be generated using RF heating, resistance heating or infrared lamp heating. The inside of the reaction vessel may maintain a vacuum degree of 200torr, the surface temperature of the lower epitaxial layer 12 may maintain a temperature of about 1200 ℃.

When forming the upper epi layer 18, the dislocation prevention element 17 may block the growth and progress of dislocations. In addition, since the upper epitaxial layer 18 can grow laterally without vertical growth by the dislocation preventing element 17, vertical growth of dislocations can be prevented. Therefore, defects inside the substrate can be minimized, and a single crystal substrate having a uniform surface can be obtained.

2A is a schematic diagram illustrating a propagation path of a potential in an existing substrate.

Referring to FIG. 2A, a plurality of dislocations exist in the lower epitaxial layer 12. The dislocations are not removed even when the upper epitaxial layer 18 is formed on the lower epitaxial layer 12, and as the upper epitaxial layer 18 grows, the dislocations are also grown.

2B is a schematic diagram illustrating a propagation path of dislocations in a single crystal substrate according to the present invention.

Referring to FIG. 2B, a plurality of potentials may exist in the lower epitaxial layer 12. However, when the potential preventing element 17 is formed in the plurality of grooves 13 from which the potential region of the lower epitaxial layer 12 is removed, the upper epitaxial layer 18 may be formed on the lower epitaxial layer 12. It is blocked by the dislocation preventing element 17 so that no electric potential propagates or is newly generated.

Meanwhile, a void 19 may exist in the groove 13. The void 19 may be formed as an empty space between the portion recessed toward the base substrate 10 and the upper epitaxial layer 18. The voids 19 can play a very positive role in absorbing internal defects and hindering their growth and progression.

3A to 3E are schematic diagrams showing a method of growing a gallium nitride single crystal according to an embodiment of the present invention.

Referring to FIG. 3A, the lower epitaxial layer 12 may be grown on the base substrate 10. The base substrate 10 may be a sapphire substrate or a silicon substrate. The lower epitaxial layer 12 may be a SiC layer, a ZnO layer, a Si layer, a GaAs layer, an NCO layer, a BN layer, an AlN layer, or a GaN layer. Due to the lattice constant difference between the lower epitaxial layer 12 and the base substrate 10, dislocations having different crystallinities may be formed in the lower epitaxial layer 12. Such dislocations can impair the quality of the single crystal substrate.

Referring to FIG. 3B, the region where the potential is formed and the region where the potential is not formed differ in etching selectivity due to differences in crystallinity. Accordingly, at least a portion of the dislocation region in the lower epitaxial layer 12 is selectively removed using an etchant that selectively removes the region where the dislocation is formed. Selectively removing the dislocation region in the lower epitaxial layer 12 may be performed using dry etching or wet etching. When using dry etching, the etchant may be an etching gas such as CF4, CH4, C2 or F6, and when using wet etching, the etchant may be an etchant such as HCl, KOH, NaOH, HF, or H 2 SO 4 . have. As described above, a plurality of grooves 13 may be formed on the upper surface of the lower epitaxial layer 12 by selectively removing the dislocation region on the lower epitaxial layer 12.

Referring to FIG. 3C, a dislocation prevention layer 16 covering the lower epitaxial layer 12 may be formed. The potential barrier 16 may be an inorganic layer or a metal layer. The inorganic film may be SiN, SiO 2 , HfO 2 or TiO 2 . The metal film may be Ag, Au, or Pt.

Referring to FIG. 3D, the dislocation prevention layer 16 formed on the lower epitaxial layer 12 is planarized until the lower epitaxial layer 12 is exposed to form the dislocation preventing element 17. The dislocation preventing element 17 may be peaceful using chemical mechanical polishing (CMP) or planarized using an etch back method. The etch back may be performed by using reactive ion etching (RIE) or inductively coupled plasma (ICP).

Referring to FIG. 3E, the upper epitaxial layer 18 may be formed on the lower epitaxial layer 12 on which the dislocation preventing element 17 is formed. The upper epitaxial layer 18 may be a single crystal growth layer. The single crystal growth layer may be a SiC layer, a ZnO layer, a Si layer, a GaAs layer, an NCO layer, a BN layer, an AlN layer, or a GaN layer. The upper epitaxial layer 18 may be formed using a recrystallization method. The recrystallization method may be MOCVD (Metal Organic Chemical Vapor Deposition), MBE (molecular beam deposition), HVPE (hydride or halide vapor phase epitaxy) or SVPE (sublimation vapor phase epitaxy).

When forming the upper epi layer 18, the dislocation prevention element 17 may block the growth and progress of dislocations.

4A to 4H are schematic views illustrating a method of manufacturing a light emitting device including a single crystal substrate, and are limited to the unit cell of the light emitting device.

Referring to FIG. 4A, a lower buffer layer 32a may be formed on the base substrate 30. The base substrate 30 may be a sapphire substrate or a silicon substrate. The lower buffer layer 32a may be a SiC layer, a ZnO layer, a Si layer, a GaAs layer, an NCO layer, a BN layer, an AlN layer, or a GaN layer. Due to the lattice constant difference between the lower buffer layer 32a and the base substrate 30, dislocations having different crystallinities may be formed in the lower buffer layer 32a. Such dislocations can impair the quality of the single crystal substrate.

Referring to FIG. 4B, the regions where the potential is formed and the region where the potential is not formed differ in etching selectivity from each other due to differences in crystallinity. Therefore, at least a portion of the dislocation region in the lower buffer layer 32a is selectively removed using an etchant that selectively removes the region where the dislocation is formed. Selectively removing the dislocation region in the lower buffer layer 32a may be performed using dry etching or wet etching. When using dry etching, the etchant may be an etching gas such as CF4, CH4, C2 or F6, and when using wet etching, the etchant may be an etchant such as HCl, KOH, NaOH, HF, or H 2 SO 4 . have. As described above, a plurality of grooves 33 may be formed on the upper surface of the lower buffer layer 32a by selectively removing the potential region on the lower buffer layer 32a.

Referring to FIG. 4C, a dislocation prevention element 34 may be formed in the removed dislocation region. The dislocation preventing element 34 may be formed using the method described with reference to FIGS. 1C-1E or may be formed using the method described with reference to FIGS. 3C-3D.

The dislocation prevention element 34 may be an inorganic layer or a metal layer. When the dislocation preventing element 34 is formed of an inorganic material layer, it is possible to improve stability at high temperature, and when forming the metal layer, reflectivity can be improved and used as a reflective layer of a light emitting device, thereby contributing to improvement of light extraction efficiency. have. The inorganic layer may be SiN, SiO 2 , HfO 2 or TiO 2 . The metal layer may be Ag, Au, or Pt.

Referring to FIG. 4D, the upper buffer layer 32b may be grown on the lower buffer layer 32a on which the dislocation preventing element 34 is formed. The upper buffer layer 32b may be a SiC layer, a ZnO layer, a Si layer, a GaAs layer, an NCO layer, a BN layer, an AlN layer, or a GaN layer.

Referring to FIG. 4E, a first type single crystal semiconductor layer 35 may be formed on the buffer layer 32. The first type single crystal semiconductor layer 35 may be a semiconductor layer into which n-type impurities are implanted. The n-type nitride-based semiconductor layer is a SiC layer, ZnO layer, Si layer, GaAs layer, NCO layer, BN layer, AlN layer, GaN layer, Mg x Zn y Cd Z O layer (0≤x, y, z≤1 ) Or an Al x Ga (1-x) N (0≤x≤1) layer.

Referring to FIG. 4F, an active layer 36 may be formed on the first type single crystal semiconductor layer 35. The active layer 36 may have a quantum dot structure or a multi quantum well structure. When the active layer 36 has a multi-quantum well structure, the active layer 36 may have a multiple structure of an InGaN layer as a well layer and a GaN layer as a barrier layer.

Referring to FIG. 4G, the second type single crystal semiconductor layer 37 may be formed on the active layer 36. The second type single crystal semiconductor layer 37 may be a semiconductor layer into which p-type impurities are implanted. The p-type nitride semiconductor layer is a SiC layer, ZnO layer, Si layer, GaAs layer, NCO layer, BN layer, AlN layer, GaN layer, Mg x Zn y Cd Z O layer (0≤x, y, z≤1 ) Or an Al x Ga (1-x) N (0≤x≤1) layer. The upper buffer layer 35, the active layer 36, and the second type single crystal semiconductor layer 37 may be formed using a metal organic chemical vapor deposition (MOCVD) technique or a molecular beam epitaxy (MBE) technique.

Referring to FIG. 4H, a portion of the second type single crystal semiconductor layer 37 and the active layer 36 may be etched to expose a portion of the first type single crystal semiconductor layer 35. In this case, a portion of the first type single crystal semiconductor layer 35 may also be etched. Accordingly, the light emitting device includes the buffer layer 32, the first type single crystal semiconductor layer 35, the active layer 36, and the second type single crystal semiconductor layer 37, which are sequentially stacked on the active layer 36. The first type single crystal semiconductor layer 35 may be exposed on one side of the second type single crystal semiconductor layer 37.

Referring to FIG. 4I, a first electrode 38 electrically connected to the first type single crystal semiconductor layer 35 and a second electrode 39 electrically connected to the second type single crystal semiconductor layer 37 are formed. can do. The first electrode 38 may be a cathode, and the second electrode 39 may be an anode. The first electrode 38 and the second electrode 39 may contain Al and / or Ag.

Table 1 shows the crystallinity and surface roughness of the single crystal substrate according to the present invention. The crystallinity of the gallium nitride substrate was analyzed by X-ray diffraction (XRD), and the initial θ value between the specimen and the detector was 34.8 °. The surface roughness was also analyzed by atomic force microscopy (AFM).

Kinds θ value (°) Roughness (nm) Existing Board 0.21 0.75 Invention Substrate 0.14 0.50

Crystallinity is a numerical value that determines the quality of a single crystal and can be predicted through the θ value between the specimen and the detector. In other words, if the value of θ is large, crystallinity is low because the X-rays have a large fall angle, and if the value of θ is small, the crystallinity is high because the X-rays have a small fall angle. Therefore, the lower the value of θ, the higher the quality of the single crystal.

As can be seen from the results of Table 1, in the case of θ value, the existing substrate showed a high value as 0.21. On the other hand, in the case of the substrate of the present invention, 0.14 showed a lower value than the conventional substrate. This may indicate that the single crystal quality of the substrate of the present invention is improved compared to the existing substrate.

In addition, in the case of roughness, the existing substrate shows a slightly higher value as 0.75, while the substrate according to the present invention has a low surface roughness as 0.5. Since the roughness can be determined that the lower the value, the better the lateral growth, the substrate according to the present invention can correspond to the result that the growth of the dislocation in the vertical direction is excellent due to the excellent lateral growth.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the present invention as defined by the following claims It can be understood that

1A to 1G are schematic views showing a method of manufacturing a gallium nitride single crystal substrate according to an embodiment of the present invention.

2A is a schematic diagram illustrating a propagation path of a potential in an existing substrate.

2B is a schematic diagram illustrating a propagation path of dislocations in a single crystal substrate according to the present invention.

3A to 3E are schematic diagrams showing a method of growing a gallium nitride single crystal according to an embodiment of the present invention.

4A to 4H are schematic views illustrating a method of manufacturing a light emitting device including a single crystal substrate.

<Description of the symbols for the main parts of the drawings>

10: base substrate 12: lower epitaxial layer

13: groove 17: potential preventing element

18: upper epitaxial layer 30: base substrate

32: buffer layer 34: dislocation prevention element

35: type 1 single crystal semiconductor layer 36: active layer

37: type 2 single crystal semiconductor layer

Claims (25)

Growing a lower epitaxial layer on the base substrate; Selectively removing at least a portion of the dislocation region in the lower epi layer; Forming a dislocation prevention element in the removed dislocation region; And Forming an upper epitaxial layer on the lower epitaxial layer on which the dislocation prevention element is formed. The method of claim 1, Selectively removing at least a portion of the dislocation region, Method of producing a single crystal substrate, characterized in that performed using dry etching or wet etching. The method of claim 1, And the dislocation preventing element is formed by forming a dislocation prevention film on the lower epitaxial layer and then planarizing the lower epitaxial layer until the lower epitaxial layer is exposed. The method of claim 3, wherein And the dislocation prevention element is planarized using chemical mechanical polishing or etch back method. The method of claim 1, And the dislocation prevention element is formed by forming a photoresist pattern on the lower epitaxial layer other than the removed dislocation region, and forming a dislocation prevention film, and then removing the photoresist pattern.  The method according to any one of claims 1 to 5, And the dislocation preventing element is a metal layer or an inorganic layer. The method of claim 1, The upper epitaxial layer is formed by using a MOCVD method, MBE method, HVPE method or SVPE method. The method according to claim 1 or 7, The upper epi layer is a SiC layer, ZnO layer, Si layer, GaAs layer, NCO layer, BN layer, AlN layer or GaN layer manufacturing method of a single crystal substrate. Base substrate: A lower epi layer on the base substrate and having a plurality of grooves on an upper surface thereof; A dislocation prevention element located within the groove; And And a top epi layer positioned on the dislocation prevention element and the bottom epi layer. The method of claim 9, Wherein the dislocation prevention element is a metal layer or an inorganic layer. The method of claim 10, The metal layer is an Ag layer, Au layer or Pt layer. The method of claim 10, The inorganic layer is a SiN layer, SiO 2 layer, HfO 2 layer or TiO 2 layer single crystal substrate. The method of claim 9, The upper epi layer is a SiC layer, ZnO layer, Si layer, GaAs layer, NCO layer, BN layer, AlN layer or GaN layer manufacturing method of a single crystal substrate. Growing a lower buffer layer on the base substrate; Selectively removing at least a portion of the dislocation region in the lower buffer layer; Forming a dislocation prevention element in the removed dislocation region; Forming an upper buffer layer on the lower buffer layer in which the dislocation prevention element is formed; Forming a first type semiconductor layer on the upper buffer layer; Forming an active layer on the first type semiconductor layer; And Forming a second type semiconductor layer on the active layer. The method of claim 14, And the potential preventing element is formed by forming a potential preventing film on the lower buffer layer and then planarizing until the lower buffer layer is exposed. The method of claim 15, The dislocation preventing element is planarized by chemical mechanical polishing or etch back method. The method of claim 14, The dislocation preventing element is formed by performing a photoresist pattern on the lower buffer layer outside the removed dislocation region, forming a dislocation preventing film, and then removing the photoresist pattern.  The method according to any one of claims 14 to 17, The potential preventing element is a light emitting device manufacturing method of a metal layer or an inorganic material layer. The method of claim 14, The upper buffer layer is formed by using a MOCVD method, MBE method, HVPE method or SVPE method. The method of claim 14 or 19, The upper buffer layer is a SiC layer, ZnO layer, Si layer, GaAs layer, NCO layer, BN layer, AlN layer or GaN layer manufacturing method. A lower buffer layer disposed on the base substrate and having a plurality of grooves in an upper surface thereof; A dislocation prevention element located within the groove; An upper buffer layer on the dislocation prevention element and the lower buffer layer; An active layer formed on the upper buffer layer; And A light emitting device comprising a second type single crystal semiconductor layer formed on the active layer. The method of claim 21, The potential preventing element is a light emitting device is a metal layer or an inorganic layer. The method of claim 22, The metal layer is an Ag layer, Au layer or Pt layer light emitting device. The method of claim 22, The inorganic layer is a SiN layer, SiO 2 layer, HfO 2 layer or TiO 2 layer light emitting device. The method of claim 21, The upper buffer layer is a SiC layer, ZnO layer, Si layer, GaAs layer, NCO layer, BN layer, AlN layer or GaN layer.
KR1020080093400A 2008-09-23 2008-09-23 Method for Manufacturing of Crystalline Substrate, Crystalline Substrate Manufactured Thereby, Light Emitting Device Including Crystalline Substrate and Manufacturing Method Thereof KR101146819B1 (en)

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