KR20090068637A - Method for forming metal line of semiconductor device - Google Patents

Method for forming metal line of semiconductor device Download PDF

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Publication number
KR20090068637A
KR20090068637A KR1020070136333A KR20070136333A KR20090068637A KR 20090068637 A KR20090068637 A KR 20090068637A KR 1020070136333 A KR1020070136333 A KR 1020070136333A KR 20070136333 A KR20070136333 A KR 20070136333A KR 20090068637 A KR20090068637 A KR 20090068637A
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KR
South Korea
Prior art keywords
forming
photoresist pattern
metal wiring
metal
etching
Prior art date
Application number
KR1020070136333A
Other languages
Korean (ko)
Inventor
이종순
Original Assignee
주식회사 동부하이텍
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Publication date
Application filed by 주식회사 동부하이텍 filed Critical 주식회사 동부하이텍
Priority to KR1020070136333A priority Critical patent/KR20090068637A/en
Publication of KR20090068637A publication Critical patent/KR20090068637A/en

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/42—Stripping or agents therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings of a semiconductor device, and the present invention relates to a lower metal wiring, an upper metal wiring, and a contact plug connecting them using a plurality of deposition processes, a plurality of planarization processes, and a plurality of photolithography processes. Unlike the conventional method of manufacturing a semiconductor device comprising a, after depositing a metal layer on the interlayer insulating film, patterning the contact hole, and filling the contact hole to form a contact plug including a portion of the upper metal wiring, the metal layer By patterning according to the defined wiring area to form the remaining upper metal wiring, a portion of the upper metal wiring and a contact plug can be simultaneously formed to reduce the processing process, thereby reducing the processing process.

Description

METHOD FOR FORMING METAL LINE OF SEMICONDUCTOR DEVICE

The present invention relates to a method for forming metal wiring of a semiconductor device, and more particularly, to a method for forming metal wiring of a semiconductor device suitable for forming an upper metal wiring electrically connected to a contact plug on a semiconductor substrate on which a lower metal wiring is formed. .

As is well known, the manufacturing process of a semiconductor device includes processes such as a deposition process, an etching process and an ion implantation process.

In other words, the semiconductor device forms a pattern through a photo process, an etching process, and an ion implantation process after depositing a thin film of various layers such as a polycrystalline film, an oxide film, a nitride film, and a metal film on a wafer. ) Is a core technology of the semiconductor manufacturing process that uses a photomask to form a desired pattern of a semiconductor device on a wafer.

In particular, a metal material such as aluminum (Al) or tungsten (W) is used to form a metal layer in the manufacturing process of a semiconductor device, and is injected by a method such as evaporation, sputtering, or the like. A photoresist coating process, a developing process, and the like are performed to form a film. Thereafter, the metal layer is selectively removed through an etching process according to the photoresist pattern. Here, the metal wiring is composed of lines and spaces, and various patterns, such as isolated patterns and dense patterns, are distributed on the wafer.

1A to 1J are process flowcharts illustrating a process of forming a lower metal wiring and an upper metal wiring according to a conventional method, and a metal wiring forming method according to the conventional method will be described with reference to these drawings.

Referring to FIG. 1A, a metal material, for example, aluminum (Al), copper (Cu), or the like is deposited on the semiconductor substrate 100 and then etched according to a predetermined photoresist pattern to lower metal wiring 102. Pattern.

After the insulating material is deposited on the semiconductor substrate 100 on which the lower metal interconnection 102 is patterned, the upper portion is planarized to form the interlayer insulating film 104 as shown in FIG. 1B.

Next, as shown in FIG. 1C, after the first photoresist pattern 106 for forming contact holes is formed on the semiconductor substrate 100 on which the interlayer insulating film 104 is formed, the first photoresist pattern 106 is formed. After etching the interlayer insulating film 104 so that the lower metal wiring 102 is exposed, the first photoresist pattern 106 is removed through a predetermined ashing process to remove the contact hole as shown in FIG. 1D. Form 108.

Thereafter, as shown in FIG. 1E, the metal material 110, for example, the turnsten W, is embedded in the contact hole 108, and then the upper portion thereof is flattened to expose the interlayer insulating film 104. As shown in 1f, the contact plug 110a is formed.

In addition, as illustrated in FIG. 1G, for example, aluminum (Al), copper (Cu), or the like, the metal layer 112 is deposited on the semiconductor substrate 100 on which the contact plug 110a is formed. A second photoresist pattern 114 for wiring patterning is formed on top of the deposited layer 112 as shown in FIG. 1H.

Subsequently, the metal layer 112 is etched according to the second photoresist pattern 114 to pattern the upper metal wiring 112a as shown in FIG. 1I, and then the second photoresist pattern 114 on the upper portion is patterned. By removing the semiconductor device, the semiconductor device including the lower metal interconnection 102 and the upper metal interconnection 112a and a contact plug 110a electrically connecting them are manufactured as shown in FIG. 1J.

However, conventionally, in the process of forming the metal wiring of the semiconductor device, as described above, the lower metal wiring, the upper metal wiring, and the contact plugs connecting them using a plurality of deposition processes, a plurality of planarization processes, and a plurality of photolithography processes. Since the manufacturing of the semiconductor device including a further increase the risk of exposure to various defects (defect) to be generated during each process, which is a situation that serves to reduce the device yield.

Accordingly, the present invention can simplify the process by depositing a metal layer on top of the interlayer insulating film, and simultaneously forming a part of the contact plug and the upper metal wiring using the same, and forming the remaining upper metal wiring using the metal layer. An object of the present invention is to provide a method for forming metal wirings in a semiconductor device.

The present invention comprises the steps of: depositing a metal layer on the semiconductor substrate on which the interlayer insulating film is deposited on the patterned lower metal wiring; Forming a first photoresist pattern defining a contact region over the deposited metal layer; Forming a contact hole by etching the metal layer and the interlayer insulating layer to expose the lower metal wires according to the first photoresist pattern; Removing the first photoresist pattern, filling the contact hole with a metal material, and planarizing an upper portion of the contact hole to form a contact plug including a portion of the upper metal wire; Forming a second photoresist pattern defining a wiring region on the contact plug formed thereon, and etching the metal layer according to the second photoresist pattern to form a remaining upper metal wiring. Provided is a method for forming metal wiring.

The present invention is different from the conventional method of manufacturing a semiconductor device including a lower metal wiring, an upper metal wiring, and a contact plug connecting the same by using a plurality of deposition processes, a plurality of planarization processes, and a plurality of photolithography processes. A metal layer is formed on the interlayer insulating film, the contact hole is formed by patterning the metal layer and the interlayer insulating film, and the contact hole is filled and planarized to form a part of the upper metal wiring and the contact plug at the same time, and then the metal layer is patterned to pattern the remaining upper metal wiring. By forming the semiconductor component, the process process can be reduced to prevent the occurrence of device defects, thereby improving the yield of semiconductor devices.

According to an aspect of the present invention, after the interlayer insulating film and the metal layer are sequentially formed on the semiconductor substrate on which the lower metal wiring is patterned, the contact hole is formed by etching the metal layer and the interlayer insulating film according to the photoresist pattern for defining the contact region. After filling the contact hole and the planarized metal material to form a part of the contact plug and the upper metal wiring, the metal layer is etched according to the photoresist pattern defining the wiring region to form the remaining upper metal wiring. This technical means can solve the problems in the prior art.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2H are process flowcharts illustrating a process of forming a lower metal wiring and an upper metal wiring according to an embodiment of the present invention. Referring to these drawings, a metal wiring forming method according to an embodiment of the present invention will be described with reference to these drawings. Explain.

Referring to FIG. 2A, a metal material, for example, aluminum (Al), copper (Cu), or the like is deposited on the semiconductor substrate 200 by sputtering of physical vapor deposition (PVD). This is etched according to a predetermined photoresist pattern (not shown) to pattern the lower metal wiring 202. Thereafter, the photoresist pattern is removed using an ashing process using N 2 , O 2, or the like, a solvent, or the like.

Then, for example, by using a chemical vapor deposition (CVD: Chemical Vapor Deposition) on the semiconductor substrate 200 patterned on the lower metal wiring 202, TEOS (Tetra Ethyl Ortho Silicate), USG (Undoped Silcate Glass), After depositing an insulating material such as BPSG (Boron Phosphorus Silicate Glass) or PSG (Phosphorus Silicate Glass), the upper part is planarized by a chemical mechanical polishing (CMP) process, and the interlayer insulating film as shown in FIG. 2B. (IMD: Inter-Metal Dielectric layer, 204).

In addition, a metal material (eg, aluminum (Al), etc.) is deposited on the semiconductor substrate 200 on which the interlayer insulating film 204 is formed, for example, by sputtering of physical vapor deposition (PVD). After forming, the first photoresist is applied to the upper portion by spin coating or the like, and a photolithography process (for example, exposure or development) is performed to define the contact region as shown in FIG. 2C. The first photoresist pattern 208 is formed.

Next, after performing the first etching process on the metal layer 206 by a method such as reactive ion etching (RIE) according to the first photoresist pattern 208 defining the contact region, the first photoresist According to the pattern 208, a second etching process is performed on the interlayer insulating film 204 by a method such as reactive ion etching to form a contact hole 210 as shown in FIG. 2D, and then an ashing process, a solvent, or the like. To remove the first photoresist pattern 208. Here, in the primary etching process, reactive ion etching is performed using an end point detector (EPD) at the point where the interlayer insulating film 204 is exposed using a gas such as Cl or BCL 3 , and the 2c etching process is performed by using C Reactive ion etching can be performed using the gas such as 5 F 8 as the EPD at the time point at which the lower metal wiring 202 is exposed.

Subsequently, a metal material, for example, tungsten (W) or the like, is deposited using chemical vapor deposition (CVD) or the like so that the contact hole 210 formed to expose the lower metal wiring 202 of the semiconductor substrate 200 is embedded. Subsequently, a chemical mechanical polishing process (CMP) is performed on the upper portion thereof to planarize the exposed metal layer 206 to form a contact plug 212 including a portion of the upper metal wiring as shown in FIG. 2E.

Then, the second photoresist is applied to the upper portion of the semiconductor substrate 200 on which the contact plug 212 is formed by spin coating or the like, followed by a photolithography process such as exposure and development, and the method shown in FIG. 2F. As described above, the second photoresist pattern 214 defining the wiring region is formed.

Next, the metal layer 206 is etched by a method such as reactive ion etching (RIE) according to the second photoresist pattern 214 defining the wiring region, and the remaining upper metal wiring 206a is etched as shown in FIG. 2G. After formation, the second photoresist pattern 214 is removed using an ashing process and a solvent to form metal wiring of the semiconductor element as shown in FIG. 2H.

Therefore, after the interlayer insulating film and the metal layer are sequentially formed on the semiconductor substrate on which the lower metal wiring is patterned, the contact hole is formed by etching the metal layer and the interlayer insulating film according to the photoresist pattern for defining the contact region, and forming the contact hole. After embedding the metal material in the planarization and planarization to form a part of the contact plug and the upper metal wiring at the same time, by etching the metal layer according to the photoresist pattern defining the wiring area to form the remaining upper metal wiring, the semiconductor device in a simplified process Metal wiring can be formed effectively.

In the foregoing description, the present invention has been described with reference to preferred embodiments, but the present invention is not necessarily limited thereto. Those skilled in the art will appreciate that the present invention may be modified without departing from the spirit of the present invention. It will be readily appreciated that branch substitutions, modifications and variations are possible.

1A to 1J are process flowcharts illustrating a process of forming a lower metal wiring and an upper metal wiring according to a conventional method;

2A to 2H are flowcharts illustrating a process of forming a lower metal wiring and an upper metal wiring according to an embodiment of the present invention.

Claims (7)

Depositing a metal layer on the semiconductor substrate on which the interlayer insulating film is deposited on the patterned lower metal wires; Forming a first photoresist pattern defining a contact region over the deposited metal layer; Forming a contact hole by etching the metal layer and the interlayer insulating layer to expose the lower metal wires according to the first photoresist pattern; Removing the first photoresist pattern, filling the contact hole with a metal material, and planarizing an upper portion of the contact hole to form a contact plug including a portion of the upper metal wire; Forming a second photoresist pattern defining a wiring region on the contact plug formed thereon; and Etching the metal layer according to the second photoresist pattern to form the remaining upper metal wirings Metal wiring forming method of a semiconductor device comprising a. The method of claim 1, The metal layer is formed by using aluminum (Al). The method according to claim 1 or 2, The forming of the contact hole may include performing a first etching process using the interlayer insulating layer as an etching target and a second etching process using the lower metal wiring as an etching target. The method of claim 3, wherein The first etching process, the method of forming a metal wire of the semiconductor device, characterized in that for performing the first reactive ion etching (RIE) using Cl gas and BCL 3 gas. The method of claim 4, wherein The secondary etching process, the method of forming a metal wire of the semiconductor device, characterized in that for performing a secondary reactive ion etching (RIE) using a C 5 F 8 gas. The method of claim 5, wherein And the contact plug including a portion of the upper metal wiring is formed using tungsten (W). The method of claim 6, And the first photoresist pattern or the second photoresist pattern is removed using an ashing process and a solvent.
KR1020070136333A 2007-12-24 2007-12-24 Method for forming metal line of semiconductor device KR20090068637A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107924900A (en) * 2015-09-25 2018-04-17 英特尔公司 Via for the lithographic definition of organic packages substrate scaling

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107924900A (en) * 2015-09-25 2018-04-17 英特尔公司 Via for the lithographic definition of organic packages substrate scaling

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