KR20090052770A - Apparatus and method for down-converting digital frequency in wireless telecommunication system - Google Patents

Apparatus and method for down-converting digital frequency in wireless telecommunication system Download PDF

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Publication number
KR20090052770A
KR20090052770A KR1020070119434A KR20070119434A KR20090052770A KR 20090052770 A KR20090052770 A KR 20090052770A KR 1020070119434 A KR1020070119434 A KR 1020070119434A KR 20070119434 A KR20070119434 A KR 20070119434A KR 20090052770 A KR20090052770 A KR 20090052770A
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signal
digital
filter
converter
multiplier
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KR1020070119434A
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Korean (ko)
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정요안
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포스데이타 주식회사
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Priority to KR1020070119434A priority Critical patent/KR20090052770A/en
Priority to PCT/KR2008/006855 priority patent/WO2009066945A2/en
Publication of KR20090052770A publication Critical patent/KR20090052770A/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/16—Multiple-frequency-changing
    • H03D7/165—Multiple-frequency-changing at least two frequency changers being located in different paths, e.g. in two paths with carriers in quadrature
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/0003—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain
    • H04B1/0007—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain wherein the AD/DA conversion occurs at radiofrequency or intermediate frequency stage
    • H04B1/001—Channel filtering, i.e. selecting a frequency channel within the SDR system

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Superheterodyne Receivers (AREA)

Abstract

The present invention relates to an apparatus and method for digital frequency down conversion, the apparatus comprising: an A / D converter for sampling and converting an analog signal having an intermediate frequency (IF) into a digital signal; A demodulator for demodulating a digital signal using a cosine wave and a sinusoidal signal; A lowpass filter for removing an image signal from the demodulated signal and for lowering a data rate; And a channel filter for generating a baseband signal by filtering the output signal of the lowpass filter.

According to the present invention, configuration and design are simple and debugging is easy. In addition, the number of ADCs and SAW filters can be reduced, which reduces mass production and system cost, and reduces board size, enabling an integrated system and easily changing frequencies. In addition, the RF path is configured briefly.

Description

Apparatus and method for down-converting digital frequency in wireless telecommunication system

The present invention relates to a frequency down converter, and more particularly, to a digital frequency down converter and a method for converting an intermediate frequency signal into a baseband signal in a wireless communication system.

In general, in a wireless communication system, a base station is composed of a remote unit (RU) that is in charge of wireless communication with a terminal and a DU (Digtial Unit) that is in communication with the RU. The part in charge of the Rx function in the RU (Remote Unit) converts an intermediate frequency (Intermediate Frequency) signal input from the RF stage into a baseband signal, and the baseband signal is transmitted to a digital unit (DU). . In this case, in order to convert the intermediate frequency signal into a baseband signal, a frequency down converter is required.

FIG. 1 is a block diagram showing the configuration of a conventional digital frequency down converter, wherein a SAW filter 100, a PLL 110, two multipliers 120 and 130, two LPFs 140 and 150, two ADCs 160 and 170 are included. Referring to FIG. 1, a signal converted into an intermediate frequency signal in an RF terminal is input to an expensive SAW filter 100. After the signal filtered by the SAW filter 100 and the cosine and sine waveform signals output from the PLL 110 are multiplied by the multipliers 120 and 130, the LPF 140 and 150 are multiplied by the multiplier 120 and 130. Is converted into a baseband IQ signal. Each converted I Q signal is input to an analog to digital converter (ADC) 160 and 170 and output as an I baseband signal and a Q baseband signal. In this case, since the ADCs 160 and 170 are used for each of the I Qs, space in a circuit in which each ADC is to be mounted is required, and the circuit becomes complicated. In addition, it takes a lot of time to debug, such as balancing the I signal and the Q signal, and a problem of using an expensive SAW filter 100 at an intermediate frequency (IF) input terminal occurs.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and the technical problem to be solved by the present invention is to convert an analog signal to a digital signal using an A / D converter and then perform frequency conversion to perform an expensive SAW filter. It is an object of the present invention to provide an apparatus and method for digital frequency down conversion of a wireless communication system, which is economically advantageous due to no use.

Another object of the present invention is to sample the intermediate frequency signal input from the RF stage, and to down-convert the image signal to generate a baseband signal, so that the circuit configuration is relatively simple and the digital frequency down of the wireless communication system is easy to debug. To provide a conversion device and method.

In order to solve the above technical problem, the digital frequency down converter according to the present invention, the A / D converter for sampling the analog signal and convert it into a digital signal; A demodulator for demodulating the digital signal using a cosine wave and a sinusoidal signal; A low pass filter for passing only the low frequency band signal of the demodulated signal and reducing the data rate; And a channel filter for generating a baseband signal by filtering the output signal of the lowpass filter.

In order to solve the above technical problem, the digital frequency down conversion method according to the present invention comprises the steps of: sampling the analog signal and converting it into a digital signal; Demodulating the digital signal using a cosine wave and a sinusoidal signal; Passing only the low frequency band signal of the demodulated signal and lowering a data rate; And generating a baseband signal by filtering the signal at which the data rate is down.

According to the present invention, the configuration and design of the frequency down converter is simple and easy to debug. In addition, an I Q unbalance problem, which is a problem in the conventional analog signal processing method, is solved. By reducing the number of A / D converters and SAW filters, it is possible to reduce mass production and system cost. It is possible to reduce board size and to realize compact system and to change frequency easily. In addition, the RF path is briefly configured by performing one conversion on the RF stage using the IF stage at 115 MHz.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings and preferred embodiments. For reference, detailed descriptions of well-known functions and configurations that may unnecessarily obscure the subject matter of the present invention will be omitted in the following description.

2 is a block diagram showing an embodiment of the configuration of the digital frequency down conversion apparatus according to the present invention. The configuration is an A / D converter 200, a demodulator 200, and a direct digital synthesizer 240 (DDS). And a low pass filter 260 and a channel filter 280. 3 shows the frequency spectrum of the input signal and the output signal for each component of the digital frequency down converter according to the present invention.

The A / D converter 200 is input from an RF terminal and converts an analog signal having an intermediate frequency into a digital signal by sampling using a clock signal lower than the intermediate frequency. In the present embodiment, the A / D converter 200 receives a 115 MHz intermediate frequency signal from an RF terminal (not shown), and samples the signal using a 115 MHz intermediate frequency signal lower than the intermediate frequency as a clock signal. Outputs a digital signal. This is because it is accurate and convenient to convert analog signals to digital signals and then demodulate and filter them.

3 (1) and (2) show the frequency spectrum of the input signal and the output signal of the A / D converter 200, wherein (1) is the frequency spectrum of the intermediate frequency signal of 115MHz, (2 ) Is a frequency spectrum of a digital signal of 100 Mbps sampled using the 100 MHz clock signal in the A / D converter 200.

The DDS 240 generates a cosine signal and a sine signal and provides the demodulator 220. For example, in order to output a signal having an intermediate frequency of 15 MHz, the DDS 240 may generate a 15 MHz sine wave and a cosine wave signal and provide the same to the demodulator 220. The demodulator 220 demodulates the digital signal converted through the A / D converter 200 by using the cosine and sinusoidal signals outputted through the DDS 240, and decodes the power of the demodulated signal. Increase the digital gain to increase it.

4 is a block diagram illustrating a more detailed configuration of the demodulator 220, and includes a first multiplier 400 and a second multiplier 450. The first multiplier 400 multiplies the digital signal sampled by the A / D converter 200 and the cosine wave signal to generate a signal input to the low pass filter 260. And a first multiplier 402 for multiplying the digital signal and the cosine wave signal, and a first reinterpreter 404 for increasing the digital gain of the signal output from the first multiplier 402.

The second multiplier 450 generates an IQ digital signal by multiplying the digital signal sampled by the A / D converter 200 and the sine wave signal, and multiplies the digital signal by the sine wave signal. And a second reinterpreter 454 for increasing the digital gain of the signal output from the second multiplier 452.

3 (2) and (3) shows the frequency spectrum of the input signal and the output signal of the demodulator 220, the input signal is frequency-shifted by 15MHz through the demodulator 220, the demodulator 220 A 100 Mbps I digital signal is generated through the first multiplier 400 constituting the second signal, and a 100 Mbps Q digital signal is generated through the second multiplier 450. The reason for using the first reinterpreter 404 and the second reinterpreter 454 is because the power is output less than the intermediate frequency (IF) signal input to the A / D converter 200 is input digital gain to compensate for this To increase the gain.

The low pass filter 260 passes only a low pass filter signal of the demodulated signal and lowers a data rate. 3 (3) and (4) show the frequency spectrum of the input signal and the output signal of the low pass filter 260, it can be seen that the signal having a frequency of 100MHz of the input signal is filtered.

FIG. 5 is a block diagram illustrating a more detailed configuration of the low pass filter 260, and includes a first half band filter unit 500 and a second half band filter unit 550. The first half band filter unit 500 passes only a low frequency band signal of the I digital signals output from the first multiplier 400 and lowers a data rate. A first data width converter 502 for converting a data width of an output signal of the first multiplier 400 to a data width of a first half-band filter 504, an image generated when demodulating the converted signal (image) a first halfband filter 504 for removing the signal and lowering the data rate, and a third reinterpreter 506 for increasing the digital gain of the signal filtered by the first halfband filter 504.

The second half band filter unit 550 passes only a low frequency band signal among the output signals of the second multiplier 450, lowers a data rate, and outputs the output signal of the second multiplier 450. The second data width converter 552 converts the data width to the data width of the second half-band filter 554, and removes an image signal generated during demodulation of the converted signal and lowers the data rate. The second halfband filter 554 and the fourth reinterpreter 556 for increasing the digital gain of the signal filtered by the second halfband filter 554 are included. In the present exemplary embodiment, the first half band filter unit 500 and the second half band filter unit 550 output 100 Mbps signals at a data rate of 20 Mbps through a data rate of 1/5.

The channel filter 280 bandpass filters an output signal of the lowpass filter 260 to generate a baseband signal. 3 (4) and (5) shows the frequency spectrum of the input signal and the output signal of the channel filter 280, only the frequency band of the base band of the input signal is band-passed, other signals are filtered can see.

6 is a block diagram illustrating a more detailed configuration of the channel filter 280, and includes a first channel filter unit 600 and a second channel filter unit 650. The first channel filter unit 600 generates a baseband I signal by filtering the output signal of the first half band filter unit 500, and determines a width of the output data of the first half band filter unit 500. The third data width converter 602 converts the first channel filter 604 and the output signal of the first channel filter 604 to filter the signal from which the data width is converted to generate a baseband I signal. A fifth data width converter 606 converts the data width.

The second channel filter unit 650 filters the output signal of the second half band filter unit 550 to generate a baseband Q signal, and adjusts the width of the output data of the second half band filter unit 550. The fourth data width converter 652 converts the second channel filter 654 for filtering the signal having the converted data width to generate a Q baseband signal, and converts the data width of the output signal of the second channel filter. And a sixth data width converter 656. In the present embodiment, the first channel filter unit and the second channel filter unit receive a 20 Mbps signal and output a data rate of 10 Mbps.

The digital frequency down converter according to the present invention can implement some components as a Field Programmable Gate Array (FPGA). The baseband signal output from the channel filter 280 may be input to a Giga Tranceiver (GTP) through a common public interface (CPRI) interface and transmitted to a channel card (not shown). Therefore, as illustrated in FIG. 7, the digital frequency down conversion apparatus according to the present invention may be implemented as an FPGA by including the CPRI interface unit and the GTP except the ADC. And the present invention can be used in the board (Board) in charge of the mobile Wimax BandWidth 8.75MHz Remote Unit (RU) Rx function. FIG. 8 is a block diagram of a digital frequency down converter according to the present invention designed using a system generator provided by an FPGA company (Xilinx). 8 shows an input terminal and a DDS 240 of the present invention. A digital signal of 100 Mbps sampled using a clock signal is input to the 115 MHz intermediate frequency signal through the input terminal, and the DDS 240 generates a sine wave and a cosine wave signal having a frequency of 15 MHz. 8 shows a demodulator 220. The demodulator 220 multiplies the digital signal by the signal of the DDS 240 to generate an I Q digital signal. 8 (3) shows a low pass filter 260, performs low pass filtering through a half band filter, and also generates a 100 Mbps IQ digital signal as a 20 Mbps IQ digital signal by performing 5 time decimation. 8 (4) shows a channel filter 280 and an output stage, and generates an IQ baseband signal through the channel filter 280, and generates a 10Mbps IQ baseband signal by performing 2 time decimation.

9 is a flowchart illustrating a digital frequency down conversion method according to the present invention. An operation of the digital frequency down converter according to the present invention will be described with reference to FIG. 9.

First, an analog signal is sampled and converted into a digital signal. (Step S910) In this embodiment, a 115 MHz intermediate frequency (IF) signal is input to the A / D converter 200.

The signal input to the A / D converter 200 is sampled with a 100 MHz clock, and the data rate of the output is 100 Mbps. The signal converted into the digital signal by the A / D converter 200 is multiplied and demodulated with the cosine wave and the sinusoidal signal output from the DDS 240 (step S920). The output frequency of the DDS 240 is 15 MHz. Is set to. This is for using an image signal generated during sampling in the A / D converter 200. In addition, the demodulator 220 demodulates and outputs a signal whose power is smaller than that of the input IF signal. To compensate for this, the digital gain is increased by using the first and second reinterpreters 404 and 454.

Then, only the low frequency band signal of the demodulated signal is passed and the data rate is lowered (step S930). More specifically, the digital gained data is 32 bits, which is a half-band filter. Half-band Filter, 504, 554) must be changed to 16 bits. To this end, the bit width is adjusted through the data width converters 502 and 504 and input to the half band filters 504 and 554.

The half band filters 504 and 554 pass only a low frequency band signal among the signals demodulated by the demodulator 220 and lower the data rate (S930). The converted signal is input to the half band filters 504 and 554 to remove an image signal generated during demodulation. It also converts the data rate to 1/5 of the data rate of the input signal. This is to set the baseband I Q data rate to 10Mbps at Mobile Wimax BW 8.75MHz at the end. That is, the low pass filter 260 performs a 5 Time Decimation function to output a data rate of 20 Mbps, and then raises the digital gain through the third and fourth reinterpreters 506 and 556.

The low pass filter 260 should effectively remove adjacent image signals during deciation using a minimum filter tap of Fpass 4.5MHz and Fstop 15MHz. The output signal is input to the channel filter 260 again, and the input data rate is 20 Mbps.

Thereafter, the signal which is down at the data rate of 20 Mbps by the low pass filter 260 is converted into a data width through the third and fourth data width converters 602 and 604, and then the channel filters 604 and 654. The filter is filtered through to generate a baseband signal (step S940).

The channel filter design characteristic is expressed by Equation 1.

[Equation 1]

Bu = Fs (Nused / NFFT)

Where Bu is useful bandwidth and Fs is a baseband sampling rate.

The channel filter 280 performs a 2Time Decimation function together with a filtering function to output an output data rate of 10Mbps. The output baseband I Q signal is input to a CPRI interface block, transmitted to a digital unit (not shown), and then to a channel card (not shown). When the characteristics of the baseband I Q signal are confirmed through a digital to analog converter (DAC), a baseband out as shown in FIG. 10 is indicated by a DAC Sinc Function and sampling (10 MHz).

On the other hand, the present invention described above can also be embodied as computer readable codes on a computer readable recording medium. Computer-readable recording media include any type of recording device that stores data that can be read by a computer system. Examples of computer-readable recording media include ROM, RAM, CD-ROM, magnetic tape, floppy disks, hard disks, optical data storage devices, and also in the form of carrier waves (e.g., transmission over the Internet). It includes what is implemented. The computer readable recording medium can also be distributed over network coupled computer systems so that the computer readable code is stored and executed in a distributed fashion. And functional programs, codes and code segments for implementing the present invention can be easily inferred by programmers in the art to which the present invention belongs.

Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art to which the present invention pertains can implement the present invention in other specific forms without changing the technical spirit or essential features, The examples are to be understood in all respects as illustrative and not restrictive.

In addition, the scope of the present invention is specified by the appended claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts are included in the scope of the present invention. Should be interpreted as

1 is a block diagram showing the configuration of a conventional digital frequency down converter.

2 is a block diagram showing an embodiment of the configuration of the digital frequency down conversion apparatus according to the present invention.

Figure 3 shows the frequency spectrum of the input and output signals for each component of the digital frequency down converter according to the present invention.

4 is a block diagram illustrating a more detailed configuration of the demodulator.

5 shows a more detailed configuration of the lowpass filter in a block diagram.

6 is a block diagram illustrating a more detailed configuration of the channel filter.

FIG. 7 may include a CPRI interface unit and a GTP, except for an A / D converter, to implement a digital frequency down converter according to the present invention as an FPGA.

8 is a block diagram of a digital frequency down converter according to the present invention designed using a system generator.

9 is a flowchart illustrating a digital frequency down conversion method according to the present invention.

10 shows the output baseband out of the channel filter.

Claims (18)

An A / D converter for sampling an analog signal having an intermediate frequency IF and converting the analog signal into a digital signal; A demodulator for demodulating the digital signal using a cosine wave and a sinusoidal signal; A low pass filter for removing an image signal from the demodulated signal and for lowering a data rate; And And a channel filter for generating a baseband signal by filtering the output signal of the lowpass filter. The method of claim 1, wherein the A / D converter is And a digital signal obtained by sampling an intermediate frequency signal using a clock signal having a frequency lower than the intermediate frequency. The method of claim 2, wherein the intermediate frequency signal is And a 115 MHz signal, wherein the clock signal is a 100 MHz signal. The apparatus of claim 1, wherein the demodulator A first multiplier configured to multiply the digital signal converted by the A / D converter and the cosine wave signal to generate an input signal of the low pass filter; And And a second multiplier configured to multiply the digital signal converted by the A / D converter and the sine wave signal to generate an input signal of the low pass filter. The method of claim 4, wherein And a DDS for providing the cosine wave signal and the sinusoidal signal to the demodulator. The method of claim 5, wherein the output frequency of the DDS is And a frequency equal to the output frequency of the A / D converter. The method of claim 4, wherein the first multiplier A first multiplier for multiplying the digital signal and the cosine wave signal; And a first reinterpreter for increasing the digital gain of the output signal of the first multiplier, The second multiplier is A second multiplier that multiplies the digital signal by a sinusoidal signal; And a second reinterpreter for increasing the digital gain of the output signal of the first multiplier. The filter of claim 4, wherein the low pass filter A first half band filter unit configured to pass only a low frequency band signal of the output signal of the first multiplier and reduce a data rate; And And a second half band filter unit for passing only a low frequency band signal of the output signal of the second multiplier and lowering a data rate. The method of claim 8, wherein the first half-band filter unit A first data width converter for converting a data width of the first multiplier output signal into a data width of a first half band filter; A first half band filter for removing an image signal generated during demodulation of the converted signal and for lowering a data rate; And a third reinterpreter for increasing the digital gain of the signal filtered by the first halfband filter. The second half band filter unit A second data width converter converting a data width of the second multiplier output signal into a data width of a first half band filter; A second halfband filter for removing an image signal generated during demodulation of the converted signal and for lowering a data rate; And a fourth reinterpreter for increasing the digital gain of the signal filtered by the second halfband filter. The method of claim 8, wherein the first halfband filter unit and the second halfband filter unit A digital frequency down converter, which outputs at a data rate of 20 Mbps using a 100 Mbps signal as an input. The method of claim 8, wherein the channel filter A first channel filter unit generating a baseband I signal by filtering an output signal of the first half band filter unit; And And a second channel filter unit configured to filter an output signal of the second halfband filter unit to generate a baseband Q signal. The method of claim 11, wherein the first channel filter unit A third data width converter configured to convert widths of output data of the first half-band filter unit; A first channel filter filtering the signal having the converted data width to generate a baseband I signal; And A fifth data width converter configured to convert a data width of an output signal of the first channel filter, The second channel filter part A fourth data width converter configured to convert widths of output data of the first half band filter unit; A second channel filter for generating a baseband Q signal by filtering the signal having the converted data width; And And a sixth data width converter for converting a data width of the output signal of the second channel filter. The method of claim 11, wherein the first channel filter unit and the second channel filter unit A digital frequency down converter, which outputs a data rate of 10 Mbps by inputting a 20 Mbps signal. (a) sampling an analog signal having an intermediate frequency and converting the analog signal into a digital signal including an image signal; (b) demodulating the digital signal using a cosine wave and a sinusoidal signal; (c) removing said image signal of said demodulated signal and lowering a data rate; And and (d) channel filtering the signal at which the data rate is down to generate a baseband signal. The method of claim 14, wherein step (a) And generating a digital signal by sampling the intermediate frequency signal using a clock signal. The method of claim 15, wherein step (b) And multiplying the digital signal by a cosine wave and a sinusoidal signal to demodulate the signal into I and Q signals. The method of claim 16, wherein step (c) And low-passing the I and Q signals, and then downing them to a predetermined data rate. 18. The method of claim 17, wherein step (d) And filtering the signal at which the data rate is down to generate a baseband signal.
KR1020070119434A 2007-11-21 2007-11-21 Apparatus and method for down-converting digital frequency in wireless telecommunication system KR20090052770A (en)

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KR1020070119434A KR20090052770A (en) 2007-11-21 2007-11-21 Apparatus and method for down-converting digital frequency in wireless telecommunication system
PCT/KR2008/006855 WO2009066945A2 (en) 2007-11-21 2008-11-20 Apparatus and method for down-converting frequency in wireless communication system

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