KR20080018846A - 스탬핑된 리드프레임 및 그 제조 방법 - Google Patents
스탬핑된 리드프레임 및 그 제조 방법 Download PDFInfo
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- KR20080018846A KR20080018846A KR20070085565A KR20070085565A KR20080018846A KR 20080018846 A KR20080018846 A KR 20080018846A KR 20070085565 A KR20070085565 A KR 20070085565A KR 20070085565 A KR20070085565 A KR 20070085565A KR 20080018846 A KR20080018846 A KR 20080018846A
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- Prior art keywords
- leadframe
- leads
- thickness
- portions
- die pad
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- 238000000034 method Methods 0.000 title claims abstract description 29
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 239000000463 material Substances 0.000 claims description 15
- 238000000465 moulding Methods 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000011159 matrix material Substances 0.000 claims description 6
- 239000004020 conductor Substances 0.000 claims description 3
- 239000008393 encapsulating agent Substances 0.000 claims description 2
- 238000006073 displacement reaction Methods 0.000 claims 1
- 239000002699 waste material Substances 0.000 abstract 1
- 230000008569 process Effects 0.000 description 11
- 238000005538 encapsulation Methods 0.000 description 10
- 239000004065 semiconductor Substances 0.000 description 7
- 238000005530 etching Methods 0.000 description 5
- 230000007246 mechanism Effects 0.000 description 5
- 235000012431 wafers Nutrition 0.000 description 4
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
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- 238000010586 diagram Methods 0.000 description 2
- 238000003631 wet chemical etching Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
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- H—ELECTRICITY
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- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H01R43/00—Apparatus or processes specially adapted for manufacturing, assembling, maintaining, or repairing of line connectors or current collectors or for joining electric conductors
- H01R43/16—Apparatus or processes specially adapted for manufacturing, assembling, maintaining, or repairing of line connectors or current collectors or for joining electric conductors for manufacturing contact members, e.g. by punching and by bending
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4842—Mechanical treatment, e.g. punching, cutting, deforming, cold welding
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Abstract
Description
Claims (20)
- 적어도 다이 패드(die pad), 프레임, 상기 다이 패드를 상기 프레임에 접속시키는 타이바들(tie bars) 및 복수의 리드들을 갖는 리드리스 패키지(leadless package)용 스탬핑된 리드프레임(stamped leadframe)을 제조하는 방법에 있어서,상기 리드들의 제1 및 제2 부분들을 클램핑(clamping)하는 단계; 및상기 제2 부분이 상기 제1 부분에 실질적으로 평행하게 접속되고 변위되도록, 상기 제1 부분에 관련하여 상기 제2 부분을 상기 제1 부분의 두께보다 짧은 거리만큼 깎는 단계를 포함하는, 스탬핑된 리드프레임 제조 방법.
- 제1항에 있어서, 상기 제1 및 제2 부분들의 두께를 실질적으로 유지하도록 상기 리드들의 제1 부분의 변위를 제어하는 단계를 포함하는, 스탬핑된 리드프레임 제조 방법.
- 제1항에 있어서, 상기 리드들의 제2 부분은 상기 제1 부분의 두께의 1/4 내지 3/4 사이의 거리만큼 깎이는, 스탬핑된 리드프레임 제조 방법.
- 제1항에 있어서, 상기 리드들의 제2 부분을 깎는 단계는 상기 제1 및 제2 부분들의 표면들에 실질적으로 수직인 측벽을 갖는 상기 제1 및 제2 부분들에 인접한 오목 부분(reentrant portion)을 생성하는 것인, 스탬핑된 리드프레임 제조 방법.
- 제1항에 있어서,상기 타이바들의 제1 및 제2 부분들을 클램핑하는 단계; 및상기 제2 부분이 상기 제1 부분에 실질적으로 평행하게 접속되고 변위되도록, 상기 제1 부분에 관련하여 상기 타이바의 제2 부분을 상기 제1 부분의 타이바의 두께보다 짧은 거리만큼 깎는 단계를 포함하는, 스탬핑된 리드프레임 제조 방법.
- 제5항에 있어서, 상기 타이바들의 제1 부분은 분리 부분들을 포함하며, 상기 타이바의 제2 부분은 깎이는 그들 사이의 중간 부분에 위치되는, 스탬핑된 리드프레임 제조 방법.
- 제5항에 있어서, 몰딩 이후 상기 타이바들의 제1 부분의 표면들이 노출되도록 상기 리드프레임을 몰딩하는 단계를 더 포함하는, 스탬핑된 리드프레임 제조 방법.
- 제1항에 있어서,상기 다이 패드의 제1 및 제2 부분들을 클램핑하는 단계; 및상기 제2 부분이 상기 제1 부분에 실질적으로 평행하게 접속되고 변위되도 록, 상기 제1 부분에 관련하여 상기 다이 패드의 제2 부분을 상기 다이 패드의 제1 부분의 두께보다 짧은 거리만큼 깎는 단계를 포함하는, 스탬핑된 리드프레임 제조 방법.
- 제1항에 있어서, 몰딩 이후 상기 다이의 표면 및 상기 리드들의 상기 제1 부분의 표면들이 노출되도록 상기 리드프레임을 몰딩하는 단계를 더 포함하는, 스탬핑된 리드프레임 제조 방법.
- 리드프레임에 있어서,다이 패드, 프레임 및 상기 다이 패드를 상기 프레임에 접속시키는 타이바들; 및각각이 제1 부분 및 제2 부분을 포함하는 복수의 리드들로서, 상기 리드들의 제2 부분은 상기 제1 부분에 실질적으로 평행하게 접속되고 상기 제1 부분에 관련하여 상기 제1 부분의 두께보다 짧은 거리만큼 변위되는, 리드들을 포함하는, 리드프레임.
- 제10항에 있어서, 상기 리드들의 상기 제1 및 제2 부분들은 실질적으로 동일한 두께를 갖는, 리드프레임.
- 제10항에 있어서, 상기 리드들의 제2 부분은 상기 제1 부분의 두께의 1/4 내 지 3/4의 거리만큼 상기 제1 부분으로부터 변위되는, 리드프레임.
- 제10항에 있어서, 상기 제1 및 제2 부분들의 표면들에 실질적으로 수직인 측벽을 갖는 상기 제1 및 제2 부분들에 인접한 오목 부분을 포함하는, 리드프레임.
- 제10항에 있어서, 각각의 타이바는 제1 부분 및 제2 부분을 포함하고, 상기 제2 부분은 상기 제1 부분에 접속되고 상기 제1 부분에 관련하여 상기 타이바의 제1 부분의 두께보다 짧은 거리만큼 변위되는, 리드프레임.
- 제14항에 있어서, 상기 타이바의 제1 부분은 분리 부분들을 포함하며, 상기 타이바의 제2 부분은 상기 타이바의 제1 부분의 분리 부분들에 관련하여 변위되는 그들 사이의 중간 부분에 위치하는, 리드프레임.
- 제14항에 있어서, 상기 타이바들의 제1 부분의 표면들은 몰딩 이후 노출되도록 구성되는, 리드프레임.
- 제10항에 있어서, 상기 다이 패드는 제1 부분 및 제2 부분을 포함하고, 상기 다이 패드의 제2 부분은 상기 제1 부분에 평행하고 상기 제1 부분에 관련하여 상기 다이 패드의 제1 부분의 두께보다 짧은 거리만큼 변위되는, 리드프레임.
- 제10항에 있어서, 상기 다이 패드의 표면과 상기 리드들의 제1 부분의 표면들은 몰딩 이후 노출되도록 구성되는, 리드프레임.
- 집적 회로 다이용 패키지에 있어서,집적 회로 다이;상기 다이를 덮는 캡슐화 물질(encapsulant material)로 형성된 패키지 몸체;각각이 제1 부분 및 제2 부분을 갖는 복수의 리드들로서, 상기 제2 부분은 상기 제1 부분에 실질적으로 평행하게 접속되고 상기 제1 부분에 관련하여 상기 제1 부분의 두께보다 짧은 거리만큼 변위되는, 리드들; 및상기 다이와 상기 리드들의 제2 부분 사이에 접속된 전기 전도체들을 포함하고,상기 다이 패드의 표면 및 상기 리드들의 제1 부분의 표면들은 공통 평면 상에 노출된, 집적 회로 다이용 패키지.
- 복수의 캡슐화된 집적 회로 다이 패키지들을 만들기 위한 리드프레임 구조에 있어서,매트릭스로 정렬된 복수의 상호접속된 금속 프레임들;각각의 상기 프레임들의 내부 에지 내에서 타이바들에 의해 접속된 다이 패드; 및각각의 프레임의 내부 에지에 접속된 복수의 리드들로서, 상기 리드들은 제1 부분 및 제2 부분을 포함하고, 상기 제2 부분은 상기 제1 부분에 실질적으로 평행하고 상기 제1 부분에 관련하여 상기 제1 부분의 두께보다 짧은 거리만큼 변위되는, 리드프레임 구조.
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US11/509,860 US8174096B2 (en) | 2006-08-25 | 2006-08-25 | Stamped leadframe and method of manufacture thereof |
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Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7838339B2 (en) * | 2008-04-04 | 2010-11-23 | Gem Services, Inc. | Semiconductor device package having features formed by stamping |
CN102214631A (zh) * | 2010-04-09 | 2011-10-12 | 飞思卡尔半导体公司 | 用于半导体装置的引线框 |
TWI557183B (zh) * | 2015-12-16 | 2016-11-11 | 財團法人工業技術研究院 | 矽氧烷組成物、以及包含其之光電裝置 |
US8648450B1 (en) * | 2011-01-27 | 2014-02-11 | Amkor Technology, Inc. | Semiconductor device including leadframe with a combination of leads and lands |
CN102738024A (zh) * | 2011-04-01 | 2012-10-17 | 飞思卡尔半导体公司 | 半导体封装及其引线框 |
DE102012022960B4 (de) * | 2012-11-23 | 2021-12-30 | Schott Ag | Gehäusebauteil, insbesondere für ein Elektronikgehäuse, und Verfahren zur Herstellung eines Gehäusebauteils |
CN103050468A (zh) * | 2012-12-17 | 2013-04-17 | 华天科技(西安)有限公司 | 一种带有梯形孔的冲压框架的扁平多芯片封装件 |
CN103021996A (zh) * | 2012-12-28 | 2013-04-03 | 华天科技(西安)有限公司 | 一种带有方形凹槽的冲压框架的扁平多芯片封装件及其制作方法 |
TWI492335B (zh) * | 2013-02-08 | 2015-07-11 | 矽品精密工業股份有限公司 | 電子裝置及其封裝結構 |
CN103594448A (zh) * | 2013-11-15 | 2014-02-19 | 杰群电子科技(东莞)有限公司 | 一种引线框架 |
KR102326069B1 (ko) * | 2015-07-29 | 2021-11-12 | 엘지디스플레이 주식회사 | 유기발광 다이오드 표시장치 |
JP6576796B2 (ja) * | 2015-11-05 | 2019-09-18 | 新光電気工業株式会社 | リードフレーム及びその製造方法、半導体装置 |
DE102016125521B4 (de) * | 2016-12-22 | 2020-10-15 | Infineon Technologies Ag | Gemeinsames Verfahren zum Verbinden eines elektronischen Chips mit einem Verbinderkörper und zum Ausbilden des Verbinderkörpers |
US10262928B2 (en) * | 2017-03-23 | 2019-04-16 | Rohm Co., Ltd. | Semiconductor device |
WO2019044177A1 (ja) * | 2017-08-30 | 2019-03-07 | 日立オートモティブシステムズ株式会社 | パワー半導体装置及びその製造方法 |
FR3089055B1 (fr) * | 2018-11-23 | 2021-08-27 | Linxens Holding | Procédé de fabrication d’un support flexible de circuit intégré, support flexible de circuit intégré, module comprenant un support flexible et un circuit intégré. |
US20200227343A1 (en) * | 2019-01-11 | 2020-07-16 | Chang Wah Technology Co., Ltd. | Semiconductor device package |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02308563A (ja) | 1989-05-23 | 1990-12-21 | Shinko Electric Ind Co Ltd | リードフレーム |
US5172214A (en) | 1991-02-06 | 1992-12-15 | Motorola, Inc. | Leadless semiconductor device and method for making the same |
EP0550013B1 (en) * | 1991-12-27 | 2000-07-26 | Fujitsu Limited | Semiconductor device and method of producing the same |
US5458158A (en) * | 1993-03-30 | 1995-10-17 | Toyo Communication Equipment Co., Ltd. | Lead cutting apparatus and an anticorrosive coat structure of lead |
US6143981A (en) | 1998-06-24 | 2000-11-07 | Amkor Technology, Inc. | Plastic integrated circuit package and method and leadframe for making the package |
US6208020B1 (en) * | 1999-02-24 | 2001-03-27 | Matsushita Electronics Corporation | Leadframe for use in manufacturing a resin-molded semiconductor device |
JP4266429B2 (ja) | 1999-03-10 | 2009-05-20 | パナソニック株式会社 | 樹脂封止型半導体装置およびその製造方法 |
JP3461332B2 (ja) * | 1999-09-10 | 2003-10-27 | 松下電器産業株式会社 | リードフレーム及びそれを用いた樹脂パッケージと光電子装置 |
JP4547086B2 (ja) * | 2000-12-25 | 2010-09-22 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2003124421A (ja) | 2001-10-15 | 2003-04-25 | Shinko Electric Ind Co Ltd | リードフレーム及びその製造方法並びに該リードフレームを用いた半導体装置の製造方法 |
US7425756B2 (en) * | 2002-04-30 | 2008-09-16 | Renesas Technology Corp. | Semiconductor device and electronic device |
JP4624170B2 (ja) * | 2005-04-25 | 2011-02-02 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP2008002499A (ja) | 2006-06-20 | 2008-01-10 | Ntn Corp | 車輪用軸受装置 |
KR20080002499A (ko) * | 2006-06-30 | 2008-01-04 | 삼성테크윈 주식회사 | 반도체 패키지용 리드 프레임, 그 제조방법 및 반도체패키지 |
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US20080122048A1 (en) | 2008-05-29 |
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