KR20070014671A - Substrate manufacturing method - Google Patents

Substrate manufacturing method Download PDF

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Publication number
KR20070014671A
KR20070014671A KR1020050069504A KR20050069504A KR20070014671A KR 20070014671 A KR20070014671 A KR 20070014671A KR 1020050069504 A KR1020050069504 A KR 1020050069504A KR 20050069504 A KR20050069504 A KR 20050069504A KR 20070014671 A KR20070014671 A KR 20070014671A
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South Korea
Prior art keywords
solder resist
photo solder
substrate
resist film
base substrate
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KR1020050069504A
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Korean (ko)
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변형직
이윤정
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삼성전자주식회사
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Priority to KR1020050069504A priority Critical patent/KR20070014671A/en
Publication of KR20070014671A publication Critical patent/KR20070014671A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Non-Metallic Protective Coatings For Printed Circuits (AREA)

Abstract

A substrate manufacturing method is provided to improve reliability of a package by intensifying the adhesiveness between hetero materials using an enlarged surface area of a solder resist layer. A metal thin film structure composed of a metal film and a photo solder resist layer at one surface of the metal film is attached to a base substrate(21) with a circuit pattern by using a thermo compression binding process. At this time, the photo solder resist layer is attached to the base substrate. An aiming roughness is obtained from the photo solder resist layer by removing the metal film from the metal thin film structure. Then, exposing and developing processes are performed on the photo solder resist layer.

Description

기판 제조 방법{SUBSTRATE MANUFACTURING METHOD}Substrate manufacturing method {SUBSTRATE MANUFACTURING METHOD}

도 1은 종래 기술에 따른 기판 제조 방법에 의해 제조된 기판을 포함하는 반도체 칩 패키지 구조를 보여주는 단면도이다.1 is a cross-sectional view showing a semiconductor chip package structure including a substrate manufactured by a substrate manufacturing method according to the prior art.

도 2a 내지 도 2e는 본 발명에 따른 기판 제조 방법을 나타낸 공정도이다.2a to 2e is a process chart showing a substrate manufacturing method according to the present invention.

도 3은 본 발명에 따른 기판 제조 방법에 의해 제조된 기판을 포함하는 반도체 칩 패키지 구조를 보여주는 단면도이다.3 is a cross-sectional view illustrating a semiconductor chip package structure including a substrate manufactured by the substrate manufacturing method according to the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

10; 반도체 칩 패키지 11; 반도체 칩10; Semiconductor chip package 11; Semiconductor chip

20; 기판 21; 베이스 기판20; Substrate 21; Base substrate

22; 배선패턴 23; 본드 핑거22; Wiring pattern 23; Bond finger

24; 볼 패드 25; 비아24; Ball pad 25; Via

27; 금속 박막 구조체 28; 금속층27; Metal thin film structure 28; Metal layer

29; 포토솔더레지스트막 30; 접착제29; Photo solder resist film 30; glue

35; 본딩와이어 37; 수지 성형부35; Bonding wire 37; Resin molding

40; 솔더 볼40; Solder ball

본 발명은 반도체 장치에 관한 것으로서, 더욱 상세하게는 회로패턴을 보호하기 위한 보호막을 가지며 반도체 부품의 실장 수단으로서 사용되는 기판 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a substrate manufacturing method having a protective film for protecting a circuit pattern and used as mounting means of a semiconductor component.

일반적으로 기판은 베이스 기판(또는 "코어(Core)"라고도 함) 상하 면에 형성된 회로패턴이 보호막으로 덮여져 보호되는 구조이다. 보호막으로서는 통상 솔더레지스트(Solder Resist)가 사용된다. 최근에는 보호막으로서 감광성을 갖는 포토 솔더레지스트(PSR; Photo Solder Resist)가 주로 사용된다.In general, a substrate is a structure in which circuit patterns formed on upper and lower surfaces of a base substrate (also referred to as a “core”) are covered with a protective film to protect the substrate. As a protective film, a solder resist is usually used. Recently, a photo solder resist (PSR) having a photosensitive property is mainly used as a protective film.

종래의 기판 제조 방법은 포토 솔더레지스트를 프린팅 하는 방법에 의해 형성하였다. 기판에 포토 솔더레지스트를 프린팅 하기 위해서는 포토 솔더레지스트의 점도가 낮아야 하는데, 이를 위하여 프린팅에 사용되는 포토 솔더레지스트는 상당량의 솔벤트(solvent)를 함유한다. 그러나 솔벤트는 포토 솔더레지스트를 경화하는 과정에서 휘발되어 포토 솔더레지스트의 표면 접착력을 약화시킨다. 또한 포토 솔더레지스트는 수분 흡수가 잘되고 접착력이 약하다. 이에 따라 포토 솔더레지스트와 관련된 여러 가지 불량이 빈번하게 발생된다.The conventional substrate manufacturing method was formed by the method of printing a photo solder resist. In order to print photo solder resist on a substrate, the viscosity of the photo solder resist must be low. For this purpose, the photo solder resist used for printing contains a large amount of solvent. However, the solvent is volatilized in the process of curing the photo solder resist, weakening the surface adhesion of the photo solder resist. In addition, the photo solder resist absorbs moisture well and has poor adhesion. As a result, various defects related to photo solder resist are frequently generated.

도 1은 종래 기술에 따른 기판 제조 방법에 의해 제조된 기판을 포함하는 반도체 칩 패키지 구조를 보여주는 단면도이다.1 is a cross-sectional view showing a semiconductor chip package structure including a substrate manufactured by a substrate manufacturing method according to the prior art.

도 1에 도시된 반도체 칩 패키지(110)는 BGA 형태의 패키지 구조로서, 구리 재질의 회로패턴(121)을 보호하기 위한 보호막으로 포토 솔더레지스트막(127)이 형성된 기판을 사용한 예이다. 반도체 칩(111)이 기판(120)의 보호막(127) 상에 접착 제(130)로 부착되며, 에폭시 몰딩 컴파운드(Epoxy Molding Compound; EMC)로 형성되는 수지 성형부(137)에 의해 보호되는 구조이다.The semiconductor chip package 110 illustrated in FIG. 1 is a BGA type package structure, and is an example of using a substrate on which a photo solder resist layer 127 is formed as a protective layer for protecting a circuit pattern 121 made of copper. The semiconductor chip 111 is attached to the protective film 127 of the substrate 120 with an adhesive 130 and is protected by the resin molding part 137 formed of an epoxy molding compound (EMC). to be.

그러나 이와 같은 반도체 칩 패키지(110)는 패키지 내에 침투된 수분의 팽창으로 인하여 패키지 크랙(crack)이나 박리(delamination) 또는 스웰링(swelling) 현상이 종종 발생된다. 주로 발생되는 계면은 포토 솔더레지스트막(127)과 회로패턴(122), 포토 솔더레지스트막(127)과 접착제(130), 포토 솔더레지스트막(127)과 수지 성형부(137)이다. 즉 포토 솔더레지스트 소재로 인해 모든 문제가 발생되며, 그에 따라 패키지 신뢰성이 저하된다는 문제점이 있다.However, such a semiconductor chip package 110 often causes a package crack, delamination or swelling due to the expansion of moisture permeated into the package. Mainly generated interfaces are the photo solder resist film 127 and the circuit pattern 122, the photo solder resist film 127 and the adhesive 130, the photo solder resist film 127 and the resin molding 137. That is, all the problems are caused by the photo solder resist material, and thus there is a problem that the package reliability is lowered.

따라서 본 발명의 목적은 포토 솔더레지스트막의 결합력을 증가시킬 수 있는 기판 제조 방법을 제공하여 패키지 신뢰성이 향상된 반도체 칩 패키지의 제조를 가능하게 하는 데에 있다.Accordingly, an object of the present invention is to provide a substrate manufacturing method that can increase the bonding force of the photo solder resist film to enable the manufacture of a semiconductor chip package with improved package reliability.

이와 같은 목적을 달성하기 위하여, 본 발명은 포토 솔더레지스트막의 표면에 거칠기를 주어 표면적을 증가시킴으로써 결합 면적이 증가시킨 기판 제조 방법을 제공한다.In order to achieve this object, the present invention provides a substrate manufacturing method in which the bonding area is increased by increasing the surface area by giving a roughness to the surface of the photo solder resist film.

본 발명에 따른 기판 제조 방법은, 금속층의 일면에 포토 솔더레지스트막이 형성된 금속 박막 구조체를 회로패턴이 형성된 베이스 기판의 적어도 일면에 열 압착하여 포토 솔더레지스트막이 베이스 기판에 접하게 부착하는 단계와, 금속 박막 구조체에서 금속층 전체를 에칭으로 제거하며 포토 솔더레지스트막의 표면에 거칠 기를 형성하는 단계 및 포토 솔더레지스트막을 노광 및 현상하여 외부 접속에 필요한 부분을 개방시키는 단계를 포함한다.The substrate manufacturing method according to the present invention comprises the steps of thermally compressing a metal thin film structure having a photo solder resist film formed on one surface of a metal layer to at least one surface of a base substrate on which a circuit pattern is formed so that the photo solder resist film is in contact with the base substrate; Etching to remove the entire metal layer from the structure, forming a roughness on the surface of the photo solder resist film, and exposing and developing the photo solder resist film to open portions necessary for external connection.

본 발명에 따른 기판 제조 방법의 실시 양태에 있어서, 금속 박막 구조체의 금속층은 구리 재질의 금속층일 수 있다. 그리고, 금속 박막 구조체를 부착하는 단계는 베이스 기판의 상면과 하면에 금속 박막 구조체를 부착하는 단계인 것이 바람직하다. 또한 회로패턴은 와이어 본딩용 본드 핑거(bond finger)와 볼 부착용 볼 패드(ball pad)를 포함할 수 있다.In an embodiment of the substrate manufacturing method according to the invention, the metal layer of the metal thin film structure may be a metal layer of copper material. In addition, the attaching the metal thin film structure is preferably the step of attaching the metal thin film structure to the upper and lower surfaces of the base substrate. In addition, the circuit pattern may include a bond finger for wire bonding and a ball pad for ball attachment.

이하 첨부 도면을 참조하여 본 발명에 따른 기판 제조 방법의 실시예를 보다 상세하게 설명하고자 한다. 본 실시예의 기판 제조 방법은 금속 박막 구조체로서 포토 솔더레지스트가 구리 재질의 금속층의 일 면에 코팅된 PCC(PSR Coated Cu)의 금속 박막 구조체를 열 압착 방식으로 부착하는 공정을 이용한다.Hereinafter, exemplary embodiments of a substrate manufacturing method according to the present invention will be described in detail with reference to the accompanying drawings. The substrate manufacturing method of this embodiment uses a process of attaching a metal thin film structure of PSC Coated Cu (PCC) coated on one surface of a metal layer made of copper as a metal thin film structure by thermocompression bonding.

도 2a 내지 도 2e는 본 발명에 따른 기판 제조 방법을 나타낸 공정도이다.2a to 2e is a process chart showing a substrate manufacturing method according to the present invention.

먼저, 도 2a에 도시된 바와 같이, 베이스 기판(21)에 구리로 회로패턴(21)을 형성한다. 여기서, 베이스 기판(21)은 CCL(Copper Clad Laminates) 기판으로서 상면과 하면에 회로패턴(22)이 형성된다. 회로패턴(22)은 와이어 본딩을 위하여 베이스 기판(21)의 상면에 형성되는 본드 핑거(23)와 베이스 기판(21)의 하면에 형성되는 볼 패드(24) 및 베이스 기판(21)을 관통하여 베이스 기판(21) 상하면의 회로패턴(22)을 연결하는 비아(25)를 포함한다.First, as shown in FIG. 2A, the circuit pattern 21 is formed of copper on the base substrate 21. Here, the circuit board 22 is formed on the upper and lower surfaces of the base substrate 21 as a CCL (Copper Clad Laminates) substrate. The circuit pattern 22 penetrates through the bond finger 23 formed on the upper surface of the base substrate 21 and the ball pad 24 and the base substrate 21 formed on the lower surface of the base substrate 21 for wire bonding. The via 25 may be connected to the circuit patterns 22 on the upper and lower surfaces of the base substrate 21.

다음으로, 도 2b에 도시된 바와 같이, 구리 재질로 구성되는 금속층(28)의 일면에 포토 솔더레지스트막(29)이 코팅된 금속 박막 구조체(27)를 베이스 기판(21)의 상면과 하면에 각각 열 압착하여 부착한다. 열 압착이 완료된 상태는 도 2c에 나타나 있다. 포토 솔더레지스트막(29)이 베이스 기판(21)의 상면과 하면에 접한 상태에서 열 압착함으로써, 포토 솔더레지스트막(29)이 회로패턴(22)을 덮으며 비아(25) 부분에도 채워진다. 비아(25) 부분에 채워지는 것을 고려하여 최초 금속 박막 구조체(27)에서 포토 솔더레지스트막(29) 두께가 설정되는 것이 바람직하다. 여기서, 금속층(28)에 코팅되는 포토 솔더레지스트막(29)은 베이스 기판(21)에 형성하고자 하는 보호막의 재질이면 다른 재질, 예컨대 폴리이미드로 대체될 수 있다.Next, as shown in FIG. 2B, the metal thin film structure 27 having the photo solder resist film 29 coated on one surface of the metal layer 28 made of copper is formed on the upper and lower surfaces of the base substrate 21. Each is thermally pressed and attached. The state in which the thermal compression is completed is shown in FIG. 2C. The photo solder resist film 29 is thermally compressed in a state where the photo solder resist film 29 is in contact with the top and bottom surfaces of the base substrate 21, so that the photo solder resist film 29 covers the circuit pattern 22 and is also filled in the via 25. The thickness of the photo solder resist film 29 is preferably set in the first metal thin film structure 27 in consideration of filling in the via 25 portion. Here, the photo solder resist layer 29 coated on the metal layer 28 may be replaced with another material, for example, polyimide, as long as it is a material of the protective film to be formed on the base substrate 21.

그리고나서, 금속 박막 구조체(27)의 금속층(28)을 에칭에 의하여 완전히 제거한다. 금속층(28)이 제거 완료된 상태가 도 2d에 나타나 있다. 에칭이 이루어지는 과정에서 포토 솔더레지스트막(29)의 표면에는 미세한 거칠기(29a)가 형성된다. 이에 의해 포토 솔더레지스트막(29)의 표면적이 증가된다. 과도 에칭(over etching)에 의해 거칠기(29a)를 증가시키는 것도 가능하다. 회로패턴(22)을 덮는 포토 솔더레지스트막(29)은 열 압착되기 때문에 완곡이 없어진다. 이에 의해 포토 솔더레지스트막(29)의 단차로 인하여 발생될 수 있는 불량이 줄어든다. 예를 들어 포토 솔도레지스트막(29)의 완곡으로 인한 보이드(void)와 크랙(crack)의 발생, 와이어 본딩 불량이 줄어든다.Then, the metal layer 28 of the metal thin film structure 27 is completely removed by etching. The state in which the metal layer 28 has been removed is shown in FIG. 2D. In the process of etching, fine roughness 29a is formed on the surface of the photo solder resist film 29. This increases the surface area of the photo solder resist film 29. It is also possible to increase the roughness 29a by over etching. Since the photo solder resist film 29 covering the circuit pattern 22 is thermocompressed, there is no curvature. This reduces the defects that may occur due to the step of the photo solder resist film 29. For example, generation of voids and cracks due to curvature of the photosolde resist film 29 and poor wire bonding are reduced.

다음으로, 도 2e에 도시된 바와 같이, 포토 솔더레지스트막(29)을 노광 및 현상하여 외부 접속에 필요한 부분, 즉 본드 핑거(23)와 볼 패드(24)를 개방시킨 다. 여기서, 포토 솔더레지스트막(29)은 자체로서 감광성을 가지기 때문에 별도로 포토레지스트를 도포하는 공정을 생략하는 것이 가능하게 된다. 이에 의해 기판(20)의 제조가 완료된다.Next, as shown in FIG. 2E, the photo solder resist film 29 is exposed and developed to open portions necessary for external connection, that is, the bond fingers 23 and the ball pads 24. Here, the photo solder resist film 29 itself has photosensitivity so that the step of applying the photoresist separately can be omitted. Thereby, manufacture of the board | substrate 20 is completed.

도 3은 본 발명에 따른 기판 제조 방법에 의해 제조된 기판을 포함하는 반도체 칩 패키지 구조를 보여주는 단면도이다.3 is a cross-sectional view illustrating a semiconductor chip package structure including a substrate manufactured by the substrate manufacturing method according to the present invention.

도 3에 도시된 반도체 칩 패키지(10)는 전술한 본 발명의 기판 제조 방법에 의해 제조된 기판(20)이 적용된 일 예이다. 기판(20)의 포토 솔더레지스트막(29) 위에 접착제(30)를 사용하여 반도체 칩(11)이 부착된다. 반도체 칩(11)과 기판(20)의 본드 핑거(23)가 본딩 와이어(35)에 의해 전기적으로 연결된다. 그리고 기판(20)의 상면 상부가 에폭시 몰딩 컴파운드로 형성되는 수지 성형부(37)에 의해 밀봉된다. 수지 성형부(37)는 본딩 와이어(35)와 그 접합 부분도 밀봉한다. 반도체 칩(11)이 실장된 기판(20)의 다른 면에 형성된 볼 패드(24)에는 외부 접속 볼(40)이 접합되어 외부와의 전기적인 연결을 수행한다.The semiconductor chip package 10 shown in FIG. 3 is an example to which the substrate 20 manufactured by the above-described substrate manufacturing method of the present invention is applied. The semiconductor chip 11 is attached to the photo solder resist film 29 of the substrate 20 using the adhesive 30. The bond chip 23 of the semiconductor chip 11 and the substrate 20 is electrically connected by the bonding wire 35. The upper portion of the upper surface of the substrate 20 is sealed by the resin molding portion 37 formed of an epoxy molding compound. The resin molded part 37 also seals the bonding wire 35 and its joint portion. An external connection ball 40 is bonded to the ball pad 24 formed on the other surface of the substrate 20 on which the semiconductor chip 11 is mounted to perform electrical connection with the outside.

여기서, 포토 솔더레지스트막(29)의 표면에는 미세한 거칠기(29a)가 형성되어 있기 때문에 접착제(30)와의 접합 면적이 넓어져 결합력이 증가된다. 그리고 수지 성형부(37)와 접하는 포토 솔더레지스트막(29)의 표면에도 미세한 거칠기(29a)가 형성되어 있기 때문에 수지 성형부(37)와의 접합 면적이 넓어져 결합력이 증가된다.Here, since the fine roughness 29a is formed on the surface of the photo solder resist film 29, the bonding area with the adhesive 30 is enlarged, and the bonding force is increased. Further, since the fine roughness 29a is formed on the surface of the photo solder resist film 29 in contact with the resin molded part 37, the bonding area with the resin molded part 37 is widened, and the bonding force is increased.

한편, 본 발명에 따른 기판 제조 방법은 전술한 실시예에 한정되지 않고 본 발명의 기술적 중심 사상을 벗어나지 않는 범위 내에서 다양하게 변형 실시될 수 있다. 이는 본 발명이 속하는 기술분야에 종사하는 자라면 쉽게 이해할 수 있을 것이다.Meanwhile, the substrate manufacturing method according to the present invention is not limited to the above-described embodiments and may be variously modified within a range not departing from the technical spirit of the present invention. This will be readily understood by those skilled in the art.

예를 들어, 본 발명에 다른 기판 제조 방법은 인쇄회로기판이나 테이프 배선 기판 등 다양한 형태의 기판 제조에 적용될 수 있다. 또한 2층 인쇄회로기판 뿐만 아니라 다층 인쇄회로기판의 제조에 적용도 가능하다.For example, the substrate manufacturing method according to the present invention can be applied to the manufacture of various types of substrates such as a printed circuit board or a tape wiring board. It is also applicable to the manufacture of multilayer printed circuit boards as well as two-layer printed circuit boards.

이상과 같은 본 발명에 따른 기판 제조 방법에 따르면, 솔더레지스트막의 표면적이 증가되기 때문에 접착제 또는 접착 필름 및 에폭시 몰딩 컴파운드 등 포토솔더레지스트막과 접착되는 이종 물질간의 결합력이 증가된다. 따라서, 패키지 크랙이나 박리 및 스웰링 현상의 발생이 방지되어 패키지 신뢰성이 향상된다.According to the substrate manufacturing method according to the present invention as described above, since the surface area of the solder resist film is increased, the bonding force between the heterogeneous material that is bonded to the photosolder resist film such as an adhesive or an adhesive film and an epoxy molding compound is increased. Therefore, the occurrence of package cracks, peeling and swelling can be prevented to improve package reliability.

또한 금속 박막 구조체를 열 압착하여 감광성을 갖는 포토 솔더레지스트막을 형성하고 금속층 전체를 제거함으로써 별도의 포토레지스트 도포 공정이 불필요하게 된다. 따라서 공정이 복잡하지 않게 되어 양산성이 좋다. 그리고 포토 솔더레지스트막의 완곡이 발생되지 않아 패키지 신뢰성이 더욱 향상된다.In addition, the metal thin film structure is thermally compressed to form a photo solder resist film having photosensitivity, and the entire metal layer is removed, thereby eliminating a separate photoresist coating process. Therefore, the process is not complicated and mass productivity is good. In addition, since the curvature of the photo solder resist film does not occur, package reliability is further improved.

Claims (4)

⒜ 금속층의 일면에 포토 솔더레지스트막이 형성된 금속 박막 구조체를 회로패턴이 형성된 베이스 기판의 적어도 일면에 열 압착하여 포토 솔더레지스트막이 베이스 기판에 접하게 부착하는 단계, ⒝ 금속 박막 구조체에서 금속층 전체를 에칭으로 제거하며 포토 솔더레지스트막의 표면에 거칠기를 형성하는 단계 및 ⒞ 포토 솔더레지스트막을 노광 및 현상하여 외부 접속에 필요한 부분을 개방시키는 단계를 포함하는 것을 특징으로 하는 기판 제조 방법.열 thermally compressing a metal thin film structure having a photo solder resist film formed on one surface of the metal layer to at least one surface of the base substrate on which the circuit pattern is formed so that the photo solder resist film is in contact with the base substrate; And forming a roughness on the surface of the photo solder resist film and (b) exposing and developing the photo solder resist film to open a portion necessary for external connection. 제1 항에 있어서, According to claim 1, 상기 금속 박막 구조체의 금속층은 구리 재질의 금속층인 것을 특징으로 하는 기판 제조 방법.The metal layer of the metal thin film structure is a substrate manufacturing method, characterized in that the metal layer of copper material. 제1 항에 있어서, According to claim 1, 상기 ⒜ 단계는 베이스 기판의 상면과 하면에 금속 박막 구조체를 부착하는 단계인 것을 특징으로 하는 기판 제조 방법.Wherein the step is a step of attaching a metal thin film structure on the upper and lower surfaces of the base substrate. 제1 항에 있어서,According to claim 1, 상기 회로패턴은 상기 와이어 본딩용 본드 핑거(bond finger)와 볼 부착용 볼 패드(ball pad)를 포함하는 것을 특징으로 하는 기판 제조 방법.The circuit pattern is a substrate manufacturing method comprising a bond finger for bonding the wire (bond finger) and a ball pad (ball pad) for attaching the ball.
KR1020050069504A 2005-07-29 2005-07-29 Substrate manufacturing method KR20070014671A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101016588B1 (en) * 2007-10-12 2011-02-22 르네사스 일렉트로닉스 가부시키가이샤 Semiconductor device and method of manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101016588B1 (en) * 2007-10-12 2011-02-22 르네사스 일렉트로닉스 가부시키가이샤 Semiconductor device and method of manufacturing the same

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