KR20070002669A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

Info

Publication number
KR20070002669A
KR20070002669A KR1020050058294A KR20050058294A KR20070002669A KR 20070002669 A KR20070002669 A KR 20070002669A KR 1020050058294 A KR1020050058294 A KR 1020050058294A KR 20050058294 A KR20050058294 A KR 20050058294A KR 20070002669 A KR20070002669 A KR 20070002669A
Authority
KR
South Korea
Prior art keywords
gate
semiconductor device
layer
manufacturing
semiconductor substrate
Prior art date
Application number
KR1020050058294A
Other languages
Korean (ko)
Other versions
KR100682198B1 (en
Inventor
김희상
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020050058294A priority Critical patent/KR100682198B1/en
Publication of KR20070002669A publication Critical patent/KR20070002669A/en
Application granted granted Critical
Publication of KR100682198B1 publication Critical patent/KR100682198B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Ceramic Engineering (AREA)

Abstract

A method for manufacturing a semiconductor device is provided to extend the effective gate length and to prevent punch-through by forming a barrier layer in a substrate. A protrusion part is formed at a gate forming region of a semiconductor substrate(100). A barrier layer(125) is formed at both sidewalls of the protrusion part. A silicon epitaxial layer(130) is grown on the substrate and planarized. A gate is then formed on the substrate. The height of the protrusion part is 300 to 500Š.

Description

반도체 소자의 제조 방법{METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}Method for manufacturing a semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

도 1은 종래 기술에 따른 반도체 소자의 제조 방법을 도시한 단면도.1 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the prior art.

도 2a 내지 도 2h는 본 발명에 따른 반도체 소자의 제조 방법을 도시한 단면도들. 2A to 2H are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

본 발명은 반도체 소자의 제조 방법에 관한 것으로, 게이트 에지부 하부의 반도체 기판 내부에 배리어막을 형성하여 소스/드레인 영역의 도펀트들이 게이트 하단으로 확산되어 유효 게이트 길이가 짧아지는 것을 방지하며, 드레인의 공핍층이 증가하는 것을 막아주어 펀치 쓰루 현상을 방지하며, 배리어막과 게이트 산화막 사이에 실리콘층을 일부 남겨두어 트랜지스터 동작시 채널 형성에 방해가 되지 않도록 하는 기술을 나타낸다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of fabricating a semiconductor device, wherein a barrier film is formed inside a semiconductor substrate under a gate edge to prevent dopants in a source / drain region from diffusing to a lower end of a gate, thereby shortening an effective gate length, This technology prevents an increase in the pip layer to prevent punch through, and leaves a portion of the silicon layer between the barrier layer and the gate oxide layer so as not to interfere with channel formation during transistor operation.

도 1은 종래 기술에 따른 반도체 소자의 제조 방법을 도시한 단면도이다. 1 is a cross-sectional view showing a method of manufacturing a semiconductor device according to the prior art.

도 1을 참조하면, 소자 분리막(20)이 구비된 반도체 기판(10) 상부에 게이트 산화막(30)을 형성하고, 게이트 산화막(30) 상부에 폴리실리콘층(40), 텅스텐 실리사이드층(50) 및 게이트 하드마스크층(60)의 적층 구조를 형성한다. 다음에, 상기 적층 구조를 식각하여 게이트를 형성한다. Referring to FIG. 1, a gate oxide layer 30 is formed on a semiconductor substrate 10 provided with an isolation layer 20, and a polysilicon layer 40 and a tungsten silicide layer 50 are formed on the gate oxide layer 30. And a stacked structure of the gate hard mask layer 60. Next, the stacked structure is etched to form a gate.

상술한 종래 기술에 따른 반도체 소자의 제조 방법에서, 게이트 길이가 짧아지면서 펀치쓰루(Punch through) 및 짧은 채널 효과(Short Channel Effect)가 발생하여 리프레쉬 특성을 열화시키는 문제점이 있다. In the above-described method of manufacturing a semiconductor device according to the related art, as the gate length becomes shorter, a punch through and a short channel effect occur to deteriorate the refresh characteristics.

상기 문제점을 해결하기 위하여, 게이트 에지부 하부의 반도체 기판 내부에 배리어막을 형성하여 소스/드레인 영역의 도펀트들이 게이트 하단으로 확산되어 유효 게이트 길이가 짧아지는 것을 방지하며, 드레인의 공핍층이 증가하는 것을 막아주어 펀치 쓰루 현상을 방지하며, 배리어막과 게이트 산화막 사이에 실리콘층을 일부 남겨두어 트랜지스터 동작시 채널 형성에 방해가 되지 않도록 하는 반도체 소자의 제조 방법을 제공하는 것을 목적으로 한다.In order to solve the above problem, a barrier layer is formed inside the semiconductor substrate under the gate edge to prevent the dopants in the source / drain regions from diffusing to the bottom of the gate to shorten the effective gate length, and to increase the drain depletion layer. An object of the present invention is to provide a method of manufacturing a semiconductor device which prevents punch through and prevents a punch-through phenomenon, and leaves a portion of a silicon layer between the barrier film and the gate oxide film so as not to interfere with channel formation during transistor operation.

본 발명에 따른 반도체 소자의 제조 방법은 Method for manufacturing a semiconductor device according to the present invention

반도체 기판 상부의 게이트 예정 영역에 돌출부를 형성하는 단계와,Forming a protrusion in the gate predetermined region on the semiconductor substrate;

상기 돌출부 측벽에 배리어막을 형성하는 단계와,Forming a barrier film on the sidewalls of the protrusions;

상기 반도체 기판에 실리콘 에피층을 성장시킨 후 평탄화 식각 공정을 수행하는 단계와,Growing a silicon epitaxial layer on the semiconductor substrate and performing a planarization etching process;

상기 반도체 기판 상부에 게이트를 형성하는 단계Forming a gate over the semiconductor substrate

를 포함하는 것을 특징으로 한다. Characterized in that it comprises a.

이하에서는 본 발명의 실시예를 첨부한 도면을 참조하여 상세히 설명하기로 한다. Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

도 2a 내지 도 2h는 본 발명에 따른 반도체 소자의 제조 방법을 도시한 단면도들이다. 2A to 2H are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

도 2a를 참조하면, 반도체 기판(100) 상부에 게이트 예정 영역을 정의하는 제 1 감광막 패턴(110)을 형성한다.Referring to FIG. 2A, a first photoresist layer pattern 110 defining a gate predetermined region is formed on the semiconductor substrate 100.

여기서, 제 1 감광막 패턴(110)은 상기 게이트 예정 영역보다 좁은 폭으로 형성되는 것이 바람직하다. Here, the first photoresist layer pattern 110 may be formed to have a smaller width than the gate predetermined area.

도 2b를 참조하면, 제 1 감광막 패턴(110)을 마스크로 반도체 기판(100)을 소정 깊이 식각하여 상기 게이트 예정 영역 상부에 돌출부를 형성한다.Referring to FIG. 2B, the semiconductor substrate 100 is etched by a predetermined depth using the first photoresist pattern 110 as a mask to form a protrusion on the gate predetermined region.

상기 돌출부는 300 내지 500Å의 높이로 형성되는 것이 바람직하다. The protrusion is preferably formed to a height of 300 to 500Å.

도 2c를 참조하면, 상기 돌출부를 포함한 반도체 기판(100) 전면에 절연막(120)을 형성한다. Referring to FIG. 2C, an insulating film 120 is formed on the entire surface of the semiconductor substrate 100 including the protrusion.

여기서, 절연막(120)은 산화계열의 절연물질 또는 질화막으로 형성하는 것이 바람직하다. Here, the insulating film 120 is preferably formed of an oxide-based insulating material or a nitride film.

도 2d를 참조하면, 전면 식각 공정을 수행하여 상기 돌출부 측벽에만 절연막(120)을 남겨서 배리어막(125)을 형성한다. Referring to FIG. 2D, the barrier layer 125 is formed by leaving the insulating layer 120 only on the sidewalls of the protrusions by performing an entire surface etching process.

도 2e를 참조하면, 상기 노출된 반도체 기판(100) 상부에 실리콘 에피층(130)을 성장시킨다.Referring to FIG. 2E, a silicon epitaxial layer 130 is grown on the exposed semiconductor substrate 100.

여기서, 실리콘 에피층(130)은 배리어막(125) 상측으로부터 5 내지 15nm의 두께로 형성하는 것이 바람직하다. Here, the silicon epi layer 130 is preferably formed to have a thickness of 5 to 15 nm from the top of the barrier film 125.

이때, 배리어막(125) 상부에 형성된 실리콘층(130)은 MOS 트랜지스터 동작시 채널 영역이 된다.In this case, the silicon layer 130 formed on the barrier layer 125 becomes a channel region during the operation of the MOS transistor.

도 2f를 참조하면, 평탄화 식각 공정을 수행한 후 상기 반도체 기판(100) 상부에 게이트 산화막(140)을 형성한다. Referring to FIG. 2F, after the planarization etching process is performed, a gate oxide layer 140 is formed on the semiconductor substrate 100.

도 2g를 참조하면, 반도체 기판(100) 상부에 게이트 패턴을 형성한다. Referring to FIG. 2G, a gate pattern is formed on the semiconductor substrate 100.

여기서, 상기 게이트 패턴은 폴리실리콘층(150), 게이트 금속층(160) 및 게이트 하드마스크층(170)의 적층 구조로 형성되며, 게이트 금속층(160)은 텅스텐 실리사이드층으로 형성되며, 게이트 하드마스크층(170)은 질화막으로 형성되는 것이 바람직하다. Here, the gate pattern is formed of a laminated structure of the polysilicon layer 150, the gate metal layer 160 and the gate hard mask layer 170, the gate metal layer 160 is formed of a tungsten silicide layer, the gate hard mask layer It is preferable that 170 is formed from a nitride film.

도 2h를 참조하면, 상기 게이트 패턴 측벽에 스페이서(180)을 형성하여 게이트를 형성하고 상기 게이트를 마스크로 이온 주입 공정을 수행하여 소스/드레인 영역(190)을 형성한다. Referring to FIG. 2H, a spacer 180 may be formed on sidewalls of the gate pattern to form a gate, and an ion implantation process may be performed using the gate as a mask to form a source / drain region 190.

여기서, 배리어막(125)은 소스/드레인 영역의 도펀트들이 게이트 하단으로 확산되어 유효 게이트 길이가 짧아지는 것을 방지하기 위해 게이트 에지부 하부에 형성하는 것이 바람직하다. Here, the barrier layer 125 may be formed under the gate edge to prevent the dopants in the source / drain regions from diffusing to the lower end of the gate to shorten the effective gate length.

본 발명에 따른 반도체 소자의 제조 방법은, 게이트 에지부 하부의 반도체 기판 내부에 배리어막을 형성하여 소스/드레인 영역의 도펀트들이 게이트 하단으로 확산되어 유효 게이트 길이가 짧아지는 것을 방지하며, 드레인의 공핍층이 증가하는 것을 막아주어 펀치 쓰루 현상을 방지하며, 배리어막과 게이트 산화막 사이에 실리콘층을 일부 남겨두어 트랜지스터 동작시 채널 형성에 방해가 되지 않도록 하는 효과가 있다. In the method of manufacturing a semiconductor device according to the present invention, a barrier layer is formed in a semiconductor substrate under a gate edge to prevent dopants in a source / drain region from diffusing to the bottom of the gate to shorten an effective gate length, and a drain depletion layer. By preventing this increase, a punch through phenomenon is prevented, and a part of the silicon layer is left between the barrier film and the gate oxide film, thereby preventing the channel formation during the transistor operation.

아울러 본 발명의 바람직한 실시예는 예시의 목적을 위한 것으로, 당업자라면 첨부된 특허청구범위의 기술적 사상과 범위를 통해 다양한 수정, 변경, 대체 및 부가가 가능할 것이며, 이러한 수정 변경 등은 이하의 특허청구범위에 속하는 것으로 보아야 할 것이다.In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (6)

반도체 기판 상부의 게이트 예정 영역에 돌출부를 형성하는 단계;Forming a protrusion in a gate predetermined area on the semiconductor substrate; 상기 돌출부 측벽에 배리어막을 형성하는 단계;Forming a barrier layer on the sidewalls of the protrusions; 상기 반도체 기판에 실리콘 에피층을 성장시킨 후 평탄화 식각 공정을 수행하는 단계; 및Growing a silicon epitaxial layer on the semiconductor substrate and performing a planarization etching process; And 상기 반도체 기판 상부에 게이트를 형성하는 단계; Forming a gate over the semiconductor substrate; 를 포함하는 것을 특징으로 하는 반도체 소자의 제조 방법.Method of manufacturing a semiconductor device comprising a. 제 1 항에 있어서, The method of claim 1, 상기 돌출부는 반도체 기판 상부에 게이트 예정 영역을 정의하는 감광막 패턴을 형성한 후 상기 감광막 패턴을 마스크로 상기 게이트 예정 영역 양측의 상기 반도체 기판을 식각하여 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법.And forming a photoresist pattern defining a gate predetermined region on the protrusion, and then etching the semiconductor substrates on both sides of the gate predetermined region using the photoresist pattern as a mask. 제 1 항에 있어서, The method of claim 1, 상기 돌출부는 300 내지 500Å의 높이로 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법. The projecting portion is a manufacturing method of a semiconductor device, characterized in that formed in a height of 300 to 500Å. 제 1 항에 있어서, The method of claim 1, 상기 반도체 기판 상부에 배리어막을 제거하는 공정은 건식 식각 공정으로 진행되는 것을 특징으로 하는 반도체 소자의 제조 방법. The process of removing the barrier layer on the semiconductor substrate is a method of manufacturing a semiconductor device, characterized in that the dry etching process. 제 1 항에 있어서, The method of claim 1, 상기 배리어막은 산화계열의 절연물질 또는 질화막으로 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법. The barrier film is a semiconductor device manufacturing method characterized in that formed of an oxide-based insulating material or a nitride film. 제 1 항에 있어서, The method of claim 1, 상기 실리콘 에피층은 상기 배리어막 상측으로부터 5 내지 15nm의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법. The silicon epitaxial layer is a semiconductor device manufacturing method, characterized in that formed from a thickness of 5 to 15nm from the barrier film.
KR1020050058294A 2005-06-30 2005-06-30 Method for manufacturing semiconductor device KR100682198B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020050058294A KR100682198B1 (en) 2005-06-30 2005-06-30 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020050058294A KR100682198B1 (en) 2005-06-30 2005-06-30 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
KR20070002669A true KR20070002669A (en) 2007-01-05
KR100682198B1 KR100682198B1 (en) 2007-02-12

Family

ID=37869631

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020050058294A KR100682198B1 (en) 2005-06-30 2005-06-30 Method for manufacturing semiconductor device

Country Status (1)

Country Link
KR (1) KR100682198B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101097469B1 (en) * 2009-07-31 2011-12-23 주식회사 하이닉스반도체 Semiconductor device and method for fabricating the same

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06177377A (en) * 1992-06-05 1994-06-24 Texas Instr Inc <Ti> Insulated-gate field-effect transistor
KR0137811B1 (en) * 1994-12-30 1998-06-01 김주용 Fabrication method of semiconductor device

Also Published As

Publication number Publication date
KR100682198B1 (en) 2007-02-12

Similar Documents

Publication Publication Date Title
US8536653B2 (en) Metal oxide semiconductor transistor
US8106467B2 (en) Semiconductor device having carrier mobility raised by generating strain in channel region
US10847650B2 (en) Semiconductor structure and associated fabricating method
US20110163375A1 (en) High-Voltage MOS Devices Having Gates Extending into Recesses of Substrates
US7875938B2 (en) LDMOS device with multiple gate insulating members
US8067799B2 (en) Semiconductor device having recess channel structure and method for manufacturing the same
US20070152245A1 (en) Semiconductor device and method for manufacturing the same
KR100871976B1 (en) Semiconductor device and method for fabricating the same
US8198161B2 (en) Vertical transistor and method for forming the same
JP2004146825A (en) Mos transistor and its manufacturing method
KR100682198B1 (en) Method for manufacturing semiconductor device
KR100613355B1 (en) MOSFET and method of fabricating the MOSFET
KR100282453B1 (en) Method for manufacturing semiconductor device the same
KR100620642B1 (en) Method for manufacturing semiconductor device
KR100625394B1 (en) Method for manufacturing semiconductor device
KR20080006268A (en) Method of manufcaturing a tunneling field effect transistor
KR100745924B1 (en) Method for manufacturing semiconductor device
KR100694391B1 (en) Method for manufacturing semiconductor device
KR20080029266A (en) Method of manufacturing semiconductor device
KR100670749B1 (en) Method for manufacturing saddle type transistor
KR101194742B1 (en) Method for forming semiconductor device
KR20080084259A (en) Method for manufacturing of semiconductor device
KR100756844B1 (en) Semiconductor device and method for manufacturing thereof
KR20040046074A (en) Method for forming Field effect transistors of semiconductor device
KR20100079006A (en) Semiconductor device, and method of fabricating thereof

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20110126

Year of fee payment: 5

LAPS Lapse due to unpaid annual fee