KR20060030690A - Non-volatile memory device and method of forming the same - Google Patents
Non-volatile memory device and method of forming the same Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 31
- 239000010410 layer Substances 0.000 claims abstract description 31
- 239000011229 interlayer Substances 0.000 claims abstract description 29
- 239000004065 semiconductor Substances 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 9
- 239000010703 silicon Substances 0.000 claims abstract description 9
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 5
- 239000007789 gas Substances 0.000 claims description 5
- 238000010438 heat treatment Methods 0.000 claims description 5
- 229910052760 oxygen Inorganic materials 0.000 claims description 5
- 239000001301 oxygen Substances 0.000 claims description 5
- 229910021529 ammonia Inorganic materials 0.000 claims description 3
- 238000005121 nitriding Methods 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000009832 plasma treatment Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
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Abstract
비휘발성 메모리 소자 및 그 형성 방법을 제공한다. 이 소자는 반도체 기판 상에 차례로 적층된 터널 산화막 및 부유 게이트막; 상기 부유 게이트막의 상부면과 측벽 및 상기 반도체 기판의 일부를 덮는 게이트 층간절연막; 및 상기 게이트 층간절연막 상의 제어 게이트막을 구비하되, 상기 게이트 층간절연막은 실리콘산화질화막(SixOyNz)으로 이루어지는 것을 특징으로 한다. A nonvolatile memory device and a method of forming the same are provided. The device comprises a tunnel oxide film and a floating gate film sequentially stacked on a semiconductor substrate; A gate interlayer insulating film covering an upper surface and a sidewall of the floating gate film and a portion of the semiconductor substrate; And a control gate layer on the gate interlayer insulating layer, wherein the gate interlayer insulating layer is formed of a silicon oxynitride layer (Si x O y N z ).
게이트 층간절연막, 실리콘산화질화막Gate interlayer insulating film, silicon oxynitride film
Description
도 1은 본 발명의 바람직한 실시예에 따른 비휘발성 메모리 소자의 단면도를 나타낸다. 1 is a cross-sectional view of a nonvolatile memory device according to a preferred embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
1: 반도체 기판 3: 터널 산화막1: semiconductor substrate 3: tunnel oxide film
5: 부유 게이트막 7: 게이트 층간절연막5: floating gate film 7: gate interlayer insulating film
9: 제어 게이트막9: control gate film
본 발명은 반도체 소자 및 그 형성 방법에 관한 것으로, 더욱 상세하게는 비휘발성 메모리 소자 및 그 형성 방법에 관한 것이다. The present invention relates to a semiconductor device and a method of forming the same, and more particularly, to a nonvolatile memory device and a method of forming the same.
비휘발성 메모리 소자는 일반적으로 차례로 적층된 터널 산화막과 부유 게이트, 상기 부유게이트의 상면과 측벽을 덮는 게이트 층간절연막 및 상기 게이트 층간절연막 상부의 제어게이트막으로 이루어진다. 상기 게이트 층간절연막으로 높은 유전율 및 소자의 신뢰도를 위해 산화막-질화막-산화막의 삼중막을 사용한다. 그러 나 종래와 같이 삼중막을 사용할 경우 수직적 높이를 190Å이하로 낮출수가 없어, 현재의 추세인 반도체 소자의 고집적화에 부적합하다. 또한 산화막을 증착한 이후에 산화막질을 견고하게 하여 누설전류등을 방지하기 위한 방편으로 매번 어닐링 공정을 진행한다. 따라서 공정이 복잡하고 많은 시간이 소요된다. A nonvolatile memory device generally includes a tunnel oxide film, a floating gate, a gate interlayer insulating film covering the top and sidewalls of the floating gate, and a control gate film on the gate interlayer insulating film, which are sequentially stacked. A triple layer of an oxide film-nitride film-oxide film is used as the gate interlayer insulating film for high dielectric constant and device reliability. However, in the case of using the triple layer as in the prior art, the vertical height cannot be lowered to 190 kW or less, which is not suitable for the high integration of current semiconductor devices. In addition, after the oxide film is deposited, the annealing process is performed every time as a means to harden the oxide film and prevent leakage current. Therefore, the process is complicated and time consuming.
따라서, 상기 문제점을 해결하기 위하여, 본 발명의 기술적 과제는 수직적 높이를 낮출수 있고, 얇은 두께로도 누설전류등을 방지할 수 있는 게이트 층간절연막을 갖는 비휘발성 메모리 소자 및 그 형성 방법을 제공하는데 있다. Accordingly, in order to solve the above problems, the technical problem of the present invention is to provide a nonvolatile memory device having a gate interlayer insulating film capable of lowering the vertical height and preventing leakage current, even at a thin thickness, and a method of forming the same. have.
상기 기술적 과제를 달성하기 위한 본 발명에 따른 비휘발성 메모리 소자는 반도체 기판 상에 차례로 적층된 터널 산화막 및 부유 게이트막; 상기 부유 게이트막의 상부면과 측벽 및 상기 반도체 기판의 일부를 덮는 게이트 층간절연막; 및 상기 게이트 층간절연막 상의 제어 게이트막을 구비하되, 상기 게이트 층간절연막은 실리콘산화질화막(SixOyNz)으로 이루어지는 것을 특징으로 한다. According to an aspect of the present invention, there is provided a nonvolatile memory device including: a tunnel oxide film and a floating gate film sequentially stacked on a semiconductor substrate; A gate interlayer insulating film covering an upper surface and a sidewall of the floating gate film and a portion of the semiconductor substrate; And a control gate layer on the gate interlayer insulating layer, wherein the gate interlayer insulating layer is formed of a silicon oxynitride layer (Si x O y N z ).
상기 또 다른 기술적 과제를 달성하기 위한 비휘발성 메모리 소자의 형성 방법은 다음과 같다. 먼저, 반도체 기판 상에 차례로 적층된 터널 산화막과 부유 게이트막을 형성한다. 상기 부유 게이트막이 형성된 상기 반도체 기판의 전면 상에 게이트 층간절연막을 형성한다. 그리고 상기 게이트 층간절연막 상에 제어게이트막을 형성한다. 상기 방법에 있어서, 상기 게이트 층간절연막은 실리콘산화질화막 (SixOyNz)으로 형성된다. A method of forming a nonvolatile memory device for achieving the another technical problem is as follows. First, a tunnel oxide film and a floating gate film that are sequentially stacked on a semiconductor substrate are formed. A gate interlayer insulating film is formed on the entire surface of the semiconductor substrate on which the floating gate film is formed. A control gate film is formed on the gate interlayer insulating film. In the method, the gate interlayer insulating film is formed of a silicon oxynitride film (Si x O y N z ).
상기 게이트 층간절연막은, 바람직하게는 질화 분위기에서 상기 부유 게이트막이 형성된 상기 반도체 기판에 대해 급속열처리 공정을 진행한 후, 산소 플라즈마 처리를 진행하여 형성된다. 바람직하게는, 상기 질화 분위기는 암모니아(NH3)가스를 10~1000sccm의 유량으로 공급하여 형성되며, 상기 급속 열처리 공정은 600~900℃의 온도와 0.5~3atm의 압력에서 진행된다. 바람직하게는, 상기 산소 플라즈마 처리는 30~500W의 RF 파워를 공급하여 400~500℃의 온도와 0.1~2torr의 압력에서 N2O 가스를 30~200sccm의 유량으로 공급하여 진행된다. The gate interlayer insulating film is preferably formed by performing an oxygen plasma treatment after performing a rapid heat treatment process on the semiconductor substrate on which the floating gate film is formed in a nitride atmosphere. Preferably, the nitriding atmosphere is formed by supplying ammonia (NH 3 ) gas at a flow rate of 10 ~ 1000sccm, the rapid heat treatment process is carried out at a temperature of 600 ~ 900 ℃ and a pressure of 0.5 ~ 3atm. Preferably, the oxygen plasma treatment is supplied by supplying an RF power of 30 ~ 500W to supply a N 2 O gas at a flow rate of 30 ~ 200sccm at a temperature of 400 ~ 500 ℃ and a pressure of 0.1 ~ 2torr.
상기 방법에 있어서, 게이트 층간절연막을 유전율이 높은 실리콘산화질화막의 단일막으로 형성하므로 커플링비를 높일 수 있고 누설전류를 방지할 수 있으며, 두께를 얇게 형성할 수 있어 수직적 높이를 낮출수 있다. 또한 산화막-질화막-산화막의 삼중막을 형성하는 종래기술에 비해 형성 과정이 간단하며 공정 시간을 단축시킬 수 있다. In the above method, since the gate interlayer insulating film is formed of a single layer of silicon oxynitride film having a high dielectric constant, the coupling ratio can be increased, the leakage current can be prevented, and the thickness can be formed thin so that the vertical height can be reduced. In addition, the formation process is simpler than the prior art of forming the triple layer of the oxide film-nitride film-oxide film and can shorten the process time.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다. 그러나, 본 발명은 여기서 설명되어지는 실시예에 한정되지 않고 다른 형태로 구체화될 수도 있다. 오히려, 여기서 소개되는 실시예는 개시된 내용이 철저하고 완전해질 수 있도록 그리고 당업자에게 본 발명의 사상이 충분히 전달될 수 있도록 하기 위해 제공되어지는 것이다. 층이 다른 층 또는 기판 상에 있다고 언급되어지는 경우에 그것은 다른 층 또는 기판 상에 직접 형성될 수 있거나 또는 그들 사이에 제 3의 층이 개재될 수도 있다. 도면에 있어서, 층 및 영역들의 두께는 명확성을 기하기 위하여 과장되어진 것이다. 명세서 전체에 걸쳐서 동일한 참조번호로 표시된 부분들은 동일한 구성요소들을 나타낸다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the spirit of the present invention to those skilled in the art will fully convey. If it is mentioned that the layer is on another layer or substrate it may be formed directly on the other layer or substrate or a third layer may be interposed therebetween. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Portions denoted by like reference numerals denote like elements throughout the specification.
도 1은 본 발명의 바람직한 실시예에 따른 비휘발성 메모리 소자의 단면도를 나타낸다. 1 is a cross-sectional view of a nonvolatile memory device according to a preferred embodiment of the present invention.
도 1을 참조하면, 반도체 기판(1) 상에 터널 산화막(3)을 형성한다. 상기 터널 산화막(3)은 예를 들면 열산화막으로 형성될 수 있다. 상기 터널산화막(3) 상에 부유게이트막(5)을 형성한다. 상기 부유 게이트막(5)은 예를 들면 저압화학기상증착(Low pressure chemical vapor deposition) 방법에 의해 폴리실리콘막으로 형성될 수 있다. 상기 부유 게이트막(5)과 상기 터널 산화막(3)을 차례로 패터닝하여 상기 반도체 기판(1)을 노출시킨다. Referring to FIG. 1, a
계속해서, 상기 반도체 기판(1)의 전면 상에 게이트 층간절연막(7)을 형성한다. 상기 게이트 층간절연막(7)은 실리콘산화질화막(SixOyNz)으로 형성된다. 구체적으로, 먼저 상기 반도체 기판(1)의 전면에 대해 암모니아를 10~1000sccm의 유량으로 공급하여 형성된 질화분위기에서 상압 및 600~700℃의 온도에서 급속 열처리 공정을 진행하여 상기 반도체 기판(1)의 전면에 실리콘질화막(Si3N4)을 형성한다. 그리고, 30~500W의 RF 파워를 공급하고 N2O 가스를 30~200sccm의 유량으로 공급하여 플라즈마를 형성하고 400~500℃의 온도와 0.1~2torr의 압력에서 상기 실리콘질화막을 산화하여 실리콘산화질화막(SixOyNz)을 형성한다.
Subsequently, a gate
후속으로 상기 게이트 층간절연막(7) 상에 예를 들면 저압화학기상증착방법으로 인이 도핑된 폴리실리콘으로 제어게이트막(9)을 형성한다. 상기 제어게이트막(9), 상기 게이트 층간절연막(7), 상기 부유게이트막(5) 및 상기 터널게이트막(3)을 차례로 패터닝하여 비휘발성 메모리 게이트 패턴을 형성한다.Subsequently, the
상기 방법에 있어서, 게이트 층간절연막을 유전율이 높은 실리콘산화질화막의 단일막으로 형성하므로 커플링비를 높일 수 있고 누설전류를 방지할 수 있으며, 두께를 얇게 형성할 수 있어 수직적 높이를 낮출수 있다. 또한 산화막-질화막-산화막의 삼중막을 형성하는 종래기술에 비해 형성 과정이 간단하며 공정 시간을 단축시킬 수 있다. In the above method, since the gate interlayer insulating film is formed of a single layer of silicon oxynitride film having a high dielectric constant, the coupling ratio can be increased, the leakage current can be prevented, and the thickness can be formed thin so that the vertical height can be reduced. In addition, the formation process is simpler than the prior art of forming the triple layer of the oxide film-nitride film-oxide film and can shorten the process time.
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