KR20050106221A - Guard-ring of semiconductor devices and method for fabricating the same - Google Patents
Guard-ring of semiconductor devices and method for fabricating the same Download PDFInfo
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- KR20050106221A KR20050106221A KR1020040031388A KR20040031388A KR20050106221A KR 20050106221 A KR20050106221 A KR 20050106221A KR 1020040031388 A KR1020040031388 A KR 1020040031388A KR 20040031388 A KR20040031388 A KR 20040031388A KR 20050106221 A KR20050106221 A KR 20050106221A
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- guard ring
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 238000000034 method Methods 0.000 title claims abstract description 23
- 239000010410 layer Substances 0.000 claims description 18
- 230000002093 peripheral effect Effects 0.000 claims description 13
- 239000011229 interlayer Substances 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 11
- 239000004020 conductor Substances 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- 230000007547 defect Effects 0.000 abstract description 4
- 239000003990 capacitor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- Microelectronics & Electronic Packaging (AREA)
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- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 소자의 가드링 및 그 형성 방법에 관한 것으로써, 가드링 영역의 하부에 결함이 발생하고 희생산화막이 유실되면서 반도체 소자에 발생되는 손실을 방지하기 위하여, 가드링 영역에도 콘택 플러그를 형성하는 방법을 사용하여 소자의 신뢰성 및 제품의 수율을 향상시킬 수 있다. The present invention relates to a guard ring of a semiconductor device and a method for forming the semiconductor device. In order to prevent a loss occurring in the semiconductor device while a defect occurs in the lower portion of the guard ring region and the sacrificial oxide film is lost, a contact plug is also provided in the guard ring region. Forming methods can be used to improve device reliability and product yield.
Description
본 발명은 반도체 소자의 가드링 및 그 형성 방법에 관한 것으로써, 특히 가드링 영역의 하부에 결함이 발생하고 희생산화막이 유실되면서 반도체 소자에 손실이 발생되는 문제를 해결하기 위하여 가드링용 콘택플러그를 형성하는 반도체 소자의 가드링 및 그 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a guard ring of a semiconductor device and a method of forming the same. In particular, in order to solve a problem in which a defect occurs in a lower portion of a guard ring region and a loss occurs in a semiconductor device due to loss of a sacrificial oxide film, a contact ring for a guard ring is provided. A guard ring of a semiconductor element to be formed and a method of forming the same.
종래의 기술에 따른 반도체 소자의 저장전극 형성 방법에 의하면 셀 영역의 저장전극 밀도가 높아서 캐패시터가 주변회로 영역 쪽으로 넘어지는 현상이 발생하였다. 이를 방지하기 위하여 셀 영역과 주변회로 영역의 경계 영역에 저장전극 가드링을 형성하였다.According to the method of forming a storage electrode of a semiconductor device according to the related art, a phenomenon in which a capacitor falls to a peripheral circuit region occurs due to a high storage electrode density in a cell region. In order to prevent this, the storage electrode guard ring is formed in the boundary region between the cell region and the peripheral circuit region.
도 1a 내지 도 1d는 종래 기술에 따른 반도체 소자의 가드링 형성 방법을 도시한 단면도들이다.1A to 1D are cross-sectional views illustrating a method of forming a guard ring of a semiconductor device according to the prior art.
도 1a를 참조하면, 셀 영역과 주변회로 영역을 구비한 반도체 기판(10) 상부에 층간절연막(20)과 식각정지막(30)을 형성한 후, 식각정지막(30) 및 층간절연막(20)을 식각하여 셀 영역에 저장전극 콘택홀(미도시)을 형성한다. 다음에는 저장전극 콘택홀(미도시)을 도전물질로 매립하여 저장전극 콘택 플러그(40)를 형성한다.Referring to FIG. 1A, after forming the interlayer insulating film 20 and the etch stop film 30 on the semiconductor substrate 10 including the cell region and the peripheral circuit region, the etch stop film 30 and the interlayer insulating film 20 are formed. ) Is formed to form a storage electrode contact hole (not shown) in the cell region. Next, the storage electrode contact plug 40 is filled with a conductive material to form the storage electrode contact plug 40.
도 1b를 참조하면, 반도체 기판(10) 상부에 희생산화막(50)을 형성한 후 패터닝하여 저장전극 영역(60)과 가드링 영역(70)을 형성한다.Referring to FIG. 1B, the sacrificial oxide film 50 is formed on the semiconductor substrate 10 and then patterned to form the storage electrode region 60 and the guard ring region 70.
도 1c를 참조하면, 저장전극 영역(60) 및 가드링 영역(70)에 의해 노출된 식각정지막(30)을 식각한다. 이때, 가드링 영역(70)의 내부 사이즈가 더 넓으므로 식각정지막(30)에 적재현상(Loading Effect)이 일어나고, 식각 비율의 차이에 의해 가드링 영역(70)의 식각정지막(30) 및 층간절연막(20)이 손상을 받게 된다.Referring to FIG. 1C, the etch stop layer 30 exposed by the storage electrode region 60 and the guard ring region 70 is etched. At this time, since the internal size of the guard ring region 70 is wider, a loading effect occurs in the etch stop layer 30, and the etch stop layer 30 of the guard ring region 70 is caused by a difference in the etching rate. And the interlayer insulating film 20 is damaged.
도 1d를 참조하면, 저장전극 영역(60) 및 가드링 영역(70)에 각각 저장전극(75) 및 가드링(80)을 형성한다. 이때, 가드링 영역(70)의 층간절연막(20)이 손실되어 가드링(80)이 제대로 형성되지 못하고 떨어져 층간절연막(20) 및 희생산화막(50)이 노출된다. 또한, 후속 공정인 습식 딥 아웃(Dip Out)시 가드링 영역(70) 하부의 희생산화막(50)이 둥근 형태로 움푹 들어가 유실되는 딤플(Dimple)현상이 발생한다.Referring to FIG. 1D, the storage electrode 75 and the guard ring 80 are formed in the storage electrode region 60 and the guard ring region 70, respectively. At this time, since the interlayer insulating film 20 of the guard ring region 70 is lost, the guard ring 80 cannot be formed properly, and the interlayer insulating film 20 and the sacrificial oxide film 50 are exposed. In addition, a dimple phenomenon occurs in which the sacrificial oxide film 50 in the lower portion of the guard ring region 70 is pitted and lost during the subsequent wet dip out.
도 2는 종래 기술에 따른 반도체 소자의 가드링 형성 방법에 의한 딤플현상의 영향으로 희생산화막이 유실된 상태를 도시한 단면도이다.2 is a cross-sectional view illustrating a state in which a sacrificial oxide film is lost due to a dimple phenomenon by a method of forming a guard ring of a semiconductor device according to the related art.
저장전극 가드링 영역(70) 하부의 희생산화막(50)이 유실된 부분(90)은 후속 공정에서 폴리등 전도성 물질이 채워져 인접한 패턴과 전기적 쇼트등이 발생하여 반도체 소자에 치명적인 손실을 유발한다는 문제가 있다.The portion 90 in which the sacrificial oxide film 50 is missing in the lower portion of the storage electrode guard ring region 70 is filled with a conductive material such as poly in a subsequent process to cause an electrical short and an adjacent pattern to cause a fatal loss to the semiconductor device. There is.
본 발명은 상기와 같은 문제점을 해결하기 위한 것으로, 본 발명의 목적은 반도체 소자의 가드링 형성 방법에 있어서 가드링 영역의 하부에 결함이 발생하고 희생산화막이 유실되는 문제를 방지하기 위하여, 가드링 영역에도 콘택홀 및 플러그를 형성하는 방법을 사용함으로써 반도체 소자에 발생되는 손실을 없애고, 소자의 신뢰성을 향상시킬 수 있는 반도체 소자의 가드링 형성 방법을 제공함에 있다. The present invention is to solve the above problems, an object of the present invention in the method of forming a guard ring of a semiconductor device, in order to prevent a problem that a defect occurs in the lower portion of the guard ring region and the sacrificial oxide film is lost, the guard ring By using a method of forming contact holes and plugs in a region, the present invention provides a method of forming a guard ring of a semiconductor device capable of eliminating losses generated in the semiconductor device and improving the reliability of the device.
본 발명은 상기와 같은 목적을 달성하기 위한 것으로서, 셀 영역과 주변회로 영역을 구비한 반도체 기판 상부에 층간절연막과 식각정지막을 형성하는 단계와, 상기 식각정지막 및 층간절연막을 식각하여 상기 셀 영역에는 저장전극 콘택홀을 형성하고 상기 셀 영역과 주변회로 영역의 경계영역의 가드링용 콘택홀을 형성하는 단계와, 상기 저장전극 콘택홀과 가드링용 콘택홀을 도전물질로 매립하여 저장전극 콘택 플러그 및 가드링용 콘택 플러그를 형성하는 단계와, 상기 반도체 기판 상부에 희생산화막을 형성하는 단계와, 상기 희생산화막을 패터닝하여 저장전극 영역 및 가드링 영역을 형성하는 단계와, 상기 저장전극 영역 및 가드링 영역에 의해 노출된 식각정지막을 제거하는 단계 및 상기 저장전극 영역과 가드링 영역에 저장전극과 가드링을 각각 형성하는 단계를 포함하는 것을 특징으로 한다.According to an aspect of the present invention, an interlayer insulating layer and an etch stop layer are formed on a semiconductor substrate including a cell region and a peripheral circuit region, and the etch stop layer and the interlayer insulating layer are etched to form the cell region. Forming a storage electrode contact hole and forming a guard ring contact hole in a boundary area between the cell region and the peripheral circuit region; and filling the storage electrode contact hole and the guard ring contact hole with a conductive material to form a storage electrode contact plug; Forming a contact ring for a guard ring, forming a sacrificial oxide film on the semiconductor substrate, patterning the sacrificial oxide film to form a storage electrode region and a guard ring region, and forming the storage electrode region and the guard ring region. Removing the etch stop layer exposed by the storage electrode and the guard ring in the storage electrode region and the guard ring region. Characterized in that it comprises the step of forming each.
이하, 첨부된 도면을 참조하여 본 발명에 따른 반도체 소자의 저장전극 형성 방법에 관하여 상세히 설명하면 다음과 같다.Hereinafter, a method of forming a storage electrode of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 3a 내지 도 3e는 본 발명에 따른 반도체 소자의 저장전극 형성 방법을 도시한 단면도들이다.3A to 3E are cross-sectional views illustrating a method of forming a storage electrode of a semiconductor device according to the present invention.
도 3a를 참조하면, 셀 영역과 주변회로 영역을 구비한 반도체 기판(100) 상부에 층간절연막(120)과 식각정지막(130)을 형성한다. 다음에는, 식각정지막(130) 및 층간절연막(120)을 패터닝하여 셀 영역에 저장전극 콘택홀(110)과 셀 영역과 주변회로 영역의 경계 영역에 저장전극 가드링용 콘택홀(115)을 형성한다. 이때, 상기 저장전극 콘택홀(110) 및 가드링용 콘택홀(115)은 저장전극 콘택 마스크와 가드링 콘택마스크를 이용하여 각각 형성하거나 상기 콘택홀이 디자인된 하나의 마스크를 이용하여 동시에 형성할 수도 있다.Referring to FIG. 3A, an interlayer insulating layer 120 and an etch stop layer 130 are formed on the semiconductor substrate 100 including the cell region and the peripheral circuit region. Next, the etch stop layer 130 and the interlayer insulating layer 120 are patterned to form the storage electrode contact hole 110 in the cell region and the storage electrode guard ring contact hole 115 in the boundary region of the cell region and the peripheral circuit region. do. In this case, the storage electrode contact hole 110 and the guard ring contact hole 115 may be formed using a storage electrode contact mask and a guard ring contact mask, or may be simultaneously formed using one mask for which the contact hole is designed. have.
도 3b를 참조하면, 저장전극 콘택홀(110)과 가드링용 콘택홀(115)을 도전물질로 매립하여 저장전극 콘택 플러그(140) 및 가드링용 콘택 플러그(145)를 형성한다. 이때, 저장전극 콘택 플러그(140) 및 가드링용 콘택 플러그(145)는 반도체 기판(100) 전체 표면에 도전물질(미도시)을 형성한 후 각 콘택 플러그가 절연되도록 CMP공정으로 평탄화시켜 형성하며, 가드링용 콘택 플러그(145)는 셀 영역 및 주변회로 영역의 경계 영역에 연속적 또는 불연속적인 패턴으로 형성될 수 있다.Referring to FIG. 3B, the storage electrode contact hole 110 and the guard ring contact hole 115 are filled with a conductive material to form the storage electrode contact plug 140 and the guard ring contact plug 145. In this case, the storage electrode contact plug 140 and the guard ring contact plug 145 are formed by forming a conductive material (not shown) on the entire surface of the semiconductor substrate 100 and then planarizing them by a CMP process to insulate each contact plug. The guard ring contact plug 145 may be formed in a continuous or discontinuous pattern in the boundary region of the cell region and the peripheral circuit region.
도 3c를 참조하면, 반도체 기판(100) 상부에 희생산화막(150)을 저장전극 마스크와 가드링 마스크 또는 저장전극과 가드링이 디자인된 하나의 마스크를 이용하한 사진식각공정을 수행하는 패터닝을 하여, 저장전극 영역(160)과 가드링 영역(170)을 형성한다.Referring to FIG. 3C, the sacrificial oxide layer 150 is patterned on the semiconductor substrate 100 to perform a photolithography process using a storage electrode mask and a guard ring mask or a mask in which the storage electrode and the guard ring are designed. The storage electrode region 160 and the guard ring region 170 are formed.
도 3d를 참조하면, 저장전극 영역(160) 및 가드링 영역(170)에 의해 노출된 식각정지막(130)을 제거한다.Referring to FIG. 3D, the etch stop layer 130 exposed by the storage electrode region 160 and the guard ring region 170 is removed.
도 3e를 참조하면, 저장전극 영역(160) 및 가드링 영역(170)에 각각 저장전극(175) 및 가드링(180)을 형성한다.Referring to FIG. 3E, the storage electrode 175 and the guard ring 180 are formed in the storage electrode region 160 and the guard ring region 170, respectively.
도 4는 본 발명에 따른 반도체 소자의 저장전극 콘택 플러그 및 가드링용 콘택 플러그에 대한 레이아웃도 이다. 4 is a layout of the storage electrode contact plug and the guard ring contact plug of the semiconductor device according to the present invention.
도 4를 참조하면, 셀 영역과 주변회로의 경계 영역에 구비된 반도체 소자의가드링(미도시)은 그 하부에 가드링용 콘택 플러그(145)를 더 구비한다. 또한 가드링용 콘택 플러그(145)는 연속 또는 불연속적인 패턴으로 형성할 수 있는 것을 도시한 반도체 소자의 가드링 이다.Referring to FIG. 4, a guard ring (not shown) of a semiconductor device provided in a boundary region between a cell region and a peripheral circuit may further include a guard ring contact plug 145 below. In addition, the guard ring contact plug 145 is a guard ring of a semiconductor device, which can be formed in a continuous or discontinuous pattern.
이상에서 설명한 바와 같이, 본 발명에 따른 반도체 소자의 가드링 영역의 하부에 결함이 발생하고 희생산화막이 유실되면서 반도체 소자에 손실이 발생되는 문제를 해결하기 위하여 가드링 그 하부에 가드링용 콘택플러그를 더 구비함으로써, 셀 영역의 저장전극과 가드링간의 조건을 동일하게 유지시킬 수 있다. 따라서, 희생산화막이 유실된 영역에 폴리등의 전도성 물질이 채워져 전기적 쇼트등 반도체 소자에 미치는 치명적인 손실을 방지할 수 있고, 수율향상에 기여할 뿐만 아니라 반도체 소자의 신뢰성을 높이는 효과가 있다.As described above, in order to solve a problem in which a defect occurs in the lower portion of the guard ring region of the semiconductor device and a loss occurs in the semiconductor device while the sacrificial oxide film is lost, a contact ring for the guard ring is disposed below the guard ring. By further providing, the conditions between the storage electrode and the guard ring in the cell region can be maintained the same. Therefore, a conductive material such as poly is filled in a region where the sacrificial oxide film is lost, thereby preventing a fatal loss on the semiconductor device such as an electrical short, and contributing to the improvement of yield, as well as improving the reliability of the semiconductor device.
도 1a 내지 도 1d는 종래 기술에 따른 반도체 소자의 가드링 형성 방법을 도시한 단면도들.1A to 1D are cross-sectional views illustrating a method of forming a guard ring of a semiconductor device according to the prior art.
도 2는 종래 기술에 따른 반도체 소자의 가드링 형성 방법에 의한 딤플현상의 영향으로 희생산화막이 유실된 상태를 도시한 단면도.2 is a cross-sectional view showing a state where a sacrificial oxide film is lost due to the dimple phenomenon by the method of forming a guard ring of a semiconductor device according to the related art.
도 3a 내지 도 3e는 본 발명에 따른 반도체 소자의 가드링 형성 방법을 도시한 단면도들.3A to 3E are cross-sectional views illustrating a method of forming a guard ring of a semiconductor device according to the present invention.
도 4는 본 발명에 따른 반도체 소자의 가드링 콘택 플러그 및 가드링용 콘택 플러그에 대한 레이아웃도.4 is a layout of the guard ring contact plug and the guard ring contact plug of the semiconductor device according to the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
10, 100 : 반도체 기판 20, 120 : 층간절연막10, 100: semiconductor substrate 20, 120: interlayer insulating film
30, 130 : 식각정지막 40, 140 : 저장전극 콘택 플러그30, 130: etch stop film 40, 140: storage electrode contact plug
50, 150 : 희생산화막 60, 160 : 저장전극 영역50, 150: sacrificial oxide layer 60, 160: storage electrode region
70, 170 : 가드링 영역 75, 175 : 저장전극70, 170: guard ring region 75, 175: storage electrode
80, 180 : 가드링 90 : 희생산화막이 유실된 부분80, 180: guard ring 90: part where the sacrificial oxide film is missing
110 : 저장전극 콘택홀 115 : 가드링용 콘택홀 110: storage electrode contact hole 115: guard ring contact hole
145 : 가드링용 콘택 플러그 145: contact ring for guard ring
Claims (5)
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| Application Number | Priority Date | Filing Date | Title |
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| KR1020040031388A KR20050106221A (en) | 2004-05-04 | 2004-05-04 | Guard-ring of semiconductor devices and method for fabricating the same |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1020040031388A KR20050106221A (en) | 2004-05-04 | 2004-05-04 | Guard-ring of semiconductor devices and method for fabricating the same |
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| KR20050106221A true KR20050106221A (en) | 2005-11-09 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011119373A3 (en) * | 2010-03-26 | 2011-12-22 | Altera Corporation | Integrated circuit guard rings |
| US8148764B2 (en) | 2009-06-30 | 2012-04-03 | Hynix Semiconductor Inc. | Semiconductor device having a high aspect cylindrical capacitor and method for fabricating the same |
-
2004
- 2004-05-04 KR KR1020040031388A patent/KR20050106221A/en not_active Application Discontinuation
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8148764B2 (en) | 2009-06-30 | 2012-04-03 | Hynix Semiconductor Inc. | Semiconductor device having a high aspect cylindrical capacitor and method for fabricating the same |
| WO2011119373A3 (en) * | 2010-03-26 | 2011-12-22 | Altera Corporation | Integrated circuit guard rings |
| US8097925B2 (en) | 2010-03-26 | 2012-01-17 | Altera Corporation | Integrated circuit guard rings |
| US8614130B2 (en) | 2010-03-26 | 2013-12-24 | Altera Corporation | Integrated circuit guard rings |
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