KR20040061621A - Method for fabricating mim capacitor - Google Patents
Method for fabricating mim capacitor Download PDFInfo
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- KR20040061621A KR20040061621A KR1020020087902A KR20020087902A KR20040061621A KR 20040061621 A KR20040061621 A KR 20040061621A KR 1020020087902 A KR1020020087902 A KR 1020020087902A KR 20020087902 A KR20020087902 A KR 20020087902A KR 20040061621 A KR20040061621 A KR 20040061621A
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- film
- silicon nitride
- upper electrode
- dielectric
- metal film
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- 239000003990 capacitor Substances 0.000 title claims abstract description 36
- 238000000034 method Methods 0.000 title claims abstract description 34
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 40
- 239000002184 metal Substances 0.000 claims abstract description 39
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 39
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000005468 ion implantation Methods 0.000 claims abstract description 10
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 15
- 238000004519 manufacturing process Methods 0.000 claims description 14
- 238000000137 annealing Methods 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 229910018182 Al—Cu Inorganic materials 0.000 claims description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 abstract description 7
- 229910007991 Si-N Inorganic materials 0.000 abstract description 5
- 229910006294 Si—N Inorganic materials 0.000 abstract description 5
- 239000012212 insulator Substances 0.000 abstract 1
- 239000010408 film Substances 0.000 description 91
- 230000008021 deposition Effects 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 229910003070 TaOx Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- -1 nitride silicon nitride Chemical class 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 보다 구체적으로는 MIM 캐패시터 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a MIM capacitor.
최근 반도체 제조 기술의 발달과 더불어, 메모리 소자의 수요가 급증하고 있다. 데이터 저장 수단으로 이용되는 커패시터는 전극의 면적과 전극간의 거리와 전극 사이에 삽입되는 유전막의 유전율에 따라 그 정전용량이 달라진다. 그런데, 반도체 장치가 고집적화됨에 따라 반도체 장치에서 커패시터 형성영역이 줄어들고 그 결과 커패시터의 전극면적이 작아져서 커패시터의 정전용량이 감소된다.Recently, with the development of semiconductor manufacturing technology, the demand for memory devices is increasing rapidly. The capacitor used as the data storage means varies in capacitance depending on the area of the electrode, the distance between the electrodes, and the dielectric constant of the dielectric film inserted between the electrodes. However, as the semiconductor device is highly integrated, the capacitor formation area in the semiconductor device is reduced, and as a result, the electrode area of the capacitor is reduced, thereby reducing the capacitance of the capacitor.
따라서, 반도체 장치의 집적 밀도가 증가함에 따라, 산화막보다 큰 유전 상수를 갖는 물질인 TiO(유전상수가 300 정도), TaOx(유전상수가 25정도)등이 이용된다. 이러한 유전 상수가 큰 물질들은 결정화를 위해 집적 공정 중 고온의 어닐 공정이 반드시 필요하다.Therefore, as the integration density of a semiconductor device increases, TiO (a dielectric constant of about 300), TaOx (a dielectric constant of about 25), and the like, which have a dielectric constant larger than that of an oxide film, are used. These high dielectric constant materials require a high temperature annealing process in the integration process for crystallization.
그러나, 어닐 공정은, R.B.Van DOVER, "Advaned dilectrics for gate oxide, DRAM RF capacitor", in IEDM Tech. Dig., 1998,pp823-826에 기재된 바와 같이, 박막의 표면거칠기를 저하시키고 높은 누설 전류와 낮은 문턱전압을 초래한다.However, the annealing process is described in R.B. Van DOVER, "Advaned dilectrics for gate oxide, DRAM RF capacitor", in IEDM Tech. As described in Dig., 1998, pp 823-826, the surface roughness of the thin film is reduced, resulting in high leakage current and low threshold voltage.
이러한 이유로, M.Maeda, "Dielectric characteristics of a metal-insulator-metal capacitor using plasma-enhanced chemical vapor deposited silicon nitride film", J. Vac.Sci. Technol. vol130, pp2419-2433, Dec. 1983)에 기재된 바와 같이, 최근 MIM 캐패시터의 유전막으로 유전율이 6∼8 가량으로 비교적 크며, 증착 온도가 낮으며, 집적 공정이 단순한 실리콘 질화막(Si3N4)을 가장 많이 사용하고 있다.For this reason, M. Maeda, "Dielectric characteristics of a metal-insulator-metal capacitor using plasma-enhanced chemical vapor deposited silicon nitride film", J. Vac. Sci. Technol. vol 130, pp 2419-2433, Dec. As described in (1983), a silicon nitride film (Si 3 N 4), which has a relatively large dielectric constant of about 6 to 8, a low deposition temperature, and a simple integration process, is most commonly used as a dielectric film of a MIM capacitor.
그러나, 상기 실리콘 질화막도 SiO2산화막에 비해 breakdown field strength가 낮고 VCC(Voltage Coefficient of Capacitor) 및 TCC(Temperature Coefficient of Capacitor)가 높은 단점이 있다. 특히, 알.에프(R.F) 어플리케이션(application)에서는 "0"에 가까운 매우 낮은 VCC가 요구되어지고 있다.However, the silicon nitride film also has a lower breakdown field strength and a higher voltage coefficient of capacitor (VCC) and higher temperature coefficient of capacitor (TCC) than the SiO 2 oxide film. In particular, a very low VCC close to " 0 " is required in an R.F. application.
도 1a 내지 도 1d는 종래 기술에 따른 MIM 캐패시터 제조 방법을 설명하기 위한 공정단면도이다.1A to 1D are cross-sectional views illustrating a method of manufacturing a MIM capacitor according to the prior art.
종래 기술에 따른 MIM 캐패시터 제조 방법은, 도 1a에 도시된 바와 같이, 반도체기판(1) 상에 절연막(3)을 형성한다. 이때, 상기 기판(1)에는, 도면에 도시되지 않았지만, 게이트 전극 및 소오스/드레인의 불순물영역을 포함한 트랜지스터(transistor) 및 상기 불순물영역과 연결되는 도전 플러그가 각각 구비되어져 있다.In the MIM capacitor manufacturing method according to the prior art, as shown in FIG. 1A, the insulating film 3 is formed on the semiconductor substrate 1. In this case, although not shown in the drawing, the substrate 1 is provided with a transistor including an impurity region of a gate electrode and a source / drain, and a conductive plug connected to the impurity region, respectively.
이어, 상기 절연막(3) 위에 Ti/TiN/Al-Cu/Ti/TiN의 배선 구조를 가진 캐패시터의 하부 전극(5)를 형성한다.Subsequently, a lower electrode 5 of a capacitor having a wiring structure of Ti / TiN / Al-Cu / Ti / TiN is formed on the insulating film 3.
이어, 도 1b에 도시된 바와 같이, 상기 하부전극(5)을 포함한 기판 전면에 NH3 및 SiH4 증착가스를 사용하여 PECVD(Plasma Enhanced Chemical Vapor Deposition) 방식으로 유전막용 실리콘 질화막(Si3N4)(7)을 형성한다. 이때, 유전막용 실리콘 질화막(Si3N4)(7) 대신 SiO2산화막을 이용할 수도 있다. 한편, 상기 실리콘 질화막(7)은 SiO2산화막과 비교하여 유전율이 크다.Subsequently, as shown in FIG. 1B, a dielectric nitride silicon nitride layer (Si 3 N 4) 7 is formed by using a plasma enhanced chemical vapor deposition (PECVD) method using NH 3 and SiH 4 deposition gases on the entire surface of the substrate including the lower electrode 5. Form. In this case, an SiO 2 oxide film may be used instead of the silicon nitride film (Si 3 N 4) 7 for the dielectric film. On the other hand, the silicon nitride film 7 has a higher dielectric constant than the SiO 2 oxide film.
그런 다음, 도 1c에 도시된 바와 같이, 상기 유전막용 실리콘 질화막(7) 상에 스퍼터링 공정에 의해 상부 전극용 금속막(9)을 증착한다. 이때, 상기 상부 전극용 금속막(9)은 MIM 캐패시터의 상부에 존재할 금속 배선의 사진 및 식각 공정이 용이하도록 캐패시터 특성이 열화되지 않는 범위에서 최대한 얇게 증착하는 것이 유리하다.Then, as shown in FIG. 1C, the upper electrode metal film 9 is deposited by the sputtering process on the silicon nitride film 7 for the dielectric film. In this case, the upper electrode metal film 9 is advantageously deposited as thin as possible in a range that does not deteriorate the capacitor characteristics so as to facilitate the photolithography and etching process of the metal wiring existing on the MIM capacitor.
이 후, 상기 상부 전극용 금속막(9) 위에 상부 전극 형성영역이 정의된 감광막 패턴(11)을 형성한다.Thereafter, a photosensitive film pattern 11 having an upper electrode formation region defined thereon is formed on the upper electrode metal film 9.
이어, 도 1d에 도시된 바와 같이, 상기 감광막 패턴을 마스크로 하고 상기 상부 전극용 금속막 및 유전막용 실리콘 질화막을 차례로 건식 식각하여 MIM 캐패시터 제작을 완료한다. 이때, 상기 건식 식각 공정에서, 상부 전극용 금속막 및 유전막을 동시에 식각할 수도 있고, 또는 상부 전극용 금속막만을 식각할 수도 있다.Subsequently, as shown in FIG. 1D, the photoresist pattern is used as a mask and dry etching is performed on the upper electrode metal layer and the dielectric layer silicon nitride layer in order to complete MIM capacitor fabrication. At this time, in the dry etching process, the upper electrode metal film and the dielectric film may be simultaneously etched, or only the upper electrode metal film may be etched.
미설명된 도면부호 8은 캐패시터의 유전막을 나타낸 것이며, 도면부호 10은 캐패시터의 상부 전극을 나타낸 것이다.Unexplained reference numeral 8 denotes the dielectric film of the capacitor, and reference numeral 10 denotes the upper electrode of the capacitor.
그러나, 종래의 기술에서는 유전막으로서 실리콘 질화막을 이용할 경우, 실리콘 질화막의 증착 공정에서, 상기 증착 가스 중 H성분은 완전히 제거되지 않으며, 실리콘 질화막 내에 Si-H, N-H 및 Si-N 등과 같은 불완전한 약한 결합이 존재하게 된다. 그 중 Si-H 결합은 많은 댕글링 결합을 유발시켜 하부층에 강한 압축 특성을 주게 된다. 이러한 Si-H결합이 증가함에 따라 생기는 문제점에 대해 W.A.P.Classen 등이 발표한 바 있는 "Characterization of plasma silicon nitride layers"라는 논문에 잘 나타나 있다. 특히, 문턱전압 및 누설 전류에 매우 불리한However, in the conventional technology, when the silicon nitride film is used as the dielectric film, in the deposition process of the silicon nitride film, the H component of the deposition gas is not completely removed, and incomplete weak coupling such as Si-H, NH, and Si-N in the silicon nitride film. Will exist. Among them, Si-H bonds induce a lot of dangling bonds and give a strong compressive property to the lower layer. The problem caused by the increase in Si-H bonds is well described in the paper "Characterization of plasma silicon nitride layers" published by W.A.P.Classen et al. In particular, very disadvantageous to threshold voltage and leakage current
문제점이 있었다.There was a problem.
이에 본 발명은 상기 종래의 문제점을 해결하기 위해 안출된 것으로, 유전막으로 실리콘 질화막을 증착하고 나서, 상기 실리콘 질화막에 N2 이온주입을 실시하여 N성분이 풍부한 실리콘 질화막을 형성함으로써, 누설 전류가 작고 VCC가 매우 낮은 MIM 캐패시터 제조 방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above problems, by depositing a silicon nitride film with a dielectric film, and then implanting N2 ion into the silicon nitride film to form a silicon nitride film rich in N components, the leakage current is small and VCC The purpose is to provide a very low MIM capacitor manufacturing method.
도 1a 내지 도 1d는 종래 기술에 따른 MIM 캐패시터 제조 방법을 설명하기 위한 공정단면도.1A to 1D are cross-sectional views illustrating a method of manufacturing a MIM capacitor according to the prior art.
도 2a 내지 도 2e는 본 발명에 따른 MIM 캐패시터 제조 방법을 설명하기 위한 공정단면도.2A to 2E are cross-sectional views illustrating a method of manufacturing a MIM capacitor according to the present invention.
상기 목적을 달성하기 위한 본 발명에 따른 MIM 캐패시터 제조 방법은 하부 전극이 구비된 반도체기판을 제공하는 단계와, 기판 상에 하부 전극을 덮는 유전막용 실리콘 질화막을 형성하는 단계와, 유전막용 실리콘 질화막에 N2 이온주입 공정및 어닐 공정을 진행하여 막내에 N성분을 풍부하게 하는 단계와, 유전막용 실리콘 질화막 구조에 상부 전극용 금속막을 형성하는 단계와, 상부 전극용 금속막 및 유전막용 실리콘 질화막을 선택 식각하여 유전막 및 상부 전극을 차례로 형성하는 단계를 포함한 것을 특징으로 한다.A method of manufacturing a MIM capacitor according to the present invention for achieving the above object comprises the steps of providing a semiconductor substrate provided with a lower electrode, forming a silicon nitride film for the dielectric film covering the lower electrode on the substrate, and a silicon nitride film for the dielectric film Performing N2 ion implantation and annealing to enrich the N component in the film, forming a metal film for the upper electrode on the silicon nitride film structure for the dielectric film, and selectively etching the metal film for the upper electrode and the silicon nitride film for the dielectric film To form a dielectric film and an upper electrode in turn.
상기 하부 전극 형성 공정은 Ti/TiN 금속막을 500∼1000Å 두께로 증착하고 나서, 상기 Ti/TiN금속막을 선택 식각한다.In the lower electrode forming process, the Ti / TiN metal film is deposited to a thickness of 500 to 1000 Å, and the Ti / TiN metal film is selectively etched.
상기 하부 전극은 4000∼5000Å 두께의 Al-Cu 금속막 및 TiN 단일 금속막 중 어느 하나를 이용한다.The lower electrode may use any one of an Al—Cu metal film and a TiN single metal film having a thickness of 4000 to 5000 GHz.
상기 N2이온주입 공정은 10eV 이내의 에너지를 공급한다.The N 2 ion implantation process supplies energy within 10 eV.
상기 어닐 공정은 350∼450℃ 온도 사이에서 30분 이내로 실시 및 450∼500℃ 온도 사이에서 30초 이상에서 90초 이하 동안에 RTP 실시 중 어느 하나의 공정에 의해 진행한다.The annealing process is carried out by any one of the processes of RTP for less than 30 minutes between 350 to 450 ℃ temperature and for more than 30 seconds to less than 90 seconds between 450 to 500 ℃ temperature.
상기 상부 전극용 금속막 형성 공정은 Ti막을 400∼600Å 두께로 증착하고 나서, 상기 Ti막 위에 TiN막을 1000∼2000Å 두께로 증착한다.In the upper electrode metal film forming step, a Ti film is deposited to a thickness of 400 to 600 GPa, and a TiN film is deposited to a thickness of 1000 to 2000 GPa on the Ti film.
이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2e는 본 발명에 따른 MIM 캐패시터 제조 방법을 설명하기 위한 공정단면도이다.2A to 2E are cross-sectional views illustrating a method of manufacturing a MIM capacitor according to the present invention.
본 발명의 일실시예에 따른 MIM 캐패시터 제조 방법은, 도 2a에 도시된 바와 같이, 먼저 게이트 전극(미도시) 및 소오스/드레인의 불순물영역(미도시)을 포함한트랜지스터 및 상기 불순물영역과 연결되는 도전 플러그(미도시)가 각각 구비된 반도체 기판을 제공한다.In the method of manufacturing a MIM capacitor according to an embodiment of the present invention, as shown in FIG. 2A, a transistor including a gate electrode (not shown) and an impurity region (not shown) of a source / drain are first connected to the impurity region. Provided are semiconductor substrates each provided with a conductive plug (not shown).
이어, 상기 반도체기판(100) 상에 상부 배선층과의 절연을 위한 절연막(102)을 형성한다. 그런 다음, 상기 절연막(102) 상에 스퍼터링 방식에 의해 Ti/TiN 금속막(미도시)을 500∼1000Å 두께로 증착하고 나서, 상기 Ti/TiN금속막을 선택 식각하여 하부 전극(104)을 형성한다. 이때, 상기 금속막은 여러가지 배선 중 하나의 배선을 이용하여 캐패시터 하부 전극으로 사용하므로, 배선과 동일 구조를 갖는 경우가 통상적이다.Subsequently, an insulating film 102 for insulating the upper wiring layer is formed on the semiconductor substrate 100. Next, a Ti / TiN metal film (not shown) is deposited to a thickness of 500 to 1000 Å on the insulating film 102 by sputtering, and then the Ti / TiN metal film is selectively etched to form a lower electrode 104. . In this case, since the metal film is used as the capacitor lower electrode by using one of various wirings, the metal film usually has the same structure as the wiring.
또한, 상기 하부 전극으로서 Ti/TiN금속막 대신 Al-Cu 금속막을 4000∼5000Å 두께로 형성하거나, TiN 단일 금속막을 사용할 수도 있다.In addition, instead of the Ti / TiN metal film, an Al—Cu metal film may be formed to a thickness of 4000 to 5000 GPa, or a TiN single metal film may be used as the lower electrode.
이 후, 도 2b에 도시된 바와 같이, 상기 하부 전극(104)을 포함한 기판 전면에 유전막용 실리콘 질화막(106)을 증착한다. 상기 실리콘 질화막(106)은 NH3 및 SiH4 증착가스를 이용하여 PECVD방식으로 증착하며, 500∼1000Å 두께를 가진다. 혼합 시그널에서 사용되는 MIM 캐패시터는 1fF/㎛2의 캐패시터가 가장 많이 사용되며, 유전막용 실리콘 질화막이 500∼1000Å 두께일때 상기 값을 얻어내기가 용이하다.Thereafter, as illustrated in FIG. 2B, a silicon nitride film 106 for dielectric film is deposited on the entire surface of the substrate including the lower electrode 104. The silicon nitride film 106 is deposited by PECVD using NH3 and SiH4 deposition gases, and has a thickness of 500 to 1000 GPa. The MIM capacitor used in the mixed signal is the most commonly used capacitor of 1fF / μm 2, and it is easy to obtain the above value when the silicon nitride film for the dielectric film is 500 to 1000 Å thick.
이어, 도 2c에 도시된 바와 같이, 상기 유전막용 실리콘 질화막 위에 N2가스를 이온주입(120)하고 나서, 상기 이온주입(120)된 결과물을 어닐(122) 처리 한다. 상기 이온주입(120) 공정은 10eV 이내의 에너지를 공급한다. 또한, 어닐(122) 공정은 Si-N결합이 잘 생기도록 활성화하는 것으로서, 350∼450℃ 온도 사이에서 30분이내로 실시하거나, 450∼500℃ 온도 사이에서 30초 이상에서 90초 이하 동안에 진행하는 RTP(Rapid Thermally Process)를 이용할 수도 있다.Subsequently, as illustrated in FIG. 2C, an ion implantation 120 of N 2 gas is performed on the silicon nitride layer for the dielectric film, and then the resultant of the ion implantation 120 is annealed 122. The ion implantation 120 process supplies energy within 10 eV. In addition, the annealing 122 process is to activate the Si-N bonds well, and may be performed within 30 minutes between 350 to 450 ° C., or proceed for 30 seconds to 90 seconds or less between 450 to 500 ° C. Rapid Thermally Process (RTP) can also be used.
상기 유전막용 실리콘 질화막은 PECVD 특성 상 약한 결합이라 알려져 있는 다수의 Si-H결합이 형성되어 있지만, N2분위기에서 어닐을 하게 되면, 막내에 N성분이 풍부해지며, 상기 N성분이 Si-H의 약한 결합을 깨뜨려 강한 결합력을 갖는 Si-N결합의 결합력을 증가시킴으로써, 누설 전류에 우수할 뿐만 아니라 매우 낮은 VCC 및 TCC를 갖는다.The silicon nitride film for the dielectric film has a large number of Si-H bonds, which are known to be weak bonds due to PECVD characteristics, but when annealed in an N 2 atmosphere, the N component becomes rich in the film. By breaking the weak bonds and increasing the bonding strength of the Si-N bonds with strong bonding forces, they are not only excellent in leakage current but also have very low VCC and TCC.
미설명된 도면 부호 106a는 이온주입 및 어닐 처리된 유전막용 실리콘 질화막을 나타낸 것이다.Unexplained reference numeral 106a shows a silicon nitride film for the dielectric film subjected to ion implantation and annealing.
그런 다음, 도 2d에 도시된 바와 같이, 상기 유전막용 실리콘 질화막(106a) 위에 상부 전극용 금속막(108)을 증착한다. 이때, 상기 상부 전극용 금속막(108)으로는 Ti막을 400∼600Å 두께로 증착하고 나서, 상기 Ti막 위에 TiN막을 1000∼2000Å 두께로 증착한 것을 이용한다. 상기 상부 전극용 금속막(108)은 본 발명에 따른 MIM 캐패시터 상부에 존재할 금속 배선의 사진 및 식각 공정이 용이하도록 캐패시터 특성이 열화되지 않는 범위에서 최대한 얇게 증착하는 것이 유리하다.Then, as shown in FIG. 2D, an upper electrode metal film 108 is deposited on the dielectric silicon nitride film 106a. At this time, as the upper electrode metal film 108, a Ti film is deposited to have a thickness of 400 to 600 GPa, and a TiN film is deposited to have a thickness of 1000 to 2000 GPa on the Ti film. The upper electrode metal film 108 is advantageously deposited as thin as possible in a range that does not deteriorate the capacitor characteristics so as to facilitate the photolithography and etching process of the metal wiring existing on the MIM capacitor according to the present invention.
이 후, 상기 상부 전극용 금속막(108) 상에 상부 전극 형성영역이 정의된 감광막 패턴(130)을 형성한다.Thereafter, a photoresist pattern 130 having an upper electrode formation region defined thereon is formed on the upper electrode metal film 108.
이어, 도 2e에 도시된 바와 같이, 상기 감광막 패턴을 마스크로 하고 상기 상부 전극용 금속막 및 유전막용 실리콘 질화막을 차례로 건식 식각하여 MIM 캐패시터 구조를 형성한다. 미설명된 도면 부호 107은 유전막을 나타낸 것이고, 도면 부호 109는 상부 전극을 나타낸 것이다.Subsequently, as shown in FIG. 2E, the photoresist pattern is used as a mask, and the upper metal film for dielectric and the silicon nitride film for dielectric film are sequentially etched to form a MIM capacitor structure. Unexplained reference numeral 107 denotes a dielectric film, and reference numeral 109 denotes an upper electrode.
그런 다음, 도면에는 도시되지 않았지만, 상기 MIM 캐패시터 구조에 통상의 반도체장치의 배선 공정을 실시한다.Then, although not shown in the figure, a wiring process of a conventional semiconductor device is performed on the MIM capacitor structure.
본 발명에 따르면, MIM캐패시터의 유전막으로서 실리콘 질화막에 N2이온주입 공정 및 어닐 공정을 진행한 N성분이 풍부한 실리콘 질화막을 이용함으로써, 누설전류의 원인이 되는 댕글링 결합 수를 억제시켜 우수한 유전막 특성을 갖도록 한다.According to the present invention, by using an N-rich silicon nitride film that has undergone an N 2 ion implantation process and an annealing process on a silicon nitride film as a dielectric film of a MIM capacitor, the number of dangling bonds that cause leakage current can be suppressed to provide excellent dielectric film characteristics. Have it.
이상에서와 같이, 본 발명에서는 유전막으로서 N성분이 풍부한 실리콘 질화막을 사용함으로써, 기존의 PECVD 특성 상 형성되던 Si-H결합을 Si-N결합으로 전환시켜 누설 전류의 원인이 되는 댕글링 결합수를 억제시킬 수 있다. 따라서, 우수한 유전막 특성을 갖는다.As described above, in the present invention, a silicon nitride film rich in N component is used as the dielectric film, thereby converting the Si-H bond formed in the conventional PECVD characteristic into a Si-N bond to thereby form a dangling bond water that causes leakage current. Can be suppressed. Thus, it has excellent dielectric film properties.
또한, 매우 낮은 VCC 및 TCC 특성을 가지므로, 혼합된 시그널 IC나 알.에프 어플리케이션에 유용하게 적용된다.It also has very low VCC and TCC characteristics, making it useful for mixed signal IC and RF applications.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
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