KR20040059922A - Method for forming copper interconnection of semiconductor device - Google Patents

Method for forming copper interconnection of semiconductor device Download PDF

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KR20040059922A
KR20040059922A KR1020020086427A KR20020086427A KR20040059922A KR 20040059922 A KR20040059922 A KR 20040059922A KR 1020020086427 A KR1020020086427 A KR 1020020086427A KR 20020086427 A KR20020086427 A KR 20020086427A KR 20040059922 A KR20040059922 A KR 20040059922A
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South Korea
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sin
wiring
via hole
low
oxide film
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KR1020020086427A
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Korean (ko)
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KR100896460B1 (en
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권태석
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for forming a copper line of a semiconductor device is provided to prevent diffusion of copper into an insulating layer, and to remove overhang by depositing thickly a diffusion barrier layer at sidewalls of damascene pattern. CONSTITUTION: SiN layers(5,7) and low-k oxide layers(6,8) are alternately deposited on a substrate having a lower copper line(4). By selectively etching the top low-k oxide layer(8), a via hole is formed. A damascene pattern is formed by selectively etching the low-k oxide layer(6) to remain the SiN layer(5). A diffusion barrier layer(11) is formed at sidewalls of the damascene pattern. Then, an upper copper line(12) is formed by filling a copper film in the damascene pattern.

Description

반도체소자의 구리배선 형성방법{Method for forming copper interconnection of semiconductor device}Method for forming copper interconnection of semiconductor device

본 발명은 반도체소자의 배선 형성방법에 관한 것으로, 특히대머신(damascene)구조에서의 구리배선 형성기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a wiring of a semiconductor device, and more particularly, to a technique for forming copper wiring in a damascene structure.

반도체소자의 집적도 증가와 더불어 배선의 선폭 및 콘택홀의 크기가 감소하고, 이에 따라 배선에 인가되는 전류밀도가 증대되어 EM(Electomigration)에 의한 배선의 신뢰성 저하 문제가 중요하게 되었다. EM은 배선에 전류(즉, 전자)가 흐를때 표면, 결정입계(grain boundary), 경계면, 격자에서 Al, Cu원자가 전자에 의해 밀려 이동하는 현상을 의미하며, 주고 결정입계가 합쳐지는 부분에서는 Al, Cu원자가 누적(accumulation)되어 힐록(hillock) 등을 유발하거나 또는 결정입계가 갈라지는 부분에서는 Al, Cu원자가 결핍(depletion)되어 빈 공간(vacancy)을 생성하면서 보이드(void)가 형성되고, 이렇게 형성된 보이드는 빈 공간을 트랩핑하여 Al, Cu 보이드가 점차적으로 성장하면서 결국에는 배선 자체가 단락된다. 특히, 배선 자체에 보이드(키홀)가 있을 경우, 표면으로의 이동이 원활하기 때문에 EM 페일(fail)의 발생이 크며, 또한 비아가 텅스텐플러그나 하부 배리어의 두께가 두꺼울 경우, 전자가 텅스텐 또는 배리어 금속을 지나 Al, Cu배선을 지날때 그 경계면에서 물질의 공급이 차단되어 보이드가 발생되어 페일이 되기도 한다. 또한, Cu배선의 경우, Cu배선보다 비아의 크기가 작기 때문에 배선에 인가되는 전류밀도가 증가하여 EM페일이 증가하는 문제점이 있다.In addition to the increase in the degree of integration of the semiconductor device, the line width of the wiring and the size of the contact hole are reduced, and accordingly, the current density applied to the wiring is increased, thereby causing a problem of lowering the reliability of the wiring due to EM (Electomigration). EM refers to a phenomenon in which Al and Cu atoms are moved by electrons in the surface, grain boundary, boundary, and lattice when current (i.e., electrons) flows through the wiring. In the part where the Cu atoms accumulate, causing hillocks, or when the grain boundaries are separated, Al and Cu atoms are depleted to form voids, thereby forming voids. The void traps the empty space so that the Al and Cu voids gradually grow, eventually shorting the wiring itself. In particular, when there is a void (keyhole) in the wiring itself, the occurrence of EM fail is large because the movement to the surface is smooth, and when the via is thick in the tungsten plug or the lower barrier, the electron is tungsten or the barrier. When passing through metal and passing Al and Cu wiring, the supply of material is blocked at the interface, and voids are generated and fail. In addition, in the case of the Cu wiring, since the via size is smaller than that of the Cu wiring, the current density applied to the wiring increases, thereby increasing the EM fail.

종래 기술을 이용하여 대머신 구조의 구리(Cu) 배선을 형성할 경우, 도1과 같이 비아 에치(via etch) 또는 금속 배리어 전세정시 절연막이 구리에 의해 오염되기 때문에 구리의 확산이 용이하다는 문제점이 발생한다. 또한, 구리가 층간절연막을 통하여 확산되는 것을 방지하기 위하여 금속 배리어를 증착하는데 이때, 도2에 도시한 바와 같이 증착되는 배리어가 콘택홀 측면보다 하부에 더 많이 증착되고 또한 콘택홀 입구에 오버행(over-hang)이 발생함에 따라 다음과 같은 문제점이 발생한다.In the case of forming a copper wiring having a damascene structure using the prior art, since the insulating film is contaminated by copper during via etch or metal barrier pre-cleaning as shown in FIG. Occurs. In addition, a metal barrier is deposited to prevent copper from diffusing through the interlayer insulating film, where more barriers are deposited below the contact hole side as shown in FIG. 2 and overhang at the contact hole inlet. -hang) causes the following problems.

측벽에 배리어 두께가 얇아지면 로우-k(low-k) 물질에 존재하는 세공(pore)으로 인해 얇은 두께의 Ta 또는 TaN 핀홀이 발생하여 구리의 확산이 용이하게 되며, 콘택홀 입구의 오버행에 의해 구리 증착후 키홀(key hole)이 발생하게 된다. 또한, 콘택홀 바닥부위의 배리어가 두꺼울 경우, 전자가 금속배리어를 지나 구리배선을 지날때 그 경계면에서 물질의 공급이 차단되어 보이드(void)가 발생되어 배선 자체가 단락되는 문제가 생긴다.The thinner barrier thickness on the sidewalls results in a thinner Ta or TaN pinhole due to the pore present in the low-k material, facilitating the diffusion of copper and overhanging the contact hole inlet. After deposition, key holes are generated. In addition, when the barrier at the bottom of the contact hole is thick, when electrons pass through the metal barrier and pass through the copper wiring, the supply of material is blocked at the interface, causing voids to cause a short circuit of the wiring itself.

본 발명은 상기 문제점을 해결하기 위한 것으로써, 주 배선재료인 Cu 증착전 비아에치시 하부 Cu배선이 드러나지 않게 SiN을 남긴 상태에서 배리어를 증착한 후, Ar 스퍼터링으로 바닥 부위의 배리어와 SiN을 식각하여 비아홀 측벽에 Cu와 SiN을 재증착시킴으로써 Cu 오염 및 Cu 확산을 방지하고, 비아홀 입구의 오버행을 제거하여 Cu증착시 키홀이 발생하지 않도록 하며, 바닥부위의 배리어를 얇게 증착하여 전자가 금속 배리어를 지나 Cu배선을 지날때 그 경계면에서 물질의 공급이 차단되어 발생하는 EM페일을 감소시킬 수 있도록 하는 반도체소자의 구리배선 형성방법을 제공하는데 목적이 있다.The present invention is to solve the above problems, after the deposition of the barrier in the state of leaving the SiN so that the lower Cu wiring is not exposed during the via deposition before the main wiring material Cu deposition, etching the barrier and SiN of the bottom portion by Ar sputtering By re-depositing Cu and SiN on the sidewall of the via hole, it prevents Cu contamination and Cu diffusion, and eliminates overhang of the via hole inlet so that key hole does not occur when Cu is deposited. It is an object of the present invention to provide a method for forming a copper wiring in a semiconductor device that can reduce EM fail caused by blocking the supply of material at the interface when passing through the Cu wiring.

도1 및 도2는 종래기술의 문제점을 도시한 도면,1 and 2 illustrate the problems of the prior art;

도3 및 도4는 본 발명의 원리를 도시한 도면,3 and 4 illustrate the principles of the invention;

도5a 내지 도5i는 본 발명에 의한 대머신 구조의 구리배선 형성방법을 도시한 공정순서도.Figures 5a to 5i is a process flow chart showing a copper wiring forming method of the damascene structure according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1,5,7 : SiN 2,6,8 : 로우-k산화막1,5,7 SiN 2,6,8 Low-k oxide film

3,11 : 확산배리어 4 : 하부 구리배선3,11 diffusion barrier 4: lower copper wiring

9 : 비아홀 12 : 상부 구리배선9: via hole 12: upper copper wiring

상기 목적을 달성하기 위한 본 발명의 반도체소자의 구리배선 형성방법은 하부 구리배선이 형성된 기판상에 SiN, 로우-k산화막, SiN, 로우-k산화막을 번갈아가면서 증착하는 제1단계와, 상기 최상층의 로우-k산화막을 선택적으로 식각하여 상부 금속배선과 하부 금속배선을 연결하는 비아홀을 형성하는 제2단계, 소정의 감광막패턴을 이용하여 상기 로우-k산화막을 식각하여 대머신구조를 형성하되, 상기 하부 구리배선이 드러나지 않도록 상기 비아홀 바닥부위의 SiN이 남도록 식각하는 제3단계, 기판 전면에 확산배리어를 증착하고 Ar 스퍼터링으로 비아홀 바닥부위의 확산배리어와 SiN을 식각하여 비아홀 측벽에 Cu와 SiN이 재증착되도록 하는 공정을 반복적으로 행하여 상기 하부 구리배선을 노출시키는 제4단계 및 상기 대머신구조 내부에 구리를 증착하여 상기 하부 구리배선과 연결되는 상부 구리배선을 형성하는 제5단계를 포함하여 구성되는 것을 특징으로 한다.The method for forming a copper wiring of the semiconductor device of the present invention for achieving the above object is a first step of alternately depositing SiN, low-k oxide film, SiN, low-k oxide film on the substrate on which the lower copper wiring is formed, and the top layer Selectively etching the low-k oxide film to form a via hole connecting the upper metal wire and the lower metal wire to form a damascene structure by etching the low-k oxide film using a predetermined photoresist pattern; In the third step of etching the SiN of the bottom of the via hole so that the lower copper wiring is not exposed, a diffusion barrier is deposited on the entire surface of the substrate, and Cu and SiN are formed on the sidewall of the via hole by etching the diffusion barrier and SiN at the bottom of the via hole by Ar sputtering. Repeatedly performing the process of redepositing to expose the lower copper wiring and depositing copper inside the damascene structure And a fifth step of forming an upper copper wiring connected to the lower copper wiring.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

종래기술의 문제점을 해결하기 위하여 본 발명은 비아에치시 하부의 Cu배선(1)이 드러나지 않도록 SiN(10)을 남긴 상태에서 Cu 확산배리어(15)를 도3과 같이 증착한 후, Ar 스퍼터링으로 하부의 배리어와 SiN을 식각하여 도4와 같이 비아홀 측벽에 Cu와 SiN이 재증착(Re-deposition)되도록 하고, 이러한 과정을 반복하여(배리어 증착 -> Ar스퍼티링 식각-> 배리어 증착 -> Ar 스퍼터링 식각) 하부배선의 Cu가 노출될 수 있도록 한다. 이때, 측벽의 배리어 두께는 두껍게, 비아홀 바닥부위의 배리어는 얇게 증착한다.In order to solve the problems of the prior art, the Cu diffusion barrier 15 is deposited as shown in FIG. 3 in a state in which SiN 10 is left so that the Cu wiring 1 at the bottom of the via etching is not exposed, followed by Ar sputtering. The lower barrier and SiN are etched to re-deposition Cu and SiN on the sidewalls of the via holes as shown in FIG. 4, and the process is repeated (barrier deposition-> Ar sputtering etching-> barrier deposition-> Ar sputtering etching) to expose the Cu of the lower wiring. At this time, the barrier thickness of the side wall is thick, and the barrier at the bottom of the via hole is thinly deposited.

또한, 확산 배리어 증착시에도 웨이퍼 바닥부위에 RF AC바이어스를 인가하여 이온화된 Ar+, Ta+, TaN+이온으로 바닥부위의 배리어와 SiN을 식각할 수 있다.In addition, during diffusion barrier deposition, an RF AC bias is applied to the bottom of the wafer to etch the bottom barrier and SiN with ionized Ar +, Ta +, and TaN + ions.

도5a 내지 도5i에 본 발명의 일실시예에 의한 대머신 구조의 구리배선 형성방법을 공정순서에 따라 나타내었다.5A to 5I illustrate a method of forming copper wirings of a damascene structure according to an embodiment of the present invention, according to a process sequence.

먼저, 도5a를 참조하면, 실리콘기판(도시하지 않음)위에 대머신 구조를 이용하여 하부 금속배선을 형성하기 위해 SiN(1)과 로우-k(low-k)산화막(2)을 차례로 증착한 후, 감광제(도시하지 않음)를 이용한 노광 및 현상을 통해 배선이 형성될 트렌치부분의 산화막(2)을 선택적으로 식각한 다음, 감광제를 제거한다.First, referring to FIG. 5A, in order to form a lower metal interconnection using a damascene structure on a silicon substrate (not shown), a SiN 1 and a low-k oxide film 2 are sequentially deposited. Thereafter, the oxide film 2 in the trench portion where the wiring is to be formed is selectively etched through exposure and development using a photosensitive agent (not shown), and then the photosensitive agent is removed.

이어서 도5b를 참조하면, 주 배선재료인 Cu를 증착하기 전에 확산배리어로 TaN(3)(또는 Ta, W, WN, Ti, TiN)을 증착한 다음, Cu 씨드층을 CVD 또는 PVD방식에 의해 증착한 후, Cu(4)를 전기도금(electroplating)방법으로 증착한다. Cu 증착후, CMP공정으로 배선이 형성되는 트렌치부위에만 Cu를 남기고 나머지 부분은 제거한다.5B, TaN (3) (or Ta, W, WN, Ti, TiN) is deposited in a diffusion barrier before deposition of Cu as the main wiring material, and then the Cu seed layer is deposited by CVD or PVD. After the deposition, Cu (4) is deposited by electroplating. After Cu deposition, Cu is left only in the trench where wirings are formed by the CMP process, and the remaining portions are removed.

도5c를 참조하면, 상부 금속배선과 하부 금속배선간의 절연 및 Cu 확산을 방지하기 위해 SiN(5), 로우-k산화막(6), SiN(7), 로우-k산화막(8)을 번갈아가면서 증착한다.Referring to FIG. 5C, the SiN 5, the low-k oxide film 6, the SiN 7, and the low-k oxide film 8 are alternately disposed to prevent insulation and Cu diffusion between the upper metal wiring and the lower metal wiring. Deposit.

도5d를 참조하면, 상기 최상층의 로우-k산화막(8)을 선택적으로 식각하여 상부 금속배선과 하부 금속배선을 연결하는 비아홀(9)을 형성한다.Referring to FIG. 5D, the low-k oxide film 8 of the uppermost layer is selectively etched to form a via hole 9 connecting the upper metal wiring and the lower metal wiring.

도5e를 참조하면, 대머신구조를 이용하여 상부 금속배선을 형성하기 위해 감광제를 도포한 후, 노광 및 현상에 의해 소정의 패턴(10)을 형성하고, 이를 마스크로 이용하여 도5f와 같이 산화막을 식각하여 배선이 형성될 부분에 비아홀을 형성한 다음, 감광제를 제거한다. 이 과정에서 도5d에서 형성된 배성형성부위가 추가로 식각되는데 이때 하부 금속배선(4)이 드러나지 않도록 SiN(5)이 50~1000Å 남도록 식각을 행한다.Referring to FIG. 5E, after the photosensitive agent is coated to form the upper metal wiring using the damascene structure, a predetermined pattern 10 is formed by exposure and development, and the oxide film is formed as shown in FIG. 5F by using it as a mask. Etching to form a via hole in the portion where the wiring is to be formed, and then remove the photosensitive agent. In this process, the formation region formed in FIG. 5D is additionally etched. At this time, etching is performed such that the SiN 5 is left at 50 to 1000 kPa so that the lower metal wiring 4 is not exposed.

다음에 도5g를 참조하면, 주 배선재료인 Cu를 증착하기 전에 확산배리어로서 TaN(또는 Ta, W, WN, Ti, TiN)(11)을 증착한다. 이때, 압력은 30mT 이하로 하고, 증착두께는 1500Å 이하로 하는 것이 바람직하다.Referring next to FIG. 5G, TaN (or Ta, W, WN, Ti, TiN) 11 is deposited as a diffusion barrier before depositing Cu as the main wiring material. At this time, the pressure is preferably 30 mT or less, and the deposition thickness is preferably 1500 kPa or less.

도5h를 참조하면, 상기 확산배리어를 증착한 후, Ar 스퍼터링으로 비아홀 바닥부위의 배리어와 SiN을 식각하여 비아홀 측벽에 Cu와 SiN이 재증착되도록 하고, 이러한 과정을 반복하여(배리어 증착 -> Ar 스퍼터링 -> 배리어 증착 -> Ar 스퍼터링) 하부의 구비배선(4)이 노출되도록 한다. 이때, 측벽 배리어는 두껍게, 비아홀 바닥의 배리어는 얇게 증착한다. 또는 확산배리어 증착시 웨이퍼 바닥부위에 RF AC바이어스를 인가하여 이온화된 Ar+, Ta+, TaN+이온으로 비아홀 바닥부위의 배리어와 SiN을 식각할 수도 있다. 이 경우에는 반복 공정이 필요없다.Referring to FIG. 5H, after the diffusion barrier is deposited, Cu and SiN are re-deposited on the sidewalls of the via hole by Ar sputtering to etch the barrier and SiN at the bottom of the via hole, and the process is repeated (barrier deposition-> Ar). Make the provisional wiring 4 under the sputtering-> barrier deposition-> Ar sputtering) exposed. At this time, the sidewall barrier is thick and the barrier at the bottom of the via hole is thinly deposited. Alternatively, during deposition of the diffusion barrier, an RF AC bias may be applied to the bottom of the wafer to etch the barrier and the SiN of the bottom of the via hole with ionized Ar +, Ta +, and TaN + ions. In this case, a repeating process is not necessary.

상기 Ar 스퍼터링시 압력은 30mT 이하로 하고, Ar 스퍼터링 식각에 의한 비아홀 바닥부위의 배리어 두께는 1000Å 이하, 비아홀 측벽부위에 재증착되는 두께는 10~1000Å 이하가 되도록 한다. Ar 대신에 Kr이나 Xe가스를 사용할 수도 있다.When the Ar sputtering pressure is 30mT or less, the barrier thickness of the bottom portion of the via hole by Ar sputtering etching is 1000Å or less, and the thickness of redeposition on the via hole sidewall portion is 10 ~ 1000Å or less. Instead of Ar, Kr or Xe gas may be used.

도5i를 참조하면, Cu씨드층을 CVD 또는 PVD방식에 의해 증착한 후, 주 배선재료인 Cu(12)를 전기도금 방법에 의해 증착한 후, CMP공정으로 비아홀 내에만 Cu를 남김으로써 하부 구리배선과 연결되는 상부 구리배선을 완성한다.Referring to FIG. 5I, after depositing a Cu seed layer by CVD or PVD, after depositing Cu 12 as a main wiring material by an electroplating method, Cu is left in the via hole only by a CMP process. Complete the upper copper wiring to be connected to the wiring.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

본 발명의 기술을 이용하여 대머신구조의 구리배선을 형성할 경우, 비아 식각시 하부 구리배선이 드러나지 않게 SiN을 남긴 상태에서 구리 확산배리어를 증착하기 때문에 비아 식각, 금속배리어 증착 전세정시 절연막이 구리에 의해 오염되는 것을 방지할 수 있을 뿐만 아니라, 비아홀 또는 대머신 구조에서의 배선 측벽에 배리어를 두껍게 증착함으로써 배리어 두께가 얇아질 경우 Ta 또는 TaN 핀홀의 발생으로 인한 절연막으로의 구리의 확산을 막을 수 있다. 또한, Ar 스퍼터링에 의해 비아홀 입구의 오버행을 제거할 수 있기 때문에 구리 증착시 키홀이 발생하지 않아 배선에 전류가 흐를때 구리원자의 표면으로의 이동(EM)을 억제하여 EM페일을 감소시킬 수 있으며, 바닥부위의 배리어가 얇게 증착되기 때문에 전자가 금속배리어를 지나 구리배선을 통과할때 그 경계면에서 물질의 공급이 차단되지 않기 때문에 EM페일을 감소시킬 수 있다.In the case of forming the copper wiring of the damascene structure using the technique of the present invention, since the copper diffusion barrier is deposited in the state of leaving SiN so that the lower copper wiring is not exposed during the via etching, the insulating film is copper during the via etching and the metal barrier deposition pre-cleaning. Not only can it be prevented from being contaminated by the film, but it can also prevent the diffusion of copper into the insulating film due to the occurrence of Ta or TaN pinhole when the barrier thickness becomes thin by depositing a thick barrier on the wiring sidewall in the via hole or the damascene structure. have. In addition, since the overhang of the via hole inlet can be removed by Ar sputtering, keyholes do not occur during copper deposition, and thus, EM fail can be reduced by suppressing the movement of copper atoms (EM) to the surface of the copper atoms when current flows in the wiring. As the barrier on the bottom is deposited thinly, the EM fail can be reduced because the supply of material at the interface is not blocked when electrons pass through the metal barrier and pass through the copper wiring.

Claims (6)

하부 구리배선이 형성된 기판상에 SiN, 로우-k산화막, SiN, 로우-k산화막을 번갈아가면서 증착하는 제1단계와;A first step of alternately depositing SiN, low-k oxide film, SiN, low-k oxide film on the substrate on which the lower copper wiring is formed; 상기 최상층의 로우-k산화막을 선택적으로 식각하여 상부 금속배선과 하부 금속배선을 연결하는 비아홀을 형성하는 제2단계;Selectively etching the low-k oxide film of the uppermost layer to form a via hole connecting the upper metal wiring and the lower metal wiring; 소정의 감광막패턴을 이용하여 상기 로우-k산화막을 식각하여 대머신구조를 형성하되, 상기 하부 구리배선이 드러나지 않도록 상기 비아홀 바닥부위의 SiN이 남도록 식각하는 제3단계;A third step of forming a damascene structure by etching the low-k oxide film using a predetermined photoresist pattern, wherein the SiN of the bottom portion of the via hole remains so that the lower copper wiring is not exposed; 기판 전면에 확산배리어를 증착하고 Ar 스퍼터링으로 비아홀 바닥부위의 확산배리어와 SiN을 식각하여 비아홀 측벽에 Cu와 SiN이 재증착되도록 하는 공정을 반복적으로 행하여 상기 하부 구리배선을 노출시키는 제4단계; 및Depositing a diffusion barrier on the entire surface of the substrate and etching the diffusion barrier and SiN at the bottom of the via hole by Ar sputtering to re-deposit Cu and SiN on the sidewall of the via hole to expose the lower copper wiring; And 상기 대머신구조 내부에 구리를 증착하여 상기 하부 구리배선과 연결되는 상부 구리배선을 형성하는 제5단계를 포함하여 구성되는 반도체소자의 구리배선 형성방법.And depositing copper into the damascene structure to form an upper copper interconnection connected to the lower copper interconnection. 제1항에 있어서,The method of claim 1, 상기 제3단계에서 하부 구리배선이 드러나지 않도록 SiN이 50~1000Å 남도록 식각하는 것을 특징으로 하는 반도체소자의 구리배선 형성방법.In the third step, the copper wiring forming method of the semiconductor device, characterized in that the etching so that the SiN is left 50 ~ 1000Å so that the lower copper wiring is not exposed. 제1항에 있어서,The method of claim 1, 상기 제4단계에서 상기 확산배리어로서 TaN Ta, W, WN, Ti 또는 TiN을 증착하는 것을 특징으로 하는 반도체소자의 구리배선 형성방법.And forming TaN Ta, W, WN, Ti, or TiN as the diffusion barrier in the fourth step. 제3항에 있어서,The method of claim 3, 상기 확산배리어 증착시 압력은 30mT 이하로 하고, 증착두께는 1500Å 이하로 하는 것을 특징으로 하는 반도체소자의 구리배선 형성방법.And a pressure of 30 mT or less and a deposition thickness of 1500 kPa or less during the diffusion barrier deposition. 제1항에 있어서,The method of claim 1, 상기 제4단계에서 Ar 스퍼터링 식각에 의한 비아홀 바닥부위의 배리어 두께는 1000Å 이하, 비아홀 측벽부위에 재증착되는 두께는 10~1000Å 이하가 되도록 공정을 실시하는 것을 특징으로 하는 반도체소자의 구리배선 형성방법.In the fourth step, the copper wiring forming method of the semiconductor device, characterized in that the barrier thickness at the bottom of the via hole by the Ar sputtering etching is less than 1000Å, the thickness of redeposited on the sidewall of the via hole is 10 ~ 1000Å or less. . 하부 구리배선이 형성된 기판상에 SiN, 로우-k산화막, SiN, 로우-k산화막을 번갈아가면서 증착하는 제1단계와;A first step of alternately depositing SiN, low-k oxide film, SiN, low-k oxide film on the substrate on which the lower copper wiring is formed; 상기 최상층의 로우-k산화막을 선택적으로 식각하여 상부 금속배선과 하부금속배선을 연결하는 비아홀을 형성하는 제2단계;Selectively etching the low-k oxide film of the uppermost layer to form a via hole connecting the upper metal wiring and the lower metal wiring; 소정의 감광막패턴을 이용하여 상기 로우-k산화막을 식각하여 대머신구조를 형성하되, 상기 하부 구리배선이 드러나지 않도록 상기 비아홀 바닥부위의 SiN이 남도록 식각하는 제3단계;A third step of forming a damascene structure by etching the low-k oxide film using a predetermined photoresist pattern, wherein the SiN of the bottom portion of the via hole remains so that the lower copper wiring is not exposed; 기판 전면에 확산배리어를 증착하고 기판 바닥부위에 RF AC바이어스를 인가하여 이온화된 Ar+, Ta+, TaN+이온으로 비아홀 바닥부위의 배리어와 SiN을 식각하여 상기 하부 구리배선을 노출시키는 제4단계; 및Depositing a diffusion barrier on the entire surface of the substrate and applying a RF AC bias to the bottom of the substrate to expose the lower copper wiring by etching the barrier and SiN at the bottom of the via hole with ionized Ar +, Ta + and TaN + ions; And 상기 대머신구조 내부에 구리를 증착하여 상기 하부 구리배선과 연결되는 상부 구리배선을 형성하는 제5단계를 포함하여 구성되는 반도체소자의 구리배선 형성방법.And depositing copper into the damascene structure to form an upper copper interconnection connected to the lower copper interconnection.
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KR100694979B1 (en) * 2004-12-23 2007-03-14 주식회사 하이닉스반도체 Method of forming a metal line in a semiconductor device
KR100800831B1 (en) 2006-10-25 2008-02-04 동부일렉트로닉스 주식회사 Method for forming copper line

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JP3463979B2 (en) 1997-07-08 2003-11-05 富士通株式会社 Method for manufacturing semiconductor device
JP2000294634A (en) * 1999-04-07 2000-10-20 Nec Corp Semiconductor device and manufacture of the same
JP2001110808A (en) 1999-10-12 2001-04-20 Sony Corp Manufacturing method of semiconductor device
KR20020032698A (en) * 2000-10-26 2002-05-04 박종섭 Method of forming a copper wiring in a semiconductor device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100694979B1 (en) * 2004-12-23 2007-03-14 주식회사 하이닉스반도체 Method of forming a metal line in a semiconductor device
KR100800831B1 (en) 2006-10-25 2008-02-04 동부일렉트로닉스 주식회사 Method for forming copper line

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