KR20020032698A - Method of forming a copper wiring in a semiconductor device - Google Patents
Method of forming a copper wiring in a semiconductor device Download PDFInfo
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- KR20020032698A KR20020032698A KR1020000063146A KR20000063146A KR20020032698A KR 20020032698 A KR20020032698 A KR 20020032698A KR 1020000063146 A KR1020000063146 A KR 1020000063146A KR 20000063146 A KR20000063146 A KR 20000063146A KR 20020032698 A KR20020032698 A KR 20020032698A
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract description 137
- 229910052802 copper Inorganic materials 0.000 title claims abstract description 136
- 239000010949 copper Substances 0.000 title claims abstract description 136
- 238000000034 method Methods 0.000 title claims abstract description 43
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 239000010410 layer Substances 0.000 claims abstract description 79
- 238000009792 diffusion process Methods 0.000 claims abstract description 41
- 239000011229 interlayer Substances 0.000 claims abstract description 25
- 230000009977 dual effect Effects 0.000 claims abstract description 18
- 230000004888 barrier function Effects 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000011065 in-situ storage Methods 0.000 claims abstract description 7
- 239000002184 metal Substances 0.000 claims description 38
- 229910052751 metal Inorganic materials 0.000 claims description 38
- 238000005530 etching Methods 0.000 claims description 29
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 claims description 14
- 239000005751 Copper oxide Substances 0.000 claims description 14
- 229910000431 copper oxide Inorganic materials 0.000 claims description 14
- 238000005229 chemical vapour deposition Methods 0.000 claims description 9
- 230000002265 prevention Effects 0.000 claims description 6
- 238000000231 atomic layer deposition Methods 0.000 claims description 4
- 239000003292 glue Substances 0.000 claims description 4
- 238000005240 physical vapour deposition Methods 0.000 claims description 3
- 238000001465 metallisation Methods 0.000 abstract 1
- 239000007789 gas Substances 0.000 description 17
- 238000000151 deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- 150000001879 copper Chemical class 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 구리 배선 형성 방법에 관한 것으로, 특히 고저항값을 가지는 구리 확산 방지 금속층에 의해 하부 구리 배선 및 상부 구리 배선의 접촉 저항값이 증가하는 것을 방지하여 전기적 특성을 향상시킬 수 있는 반도체 소자의 구리 배선 형성 방법에 관한 것이다.The present invention relates to a method for forming a copper wiring of a semiconductor device, and in particular, the electrical resistance can be improved by preventing the contact resistance values of the lower copper wiring and the upper copper wiring from increasing by the copper diffusion preventing metal layer having a high resistance value. A copper wiring formation method of a semiconductor element.
구리는 특유의 낮은 저항값 때문에 반도체 소자의 금속 배선 재료로 많이 사용되고 있다.Copper is widely used as a metal wiring material for semiconductor devices because of its unique low resistance value.
종래의 구리 금속 배선 형성 방법은 기본적으로 트랜치와 콘택홀(또는 비아)로 이루어진 이중 구조의 듀얼 다마신 패턴이 형성된 층간 절연막 상에 구리 확산 방지 금속층을 형성한 후 층간 절연막 상의 구리 확산 방지 금속층을 제거하고, 듀얼 다마신 패턴 내부에 구리를 매립하여 구리 배선을 형성한다.Conventional copper metal wiring formation method basically forms a copper diffusion preventing metal layer on an interlayer insulating film having a dual damascene pattern having a dual structure consisting of trenches and contact holes (or vias), and then removes the copper diffusion preventing metal layer on the interlayer insulating film. Then, copper is embedded in the dual damascene pattern to form a copper wiring.
이러한 구리 배선이 다층으로 적층되어 있을 경우 층간 배선을 연결하는 비아 콘택 하부는 하부 구리 배선/구리 확산 방지 금속층/상부 구리 배선의 적층 구조를 이루고있다. 여기서, 형성되는 구리 확산 방지 금속층은 구리가 절연막으로 확산되어 구배 배선의 전기적 특성이 저하되는 것을 방지하기 위하여 필수적으로 형성된다. 이러한 구리 확산 방지 금속층은 구리에 비하여 높은 저항값을 가진다. 이 경우, 비아 저항이 높고, 전류 흐름에 따른 구리 원자 이동이 구리 확산 방지 금속층에 의해 방해되어 비아 하부에서 불량이 발생된다. 이는 상부 구리 배선에서의 구리 원자 이동이 구리 확산 방지 금속층에 의해 방해를 받기 때문이다. 다시 말해, 하부 구리 배선과 상부 구리 배선 사이에 형성된 구리 확산 방지 금속층은 구리의 저저항 특성을 열화시켜 전기적 특성이 저하되는 문제점이 있다.When the copper wirings are stacked in multiple layers, the bottom of the via contact connecting the interlayer wirings has a laminated structure of a lower copper wiring / copper diffusion preventing metal layer / upper copper wiring. Here, the copper diffusion preventing metal layer formed is essentially formed in order to prevent copper from diffusing into the insulating film to lower the electrical characteristics of the gradient wiring. This copper diffusion preventing metal layer has a higher resistance value than copper. In this case, the via resistance is high, and copper atom movement due to the current flow is hindered by the copper diffusion preventing metal layer, thereby causing a defect in the bottom of the via. This is because copper atom movement in the upper copper wiring is hindered by the copper diffusion preventing metal layer. In other words, the copper diffusion preventing metal layer formed between the lower copper wiring and the upper copper wiring has a problem of deteriorating the low resistance characteristics of copper and lowering electrical characteristics.
따라서, 본 발명은 상기의 문제점을 해결하기 위하여 하부 구리 배선과 상부 구리 배선이 비아의 저면에서 직접 연결되어 배선이 이루어질 수 있도록 함으로써 구리의 저저항 특성을 유지하여 소자 동작의 전기적 특성을 향상시킬 수 있는 반도체 소자의 구리 배선 형성 방법을 제공하는데 그 목적이 있다.Accordingly, in order to solve the above problem, the lower copper wiring and the upper copper wiring are directly connected at the bottom of the via so that the wiring can be made, thereby maintaining the low resistance characteristics of the copper and improving the electrical characteristics of the device operation. It is an object of the present invention to provide a method for forming a copper wiring of a semiconductor device.
도 1a 내지 도 1d는 본 발명에 따른 반도체 소자의 구리 배선 형성 방법을 설명하기 위하여 순차적으로 도시한 소자의 단면도.1A to 1D are cross-sectional views of devices sequentially shown to explain a method for forming a copper wiring of a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>
1 : 반도체 기판2 : 하부 구리 배선1 semiconductor substrate 2 lower copper wiring
3 : 구리 확산 방지막4 : 제 1 절연막3: copper diffusion prevention film 4: first insulating film
5 : 식각 방지 절연막6 : 제 2 절연막5 etching prevention insulating film 6: second insulating film
7 : 하드 마스크용 절연막8 : 구리 확산 방지 금속층7 Insulation film for hard mask 8 Copper diffusion preventing metal layer
9 : 상부 구리 배선40 : 층간 절연막9: upper copper wiring 40: interlayer insulating film
본 발명에 따른 반도체 소자의 구리 배선 형성 방법의 제 1 실시예는 하부 구리 배선 상에 층간 절연막을 형성한 후 트렌치 및 비아로 이루어진 듀얼 다마신 패턴을 형성하는 단계, 듀얼 다마신 패턴을 포함한 전체 상에 구리 확산 방지 금속층을 형성하는 단계, 방향성 식각으로 상기 층간 절연막 상의 구리 확산 방지 금속층 및 비아 저면의 구리 확산 방지 금속층을 제거하는 단계, 비아 저면에 노출된 하부 구리 배선 표면의 구리 산화막을 제거하는 단계, 전체 상에 화학적 기상 증착법으로 시드 구리층을 형성하는 단계 및 듀얼 다마신 패턴 내부에 인-시투로 구리 배선을 형성한 후 평탄화하는 단계를 포함하여 이루어진다.The first embodiment of the method for forming a copper wiring of a semiconductor device according to the present invention comprises the steps of forming an interlayer insulating film on the lower copper wiring and forming a dual damascene pattern consisting of trenches and vias, the entire image including the dual damascene pattern Forming a copper diffusion preventing metal layer on the substrate; removing the copper diffusion preventing metal layer on the interlayer insulating layer and the copper diffusion preventing metal layer on the bottom of the via by directional etching; and removing the copper oxide film on the lower copper wiring surface exposed on the bottom of the via. And forming a seed copper layer on the whole by chemical vapor deposition and forming a copper interconnect in-situ inside the dual damascene pattern and then planarizing the copper interconnect.
또한, 본 발명에 따른 반도체 소자의 구리 배선 형성 방법의 제 2 실시예는 하부 구리 배선 상에 층간 절연막을 형성한 후 트렌치 및 비아로 이루어진 듀얼 다마신 패턴을 형성하는 단계, 듀얼 다마신 패턴을 포함한 전체 상에 구리 확산 방지 금속층을 형성하는 단계, 방향성 식각으로 상기 층간 절연막 상의 구리 확산 방지금속층 및 비아 저면의 구리 확산 방지 금속층을 제거하는 단계, 비아 저면에 노출된 상기 하부 구리 배선 표면의 구리 산화막을 제거하는 단계, 전체 상에 물리적 기상 증착법으로 글루 시드층을 형성하는 단계, 전체 상에 화학적 기상 증착법으로 시드 구리층을 형성하는 단계 및 듀얼 다마신 패턴 내부에 인-시투로 상부 구리 배선을 형성한 후 평탄화하는 단계를 포함하여 이루어진다.In addition, a second embodiment of the method for forming a copper wiring of a semiconductor device according to the present invention comprises the step of forming an interlayer insulating film on the lower copper wiring and forming a dual damascene pattern consisting of trenches and vias, including a dual damascene pattern Forming a copper diffusion preventing metal layer over the whole, removing the copper diffusion preventing metal layer on the interlayer insulating layer and the copper diffusion preventing metal layer on the bottom of the via by directional etching, and removing the copper oxide film on the lower copper wiring surface exposed on the bottom of the via. Forming a seed layer by physical vapor deposition on the whole, forming a seed copper layer by chemical vapor deposition on the whole, and forming an upper copper wiring in-situ inside the dual damascene pattern And then planarizing.
층간 절연막은 제 1 절연막, 식각 방지 절연막, 제 2 절연막 및 하드 마스크용 절연막을 순차적으로 형성하여 적층된 구조로 형성한다. 구리 확산 방지 금속층은 원자층 증착 화학 기상 증착 장비에서 10 내지 100Å의 두께로 형성하며, 방향성 식각은 Ar 가스 또는 Ar 및 N2혼합 가스를 식각 가스로 이용한다. 구리 산화물은 H2가스, H2+He 혼합가스, H2+Ar 혼합 가스 또는 H2+N2혼합 가스를 이용하여 제거하며, 방향성 식각 또는 구리 산화물 제거시 반도체 기판에 -20 내지 100V의 바이어스를 인가한다. 글루 구리층은 -50 내지 0℃의 온도 범위에서 20 내지 100Å의 두께로 형성한다.The interlayer insulating film is formed in a stacked structure by sequentially forming a first insulating film, an etch preventing insulating film, a second insulating film, and an insulating film for a hard mask. The copper diffusion preventing metal layer is formed to a thickness of 10 to 100 kPa in the atomic layer deposition chemical vapor deposition equipment, the directional etching is used as the etching gas Ar gas or Ar and N 2 mixed gas. Copper oxide is removed using H 2 gas, H 2 + He mixed gas, H 2 + Ar mixed gas, or H 2 + N 2 mixed gas, and bias of -20 to 100V is applied to the semiconductor substrate during directional etching or copper oxide removal. Apply. The glue copper layer is formed to a thickness of 20 to 100 kPa in a temperature range of -50 to 0 ° C.
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 더욱 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail.
도 1a 내지 도 1d는 본 발명에 따른 반도체 소자의 구리 배선 형성 방법을 설명하기 위하여 순차적으로 도시한 소자의 단면도이다.1A to 1D are cross-sectional views of devices sequentially shown to explain a method of forming a copper wiring of a semiconductor device according to the present invention.
도 1a를 참조하면, 반도체 소자를 형성하기 위한 여러 요소가 형성된 반도체기판(1) 상의 소정 영역에 하부 구리 배선(2)을 형성한다. 하부 구리 배선(2)을 포함한 전체 상에 구리 확산 방지막(3) 및 층간 절연막(30)을 순차적으로 형성하고, 하부 구리 배선(2)과 층간 절연막(40) 상부에 형성될 상부 요소와의 수직 배선을 위하여 트랜치와 비아로 이루어진 듀얼 다마신 패턴을 형성한다.Referring to FIG. 1A, a lower copper wiring 2 is formed in a predetermined region on a semiconductor substrate 1 on which various elements for forming a semiconductor element are formed. The copper diffusion barrier film 3 and the interlayer insulating film 30 are sequentially formed on the whole including the lower copper wiring 2, and perpendicular to the lower copper wiring 2 and the upper element to be formed on the interlayer insulating film 40. A dual damascene pattern of trenches and vias is formed for the wiring.
층간 절연막(40)은 제 1 절연막(4), 식각 방지 절연막(5), 제 2 절연막(6) 및 하드 마스크용 절연막(7)을 순차적으로 형성하여 적층된 구조로 형성한다. 트랜치는 하드 마스크용 절연막(7)을 이용한 식각 공정으로 제 2 절연막(6)을 식각하여 형성한다. 이때, 제 1 절연막(4)은 식각 방지 절연막(5)에 의하여 제 2 절연막(6) 식각 공정시 식각되지 않는다. 다시 비아 마스크를 이용한 식각 공정으로 식각 방지 절연막(5), 제 1 절연막(4) 및 구리 확산 방지막(3)을 식각하여 하부 구리 배선(2)의 소정 영역이 노출되도록 한다.The interlayer insulating film 40 is formed in a stacked structure by sequentially forming the first insulating film 4, the etch preventing insulating film 5, the second insulating film 6, and the hard mask insulating film 7. The trench is formed by etching the second insulating film 6 by an etching process using the hard mask insulating film 7. At this time, the first insulating film 4 is not etched by the etching prevention insulating film 5 during the etching process of the second insulating film 6. The etching prevention insulating film 5, the first insulating film 4, and the copper diffusion preventing film 3 are etched by an etching process using a via mask to expose a predetermined region of the lower copper wiring 2.
식각 방지 절연막(5)은 SiN 또는 SiC 절연막층을 이용하여 형성한다.The etch stop insulating film 5 is formed using a SiN or SiC insulating film layer.
도 1b를 참조하면, 전체 상에 구리 확산 방지 금속층(8)을 형성한다.Referring to FIG. 1B, the copper diffusion preventing metal layer 8 is formed on the whole.
구리 확산 방지 금속층(8)은 원자층 증착 화학 기상 증착 장비에서 10 내지 100Å의 두께로 형성한다.The copper diffusion preventing metal layer 8 is formed to a thickness of 10 to 100 kPa in atomic layer deposition chemical vapor deposition equipment.
도 1c를 참조하면, 층간 절연막(40) 상부와 하부 구리 배선 상의 구리 확산 방지 금속층(8)을 제거한다. 이후 하부 구리 배선 표면의 구리 산화막(도시되지 않음)도 제거한다.Referring to FIG. 1C, the copper diffusion preventing metal layer 8 on the upper and lower copper interconnections of the interlayer insulating film 40 is removed. The copper oxide film (not shown) of the lower copper wiring surface is then also removed.
구리 확산 방지 금속층(8) 및 구리 산화막의 제거는 구리 금속 시드층 증착 장비의 식각 챔버에서 불활성 가스와 환원성 가스의 혼합 가스를 이용하여 실시한다.Removal of the copper diffusion preventing metal layer 8 and the copper oxide film is performed using a mixed gas of an inert gas and a reducing gas in an etching chamber of the copper metal seed layer deposition equipment.
구리 확산 방지 금속층(8)을 제거하는 식각 공정은 방향성 식각법으로 실시하여 트랜치 및 비아 측벽에 형성된 구리 확산 방지 금속층(8)이 식각되지 않도록 하며, 이때 식각 가스로는 Ar 가스 또는 Ar 및 N2혼합 가스를 식각 가스로 이용한다. 이후, 구리 산화물을 제거하는 공정은 H2가스, H2+He 혼합가스, H2+Ar 혼합 가스 또는 H2+N2혼합 가스를 이용하여 실시한다.The etching process of removing the copper diffusion preventing metal layer 8 is performed by a directional etching method so that the copper diffusion preventing metal layer 8 formed on the trench and via sidewalls is not etched, and the etching gas is mixed with Ar gas or Ar and N 2. Gas is used as an etching gas. Thereafter, the step of removing the copper oxide is performed using H 2 gas, H 2 + He mixed gas, H 2 + Ar mixed gas, or H 2 + N 2 mixed gas.
구리 확산 방지 금속층(8)을 제거하는 식각 공정과 구리 산화물을 제거하는 공정을 실시할 때 반도체 기판에는 -20 내지 100V의 바이어스를 인가하여 공정이 원할하게 진행될 수 있도록 한다.When performing the etching process of removing the copper diffusion preventing metal layer 8 and the process of removing copper oxide, a bias of -20 to 100V is applied to the semiconductor substrate so that the process can proceed smoothly.
도 1d를 참조하면, 비아에 의해 노출된 하부 구리 배선(2)을 포함한 전체 상에 상부 구리 배선용 구리층을 인-시투로 형성한 후 화학적 기계적 연마를 실시하여 층간 절연막(40)의 표면이 노출될 때까지 구리층을 제거하고, 평탄화하여 상부 구리 배선(9)을 형성한다.Referring to FIG. 1D, the upper copper wiring copper layer is formed in-situ on the whole including the lower copper wiring 2 exposed by the via, and then chemical mechanical polishing is performed to expose the surface of the interlayer insulating film 40. The copper layer is removed and planarized until the upper copper wiring 9 is formed.
상부 구리 배선(9)을 형성하는 제 1 실시예로는 상부 구리 배선(9)을 형성하기 위한 구리층을 전기 화학적 구리 증착법으로 형성한다. 전기 화학적 구리 증착법으로 구리층을 증착하기 위해서는 먼저 구리 금속 시드층 증착 장비에서 인-시투로 시드 구리층(도시되지 않음)을 형성한 후 구리층을 증착한다.In the first embodiment of forming the upper copper wiring 9, a copper layer for forming the upper copper wiring 9 is formed by electrochemical copper deposition. In order to deposit a copper layer by electrochemical copper deposition, an in-situ seed copper layer (not shown) is first formed in a copper metal seed layer deposition apparatus, and then a copper layer is deposited.
상부 구리 배선(9)을 형성하는 제 2 실시예로는 제 1 실시예에서의 구리 시드층을 증착하기 전에 층간 절연막(40)과 구리 확산 방지 금속층(8)에 구리 시드층이 잘 증착될 수 있도록 글루(Glue) 구리층(도시되지 않음)을 물리 기상 증착법으로 증착한 후 화학적 기상 증착법으로 구리 시드층을 증착한다.In the second embodiment of forming the upper copper wiring 9, the copper seed layer may be well deposited on the interlayer insulating film 40 and the copper diffusion preventing metal layer 8 before the copper seed layer in the first embodiment is deposited. In order to deposit a glue copper layer (not shown) by physical vapor deposition method, a copper seed layer is deposited by chemical vapor deposition.
상기의 공정으로 하부 구리 배선과 상부 구리 배선이 직접 접촉하면서 구리 확산 방지 금속층에 의한 배선의 저항 성분이 증가하는 것을 방지한다. 또한, 상부 구리 배선이 하부 구리 배선과의 콘택 플러그 역할까지 함으로써 콘택 플러그를 형성하기 위한 공정 단계를 줄여 공정을 단순하게 하면서 콘택 플러그에 의한 저항 성분이 증가하는 것도 방지할 수 있다.The above process prevents the resistance component of the wiring by the copper diffusion preventing metal layer from increasing while the lower copper wiring and the upper copper wiring are in direct contact. In addition, since the upper copper wiring also serves as a contact plug with the lower copper wiring, the process step for forming the contact plug can be reduced, thereby simplifying the process and preventing an increase in the resistance component caused by the contact plug.
상술한 바와 같이, 본 발명은 하부 구리 배선과 상부 구리 배선의 접촉 저항을 줄임으로써 소자의 전기적 특성을 향상시키는 효과가 있다.As described above, the present invention has the effect of improving the electrical characteristics of the device by reducing the contact resistance of the lower copper wiring and the upper copper wiring.
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KR100896460B1 (en) * | 2002-12-30 | 2009-05-14 | 주식회사 하이닉스반도체 | Method for forming copper interconnection of semiconductor device |
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JPH11340226A (en) * | 1998-05-22 | 1999-12-10 | Sony Corp | Manufacture of semiconductor device |
KR20000043063A (en) * | 1998-12-28 | 2000-07-15 | 김영환 | Metalization of semiconductor device |
KR20000044851A (en) * | 1998-12-30 | 2000-07-15 | 김영환 | Method for forming copper alloy wiring of semiconductor device |
KR20000043057A (en) * | 1998-12-28 | 2000-07-15 | 김영환 | Method for making metal wiring of semiconductor device |
KR20000043910A (en) * | 1998-12-29 | 2000-07-15 | 김영환 | Method for forming copper line of semiconductor device |
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Publication number | Priority date | Publication date | Assignee | Title |
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JPH11340226A (en) * | 1998-05-22 | 1999-12-10 | Sony Corp | Manufacture of semiconductor device |
KR20000043063A (en) * | 1998-12-28 | 2000-07-15 | 김영환 | Metalization of semiconductor device |
KR20000043057A (en) * | 1998-12-28 | 2000-07-15 | 김영환 | Method for making metal wiring of semiconductor device |
KR20000043910A (en) * | 1998-12-29 | 2000-07-15 | 김영환 | Method for forming copper line of semiconductor device |
KR20000044851A (en) * | 1998-12-30 | 2000-07-15 | 김영환 | Method for forming copper alloy wiring of semiconductor device |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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KR100896460B1 (en) * | 2002-12-30 | 2009-05-14 | 주식회사 하이닉스반도체 | Method for forming copper interconnection of semiconductor device |
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