KR20040059736A - Method for manufacturing lines of semiconductor device - Google Patents
Method for manufacturing lines of semiconductor device Download PDFInfo
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- KR20040059736A KR20040059736A KR1020020086238A KR20020086238A KR20040059736A KR 20040059736 A KR20040059736 A KR 20040059736A KR 1020020086238 A KR1020020086238 A KR 1020020086238A KR 20020086238 A KR20020086238 A KR 20020086238A KR 20040059736 A KR20040059736 A KR 20040059736A
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- South Korea
- Prior art keywords
- contact
- wiring
- interlayer insulating
- semiconductor device
- trench
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- 238000000034 method Methods 0.000 title claims description 13
- 239000011229 interlayer Substances 0.000 claims abstract description 28
- 238000005530 etching Methods 0.000 claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims abstract description 10
- 239000002184 metal Substances 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 239000010410 layer Substances 0.000 claims abstract description 8
- 230000004888 barrier function Effects 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- -1 Boro Phosphorus Chemical compound 0.000 description 1
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로서, 특히 고집적 반도체 소자의 배선 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a wiring of a highly integrated semiconductor device.
반도체 소자의 고집적화가 진행됨에 따라 소자의 크기를 축소시키는 것 이외에도 소자의 성능을 향상시키기 위한 연구가 진행되고 있다. 현재 대부분의 반도체장치의 배선 공정은 단일 배선만으로는 고집적 소자의 동작시 요구되는 신호를 신속하게 전달하는데 어려움이 있기 때문에 이를 극복하기 위하여 다층 배선구조를 채택하고 있다.As the integration of semiconductor devices increases, research has been conducted to improve device performance in addition to reducing the size of the device. Currently, the wiring process of most semiconductor devices employs a multi-layered wiring structure in order to overcome this problem because it is difficult to quickly transmit a signal required for the operation of the highly integrated device using only a single wiring.
다층 배선 구조에서는 상부 배선과 하부 배선을 수직으로 연결하기 위하여 콘택이 필요하다. 그런데, 이러한 콘택은 반도체 소자가 집적화되어 감에 따라 그 면적또한 미세화되어 가고 있다.In the multilayer wiring structure, a contact is required to vertically connect the upper wiring and the lower wiring. By the way, as the semiconductor devices are integrated, the area of these contacts is also becoming smaller.
이와 같은 콘택 제조 공정시 상부 배선 또는 하부 배선과의 오버레이 마진(overlay margin)이 줄어들어 이들 배선에 대해 콘택이 미스 얼라인(mis-align)될 경우 반도체 소자의 배선이 연결되지 않게 되거나 콘택 면적이 줄어들게 되어 결국, 반도체 소자의 수율 및 신뢰성을 저하시킨다.In this contact manufacturing process, the overlay margin with the upper wiring or the lower wiring is reduced so that if the contact is misaligned with the wiring, the wiring of the semiconductor device is not connected or the contact area is reduced. As a result, the yield and reliability of the semiconductor element are lowered.
본 발명의 목적은 상기와 같은 종래 기술의 문제점을 해결하기 위하여 층간절연막에 콘택홀을 형성하고 콘택홀에 콘택을 형성한 후에 층간 절연막을 다마신 식각하여 콘택의 상부와 그 측면 일부가 노출되는 상부 배선용 트렌치를 형성한 후에 상부 배선을 형성함으로써 콘택과 상부 배선의 미스-얼라인을 미연에 방지하고 콘택 면적을 증가시켜 반도체 소자의 수율 및 신뢰성을 향상시킬 수 있는 반도체 소자의 배선 제조 방법을 제공하는데 있다.An object of the present invention is to form a contact hole in the interlayer insulating film and to form a contact in the contact hole in order to solve the problems of the prior art as described above by damaging the interlayer insulating film to the upper portion of the contact and the side portion of the side exposed By forming the upper wiring after forming the wiring trench to provide a wiring manufacturing method of the semiconductor device that can prevent the misalignment of the contact and the upper wiring in advance, and increase the contact area to improve the yield and reliability of the semiconductor device. have.
상기 목적을 달성하기 위하여 본 발명은 하부 배선, 상부 배선 사이를 수직으로 연결하는 콘택 전극을 갖는 반도체 소자의 제조 방법에 있어서, 반도체 기판의 하부 구조물에 하부 배선을 형성하는 단계와, 하부 배선이 있는 기판 전면에 층간 절연막을 형성하는 단계와, 층간 절연막내에 하부 배선의 일부가 드러나는 콘택홀을 형성하는 단계와, 콘택홀내에 도전막을 매립하여 콘택을 형성하는 단계와, 층간 절연막 표면에서부터 일정 두께로 식각하여 콘택의 상부 및 측면이 노출되면서 상부 배선 영역을 정의하는 트렌치를 형성하는 단계와, 층간 절연막의 트렌치에 도전막을 매립하여 콘택의 상부 및 측면을 감싸는 상부 배선을 형성하는 단계를 포함한다.In order to achieve the above object, the present invention provides a method of manufacturing a semiconductor device having a contact electrode vertically connected between the lower wiring, the upper wiring, the step of forming a lower wiring on the lower structure of the semiconductor substrate, Forming an interlayer insulating film on the entire surface of the substrate, forming a contact hole in which a part of the lower wiring is exposed in the interlayer insulating film, forming a contact by filling a conductive film in the contact hole, and etching a predetermined thickness from the interlayer insulating film surface Forming a trench defining an upper wiring region while the upper and side surfaces of the contact are exposed; and forming an upper wiring covering the upper and side surfaces of the contact by filling a conductive film in the trench of the interlayer insulating layer.
도 1은 본 발명에 따른 반도체 소자의 배선 제조 공정중에서 하부 배선 제조 공정을 설명하기 위한 수직 단면도,1 is a vertical cross-sectional view illustrating a lower wiring manufacturing process in a wiring manufacturing process of a semiconductor device according to the present invention;
도 2는 본 발명에 따른 반도체 소자의 배선 제조 공정중에서 콘택홀 제조 공정을 설명하기 위한 수직 단면도,2 is a vertical cross-sectional view for explaining a contact hole manufacturing process in a wiring manufacturing process of a semiconductor device according to the present invention;
도 3은 본 발명에 따른 반도체 소자의 배선 제조 공정중에서 콘택 제조 공정을 설명하기 위한 수직 단면도,3 is a vertical cross-sectional view for explaining a contact manufacturing process in a wiring manufacturing process of a semiconductor device according to the present invention;
도 4는 본 발명에 따른 반도체 소자의 배선 제조 공정중에서 상부 배선용 트렌치 제조 공정을 설명하기 위한 수직 단면도,Figure 4 is a vertical cross-sectional view for explaining the trench manufacturing process for the upper wiring in the wiring manufacturing process of the semiconductor device according to the present invention,
도 5는 본 발명에 따른 반도체 소자의 배선 제조 공정중에서 상부 배선 제조공정을 설명하기 위한 수직 단면도.5 is a vertical cross-sectional view for explaining the upper wiring manufacturing process in the wiring manufacturing process of the semiconductor device according to the present invention.
< 도면의 주요부분에 대한 부호의 설명＞<Description of the code | symbol about the principal part of drawing>
10 : 반도체 기판 12 : 하부 배선10 semiconductor substrate 12 lower wiring
14 : 층간 절연막 16 : 콘택홀용 포토레지스트 패턴14 interlayer insulating film 16 photoresist pattern for contact hole
18 : 콘택홀 20 : 콘택18: contact hole 20: contact
22 : 상부 배선용 포토레지스트 패턴22: photoresist pattern for upper wiring
24 : 상부 배선용 트랜치 26 : 상부 배선24: trench for upper wiring 26: upper wiring
이하 첨부된 도면들을 참조하여 본 발명의 바람직한 실시예에 대해 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.
도 1은 본 발명에 따른 반도체 소자의 배선 제조 공정중에서 하부 배선 제조 공정을 설명하기 위한 수직 단면도이다.1 is a vertical cross-sectional view for explaining a lower wiring manufacturing process in a wiring manufacturing process of a semiconductor device according to the present invention.
도 1을 참조하면, 본 발명은 반도체 기판으로서 실리콘 기판(10)의 하부 구조물에 도전막으로서 금속(예컨대, 알루미늄)을 증착하고 이를 패터닝하여 하부 배선(12)을 형성한다.Referring to FIG. 1, according to the present invention, a lower wiring 12 is formed by depositing and patterning a metal (eg, aluminum) as a conductive film on a lower structure of a silicon substrate 10 as a semiconductor substrate.
도 2는 본 발명에 따른 반도체 소자의 배선 제조 공정중에서 콘택홀 제조 공정을 설명하기 위한 수직 단면도이다.2 is a vertical cross-sectional view for explaining a contact hole manufacturing process in a wiring manufacturing process of a semiconductor device according to the present invention.
도 2를 참조하면, 본 발명은 하부 배선(12)이 있는 기판 전면에 TEOS(thetraethyle orthosilicate) 또는 BPSG(Boro Phosphorus Silicate Glass) 등으로 층간 절연막(14)을 증착한다. 그리고 전면 식각(etch back) 또는 화학적기계적 연마(chemical mechanical polishing: 이하 CMP라 함) 공정으로 층간 절연막(14) 표면을 평탄화한다.Referring to FIG. 2, the present invention deposits an interlayer insulating film 14 by using tetraethyle orthosilicate (TEOS) or Boro Phosphorus Silicate Glass (BPSG) on the entire surface of the substrate having the lower wiring 12. The surface of the interlayer insulating layer 14 is planarized by an etch back or chemical mechanical polishing (CMP) process.
포토리소그래피 공정을 진행하여 평탄화된 층간 절연막(14) 상부에 콘택홀 영역을 정의하는 포토레지스트 패턴(16)을 형성한다. 그리고 식각 공정을 진행하여 포토레지스트 패턴(16)에 의해 드러난 층간 절연막(14)을 식각하여 하부 배선(12) 표면이 드러나는 콘택홀(18)을 형성한 후에 포토레지스트 패턴(16)을 제거한다.The photolithography process is performed to form a photoresist pattern 16 defining a contact hole region on the planarized interlayer insulating layer 14. After the etching process, the interlayer insulating layer 14 exposed by the photoresist pattern 16 is etched to form the contact hole 18 exposing the surface of the lower wiring 12, and then the photoresist pattern 16 is removed.
도 3은 본 발명에 따른 반도체 소자의 배선 제조 공정중에서 콘택 제조 공정을 설명하기 위한 수직 단면도이다.3 is a vertical cross-sectional view for explaining a contact manufacturing process in a wiring manufacturing process of a semiconductor device according to the present invention.
도 3을 참조하면, 본 발명은 층간 절연막(14)의 콘택홀내에 도전막으로서 텅스텐을 매립하고 층간 절연막(14) 표면이 드러나도록 식각하여 층간 절연막(14) 상부의 텅스텐을 제거하여 콘택홀내에 하부 배선(12)과 수직으로 연결되는 콘택(20)을 형성한다. 이때 식각 공정은 전면 식각 또는 CMP 공정으로 진행한다.Referring to FIG. 3, the present invention embeds tungsten as a conductive film in the contact hole of the interlayer insulating film 14 and etches the exposed surface of the interlayer insulating film 14 to remove the tungsten on the interlayer insulating film 14 to remove the tungsten on the interlayer insulating film 14. A contact 20 is formed to be vertically connected to the lower wiring 12. At this time, the etching process is a front surface etching or a CMP process.
한편 도면에 도시하지는 않았지만, 콘택홀내에 도전막을 매립하여 콘택을 형성하기 전에, 티타늄(Ti)/질화티타늄(TiN) 등의 장벽 금속막(barrier metal)을 추가 형성한다.Although not shown in the drawings, a barrier metal film such as titanium (Ti) / titanium nitride (TiN) is additionally formed before the contact film is formed by filling the conductive film in the contact hole.
도 4는 본 발명에 따른 반도체 소자의 배선 제조 공정중에서 상부 배선용 트렌치 제조 공정을 설명하기 위한 수직 단면도이다.4 is a vertical cross-sectional view for explaining the trench manufacturing process for the upper wiring in the wiring manufacturing process of the semiconductor device according to the present invention.
도 4를 참조하면, 본 발명은 포토리소그래피 공정을 진행하여 콘택(20)이 형성된 층간 절연막(14) 상부에 상부 배선 영역을 정의하는 포토레지스트 패턴(22)을 형성하고, 다마신 식각(damascene etch) 공정으로 포토레지스트 패턴(22)에 의해 드러난 층간 절연막(14) 표면에서부터 일정 두께의 깊이로 식각하여 콘택(20)의 상부 및 측면이 노출되는 트렌치(24)를 형성한다.Referring to FIG. 4, the present invention proceeds through a photolithography process to form a photoresist pattern 22 defining an upper wiring region on an interlayer insulating layer 14 on which a contact 20 is formed, and to etch a damascene etch. A trench 24 is formed to expose the top and side surfaces of the contact 20 by etching a predetermined thickness from the surface of the interlayer insulating film 14 exposed by the photoresist pattern 22.
도 5는 본 발명에 따른 반도체 소자의 배선 제조 공정중에서 상부 배선 제조공정을 설명하기 위한 수직 단면도이다.5 is a vertical cross-sectional view for explaining the upper wiring manufacturing process in the wiring manufacturing process of the semiconductor device according to the present invention.
도 5를 참조하면, 본 발명은 층간 절연막(24)의 트렌치(24)에 도전막으로서 금속(예컨대, 알루미늄)을 매립하고 이를 전면 식각 또는 CMP 공정으로 평탄화하여 상부 배선(26)을 형성한다. 이때 상부 배선(26)은 다마신 식각 공정에 의해 콘택(20)의 상부 및 측면이 노출된 트렌치에 형성되기 때문에 콘택(20) 표면을 감싸는 형태로 수직으로 연결되기 때문에 콘택 면적이 증가되어 콘택 저항이 줄어들게 된다.Referring to FIG. 5, in the present invention, a metal (for example, aluminum) is embedded in the trench 24 of the interlayer insulating film 24, and the upper wiring 26 is formed by planarization of the metal (eg, aluminum) by planar etching or CMP. In this case, since the upper wiring 26 is formed in the trench in which the upper and side surfaces of the contact 20 are exposed by the damascene etching process, the upper wiring 26 is vertically connected to surround the surface of the contact 20 so that the contact area is increased and the contact resistance is increased. Will be reduced.
이상 설명한 바와 같이, 본 발명은 층간 절연막에 콘택홀을 형성하고 콘택홀에 콘택을 형성한 후에 층간 절연막을 다마신 식각하여 콘택의 상부와 그 측면 일부가 노출되는 상부 배선용 트렌치를 형성한 후에 상부 배선을 형성함으로써 콘택과 상부 배선의 미스-얼라인을 미연에 방지하는 효과가 있다.As described above, in the present invention, after forming a contact hole in the interlayer insulating film and forming a contact in the contact hole, the interlayer insulating film is etched and etched to form an upper wiring trench in which the upper portion of the contact and a portion of the side surface thereof are exposed. By forming the present invention, there is an effect of preventing miss-alignment between the contact and the upper wiring in advance.
또한 본 발명은 콘택과 상부 배선의 콘택 면적을 증가시켜 콘택 저항을 줄임으로써 반도체 소자의 수율 및 신뢰성을 향상시킬 수 있다.In addition, the present invention can improve the yield and reliability of the semiconductor device by reducing the contact resistance by increasing the contact area of the contact and the upper wiring.
한편, 본 발명은 상술한 실시예에 국한되는 것이 아니라 후술되는 청구범위에 기재된 본 발명의 기술적 사상과 범주내에서 당업자에 의해 여러 가지 변형이 가능하다.On the other hand, the present invention is not limited to the above-described embodiment, various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims to be described later.
Claims (4)
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| KR20070099972A (en) * | 2006-04-06 | 2007-10-10 | 주식회사 하이닉스반도체 | Method of forming a metal wire in a semiconductor device |
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| KR100539221B1 (en) * | 1999-09-03 | 2005-12-27 | 삼성전자주식회사 | Method of manufacturing electrical interconnection for semiconductor device |
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