KR20040058952A - Method of forming a metal wiring in a semiconductor device - Google Patents

Method of forming a metal wiring in a semiconductor device Download PDF

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Publication number
KR20040058952A
KR20040058952A KR1020020085472A KR20020085472A KR20040058952A KR 20040058952 A KR20040058952 A KR 20040058952A KR 1020020085472 A KR1020020085472 A KR 1020020085472A KR 20020085472 A KR20020085472 A KR 20020085472A KR 20040058952 A KR20040058952 A KR 20040058952A
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South Korea
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metal
metal wiring
forming
noble metal
semiconductor substrate
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KR1020020085472A
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Korean (ko)
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김시범
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주식회사 하이닉스반도체
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Priority to KR1020020085472A priority Critical patent/KR20040058952A/en
Publication of KR20040058952A publication Critical patent/KR20040058952A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures

Abstract

PURPOSE: A method for forming a metal line of a semiconductor device is provided to reduce a dielectric constant of an entire insulating layer and an error rate of the metal line due to electro migration by forming a capping layer having noble metal on the metal line. CONSTITUTION: A metal line(105) is formed on a semiconductor substrate(101). The semiconductor substrate including the metal line is dipped into a metal salt bath having a predetermined solution including noble metal salts. The noble metal is deposited only on an upper surface of the metal line of the semiconductor substrate by using a displacement plating method. A capping layer(106) is formed by depositing the noble metal on the upper surface of the metal line. The noble metal is formed with one of Pt, Pd, Ag, Au, Rh, Ru, and Ir.

Description

반도체 소자의 금속 배선 형성 방법{Method of forming a metal wiring in a semiconductor device}Method of forming a metal wiring in a semiconductor device

본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 특히, 트렌치에 형성된 금속 배선 상부에 금속 배선과의 계면 특성이 우수한 금속 캡핑층(Capping layer)을 형성할 수 있는 반도체 소자의 금속 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal wiring of a semiconductor device. In particular, a method for forming a metal wiring of a semiconductor device capable of forming a metal capping layer having excellent interfacial characteristics with a metal wiring on a metal wiring formed in a trench. It is about.

반도체 소자를 제조하는 과정에서 반도체 기판의 상부에는 다층의 금속 배선이 형성되는데, 최근 들어 구리를 이용하여 금속 배선을 형성하고 있다. 한편, 금속 배선은 알루미늄이나 기타 금속으로도 형성할 수 있지만, 특히 구리로 금속 배선을 형성하는 경우에는 다마신 공정과 전기 도금법으로 금속 배선을 형성한다. 좀 더 구체적으로 설명하면 다음과 같다.In the process of manufacturing a semiconductor device, a multilayer metal wiring is formed on an upper portion of a semiconductor substrate. Recently, metal wiring is formed using copper. On the other hand, although the metal wiring can be formed also from aluminum or other metal, especially when forming metal wiring from copper, metal wiring is formed by a damascene process and an electroplating method. More specifically, it is as follows.

먼저, 다마신 공정으로 층간 절연막에 비아 및 트렌치를 형성하고, 후속 공정에서 형성될 금속 배선의 금속 성분이 층간 절연막으로 침투하는 것을 방지하기 위하여 층간 절연막의 표면에 장벽 금속층을 형성한 후, 계속해서 구리 금속 시드층을 형성하고 전기 도금법으로 비아 및 트렌치를 구리로 매립하여 금속 배선을 형성한다. 금속 배선이 형성된 후에는, 추가로 화학적 기계적 연마 공정을 실시하여 비아 및 트렌치 이외의 층간 절연막 상부에 형성된 금속막을 제거한다. 이어서, 상부에 다시 금속 배선을 형성하는 경우, SiN 도는 SiC와 같은 확산 방지 절연막을 형성한 후 후속 공정을 진행한다.First, vias and trenches are formed in the interlayer insulating film by the damascene process, and a barrier metal layer is formed on the surface of the interlayer insulating film in order to prevent metal components of the metal wiring to be formed in the subsequent process from penetrating into the interlayer insulating film. A copper metal seed layer is formed and vias and trenches are filled with copper by electroplating to form metal interconnects. After the metal wiring is formed, a chemical mechanical polishing process is further performed to remove the metal film formed on the interlayer insulating film other than the vias and the trenches. Subsequently, in the case of forming the metal wiring on the upper portion again, a diffusion barrier insulating film such as SiN or SiC is formed, and then a subsequent process is performed.

상기에서, 통상적인 금속 배선(특히, 구리 금속 배선) 형성 공정에서는 다음과 같은 두 가지의 문제점이 있다.In the above, the conventional metal wiring (particularly, copper metal wiring) forming process has the following two problems.

첫 번째는, 재료학적으로 볼때, 금속(또는 구리)과 인접한 SiN이나 SiC의 계면이 치밀하게 형성되기 어려우며, 이로 인해 금속 배선의 전자 이동(Electro migration)에 의한 배선 불량 발생에 취약한 문제점이 발생될 수 있다.First, in terms of material, it is difficult to form a dense interface between the metal (or copper) and the adjacent SiN or SiC, which causes a problem that is vulnerable to wiring defects caused by electromigration of metal wiring. Can be.

두 번째는, SiN이나 SiC는 SiO2절연막이나 저유전(Low-k)막과 비교해볼 때 유전율이 각각 7, 4.5 정도로 크기 때문에 전체 절연막의 겉보기 유전율인 유효 유전 상수(Effective dielectric constant)를 증가시키게 되는데, 이는 절연막의 저유전율화 구현 측면에서 불리한 요소로 작용하는 문제점이 있다.Secondly, since SiN and SiC have high dielectric constants of about 7, 4.5, respectively, compared to SiO 2 insulating films or low-k films, they increase the effective dielectric constant, the apparent dielectric constant of the entire insulating film. This is a disadvantage that acts as a disadvantage in terms of implementing a low dielectric constant of the insulating film.

따라서, 본 발명은 상기의 문제점을 해결하기 위하여 트렌치에 금속 배선을 형성한 후 귀금속(Noble metal)의 금속염 전해조(Bath)에 반도체 기판을 장입하여 치환 도금(Displacement plating)법으로 귀금속을 금속 배선 상부에만 증착시키고, 이를 통해 귀금속으로 이루어진 캡핑층을 금속 배선 상부에 형성함으로써, SiC나 SiN등의 구리확산 방지 절연막의 사용이 필요치 않아 절연막 전체의 유전율을 감소시키면서 금속 배선의 전자 이동(Electro migration)에 의한 배선 불량 발생 문제를 억제하고 공정 단계를 간소화하여 공정의 신뢰성 및 소자의 전기적 특성을 향상시킬 수 있는 반도체 소자의 금속 배선 형성 방법을 제공하는데 그 목적이 있다.Accordingly, in order to solve the above problems, the present invention forms a metal wiring in a trench, inserts a semiconductor substrate into a metal salt electrolytic cell of a noble metal, and replaces the precious metal with a metal plating by a displacement plating method. By depositing only on the metal wiring, a capping layer made of a noble metal is formed on the upper portion of the metal wiring, thereby eliminating the need for a copper diffusion preventing insulating film such as SiC or SiN. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a metal wiring of a semiconductor device, which can suppress a problem of occurrence of wiring defects and simplify a process step to improve process reliability and device electrical characteristics.

도 1a 내지 도 1d는 본 발명의 실시예에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 소자의 단면도들이다.1A through 1D are cross-sectional views of devices for describing a method for forming metal wires in a semiconductor device according to an embodiment of the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

101 : 반도체 기판 102 : 층간 절연막101 semiconductor substrate 102 interlayer insulating film

103 : 듀얼 다마신 패턴 104 : 장벽 금속층103: dual damascene pattern 104: barrier metal layer

105 : 금속 배선 106 : 캡핑층105 metal wiring 106 capping layer

본 발명의 실시예에 따른 반도체 소자의 금속 배선 형성 방법은 금속 배선이 형성된 반도체 기판이 제공되는 단계와, 귀금속 금속염을 포함한 용액이 담긴 전해조에 반도체 기판을 장입하는 단계 및 치환 도금법으로 귀금속을 금속 배선 상부에만 귀금속을 증착시켜 귀금속으로 이루어진 캡핑층을 형성하는 단계를 포함한다.In the method of forming a metal wiring of a semiconductor device according to an embodiment of the present invention, a metal wiring is formed by providing a semiconductor substrate on which metal wiring is formed, inserting the semiconductor substrate into an electrolytic cell containing a solution containing a noble metal salt, and metal wiring using the substitution plating method. Depositing a noble metal only on the top to form a capping layer made of the noble metal.

상기에서, 귀금속은 Pt, Pd, Ag, Au, Rh, Ru 또는 Ir이다.In the above, the noble metal is Pt, Pd, Ag, Au, Rh, Ru or Ir.

한편, 전해조에 담긴 용액은 귀금속 이온을 포함하는 황산염, 염화물 용액, 환원 촉진제 및 기타 유기 첨가물 조절제를 포함한다. 또한, 용액에는 반응 조절을 위하여 HCOOH의 환원제와 비이상 성장을 조절하기 위하여 BTA(Benzotriazole)을 더 혼합할 수 있다.On the other hand, the solution contained in the electrolyzer includes sulfates, chloride solutions, reduction promoters and other organic additive control agents containing noble metal ions. In addition, the solution may be further mixed with BTA (Benzotriazole) to control the abnormal growth and the reducing agent of HCOOH for the reaction control.

이러한, 캡핑층의 두께는 반도체 기판의 장입 시간에 따라 조절할 수 있다.The thickness of the capping layer may be adjusted according to the charging time of the semiconductor substrate.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 설명하기로 한다. 그러나, 본 발명은 이하에서 개시되는 실시예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 수 있으며, 단지 본 실시예는 본 발명의 개시가 완전하도록 하며 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이다. 한편, 도면상에서 동일 부호는 동일한 요소를 지칭한다.Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be embodied in various different forms, and only the embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information. In the drawings, like reference numerals refer to like elements.

도 1a 내지 도 1d는 본 발명의 실시예에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 소자의 단면도들이다.1A through 1D are cross-sectional views of devices for describing a method for forming metal wires in a semiconductor device according to an embodiment of the present invention.

도 1a를 참조하면, 반도체 소자를 형성하기 위하여 트랜지스터나 플래시 메모리 셀과 같은 여러 요소(도시되지 않음)가 형성된 반도체 기판(101) 상부에 층간 절연막(102)을 형성한다. 이후, 하부의 접합 영역(도시되지 않음)이 노출되도록 듀얼 다마신(Dual damascene) 공정으로 층간 절연막(102)의 소정 영역에 비아홀을 형성하고, 후속 공정에서 금속 배선이 형성될 영역에는 트렌치를 형성하여 비아홀과트렌치로 이루어진 듀얼 다마신 패턴(103)을 형성한다.Referring to FIG. 1A, an interlayer insulating layer 102 is formed on a semiconductor substrate 101 on which various elements (not shown), such as a transistor or a flash memory cell, are formed to form a semiconductor device. Subsequently, a via hole is formed in a predetermined region of the interlayer insulating layer 102 by a dual damascene process to expose a lower junction region (not shown), and a trench is formed in a region where metal wiring is to be formed in a subsequent process. The dual damascene pattern 103 formed of via holes and trenches is formed.

도 1b를 참조하면, 후속 공정에서 형성될 금속 배선의 금속 성분이 층간 절연막(102)으로 침투되는 것을 방지하기 위하여 듀얼 다마신 패턴(103)의 측벽 및 저면에 장벽 금속층(104)을 형성한다.Referring to FIG. 1B, a barrier metal layer 104 is formed on sidewalls and bottom surfaces of the dual damascene pattern 103 to prevent the metal component of the metal wiring to be formed in the subsequent process from penetrating into the interlayer insulating film 102.

도 1c를 참조하면, 듀얼 다마신 패턴(103)을 금속 물질로 매립하여 금속 배선(105)을 형성한다. 금속 배선(105)을 구리로 형성하는 경우에는 듀얼 다마신 패턴(103)의 저면에 시드층을 형성하고 전기 도금법으로 듀얼 다마신 패턴(103)을 구리로 매립한 후에, 화학적 기계적 연마 공정으로 층간 절연막(102) 상부에 증착된 구리막을 제거하는 방법으로 구리 금속 배선을 형성한다. 이는, 구리를 이용한 금속 배선 형성 공정에만 사용되는 방법이 아니라, 귀금속을 사용하거나 다른 금속을 사용하여 금속 배선을 형성하는 경우에도 적용될 수 있다.Referring to FIG. 1C, the dual damascene pattern 103 is embedded with a metal material to form a metal wiring 105. In the case where the metal wiring 105 is formed of copper, a seed layer is formed on the bottom of the dual damascene pattern 103 and the dual damascene pattern 103 is embedded with copper by electroplating, and then the interlayer is formed by chemical mechanical polishing. Copper metal wirings are formed by removing the copper film deposited on the insulating film 102. This can be applied not only to the method of forming a metal wiring using copper, but also to a case of forming a metal wiring using a noble metal or using another metal.

도 1d를 참조하면, 금속 배선(105)이 형성된 반도체 기판(101)을 귀금속(Noble metal)의 금속염을 포함한 용액이 담긴 전해조(Bath)에 장입하여 치환 도금(Displacement plating)법으로 귀금속을 금속 배선(105) 상부에만 증착시키고, 이를 통해 귀금속으로 이루어진 캡핑층(106)을 금속 배선(105) 상부에 형성한다. 이때, 반도체 기판(101)을 Pt, Pd, Ag, Au, Rh, Ru 또는 Ir 금속염 전해조에 장입하여 Pt, Pd, Ag, Au, Rh, Ru 또는 Ir을 금속 배선(105) 상부에 증착할 수 있다.Referring to FIG. 1D, the semiconductor substrate 101 on which the metal wiring 105 is formed is inserted into an electrolytic bath containing a solution containing a metal salt of a noble metal, and the precious metal is wired by a displacement plating method. (105) is deposited only on the upper portion, thereby forming a capping layer 106 made of a noble metal on the upper portion of the metal wiring 105. At this time, the semiconductor substrate 101 may be charged into a Pt, Pd, Ag, Au, Rh, Ru, or Ir metal salt electrolytic cell to deposit Pt, Pd, Ag, Au, Rh, Ru, or Ir on the metal wiring 105. have.

구체적으로 예를 들어, 구리 금속 배선이 형성된 반도체 기판(101)을 Pt 금속염 전해조에 장입하면 하기의 화학식 1에 기재된 화학 반응식과 같은 화학 반응이 발생하여 구리 금속 배선의 상부에만 금속층이 증착된다.Specifically, for example, when the semiconductor substrate 101 on which the copper metal wiring is formed is charged into a Pt metal salt electrolytic cell, a chemical reaction such as the chemical formula shown in Formula 1 below occurs, and the metal layer is deposited only on the upper portion of the copper metal wiring.

Cu + Pt2++ 환원제(Reducing agent) ====> Cu2++ PtCu + Pt 2+ + Reducing agent ====> Cu 2+ + Pt

즉, Pt 이온을 포함하는 황산염(Sulfate), 염화물(Chloride) 용액, 환원 촉진제 및 기타 유기 첨가물 조절제를 포함하는 용액 내에 구리 금속 배선이 형성된 반도체 기판을 장입하면, Pt 금속은 Cu에 비하여 귀금속(Noble metal)이기 때문에 Cu는 산화되어 이온 상태로 녹아나오고 Pt 이온은 환원되어 Pt 금속이 구리 금속 배선 상부에만 증착된다. 이때, 반도체 기판이 장입되는 용액에는 반응 조절을 위하여 HCOOH 등의 환원제와 비이상 성장을 조절하기 위하여 BTA(Benzotriazole)을 혼합할 수 있다.That is, when a semiconductor substrate having copper metal wiring is formed in a solution containing sulfate, chloride solution, reduction accelerator, and other organic additive control agent containing Pt ions, Pt metal is noble than Cu. metal, Cu is oxidized and melted in an ionic state, and Pt ions are reduced so that Pt metal is deposited only on the copper metal wiring. In this case, the solution loaded with the semiconductor substrate may be mixed with a reducing agent such as HCOOH and BTA (Benzotriazole) to control the abnormal growth to control the reaction.

한편, 상기와 같이, 치환 도금법에 의해 형성되는 캡핑층(106)의 두께는 반도체 기판(101)의 장입 시간에 따라 조절할 수 있으며, 바람직하게는 10 내지 200??의 두께로 형성한다.On the other hand, as described above, the thickness of the capping layer 106 formed by the substitution plating method can be adjusted according to the charging time of the semiconductor substrate 101, preferably formed in a thickness of 10 to 200 ??.

이후, 도면에는 도시되어 있지 않지만, 상부에 다시 금속 배선을 형성하는 경우, 상부 층간 절연막을 형성하고 층간 절연막에 듀얼 다마신 패턴을 형성한 후 상기의 공정을 반복 실시하여 상부 금속 배선을 형성한다.Subsequently, although not shown in the drawing, when the metal wiring is again formed on the upper portion, the upper interlayer insulating film is formed, the dual damascene pattern is formed on the interlayer insulating film, and the above process is repeated to form the upper metal wiring.

상술한 바와 같이, 본 발명은 금속 배선이 형성된 반도체 기판을 귀금속(Noble metal)의 금속염 전해조(Bath)에 장입하여 치환 도금(Displacement plating)법으로 귀금속을 금속 배선 상부에만 증착시키고, 이를 통해 귀금속으로 이루어진 캡핑층을 금속 배선 상부에 형성함으로써, SiN또는 SiC등의 유전율이 큰 구리 확산 방지 절연막 사용이 필요치 않게되어 전체 절연막의 유전율을 감소시키면서 금속 배선의 전자 이동(Electro migration)에 의한 배선 불량 발생을 개선하고 공정 단계를 간소화하여 공정의 신뢰성 및 소자의 전기적 특성을 향상시킬 수 있다.As described above, the present invention charges the semiconductor substrate on which the metal wiring is formed into a metal salt electrolytic cell of a noble metal, and deposits the noble metal only on the upper portion of the metal wiring by a displacement plating method. By forming the formed capping layer on the upper part of the metal wiring, it is not necessary to use a copper diffusion preventing insulating film having a high dielectric constant such as SiN or SiC, thereby reducing wiring defects due to electron migration of the metal wiring while reducing the dielectric constant of the entire insulating film. Improvements and streamlined process steps can improve process reliability and device electrical characteristics.

Claims (4)

금속 배선이 형성된 반도체 기판이 제공되는 단계;Providing a semiconductor substrate on which metal wiring is formed; 귀금속 금속염을 포함한 용액이 담긴 전해조에 상기 반도체 기판을 장입하는 단계; 및Charging the semiconductor substrate into an electrolytic cell containing a solution containing a noble metal salt; And 치환 도금법으로 귀금속을 상기 금속 배선 상부에만 귀금속을 증착시켜 상기 귀금속으로 이루어진 캡핑층을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.Forming a capping layer made of the noble metal by depositing the noble metal only on the upper portion of the metal wiring by a substitution plating method. 제 1 항에 있어서,The method of claim 1, 상기 귀금속은 Pt, Pd, Ag, Au, Rh, Ru 또는 Ir인 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.And the noble metal is Pt, Pd, Ag, Au, Rh, Ru or Ir. 제 1 항에 있어서,The method of claim 1, 상기 전해조에 담긴 용액은 상기 귀금속 이온을 포함하는 황산염, 염화물 용액, 환원 촉진제 및 기타 유기 첨가물 조절제를 포함하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법The solution contained in the electrolytic cell comprises a sulfate, a chloride solution, a reduction accelerator and other organic additive control agent containing the noble metal ion, the metal wiring forming method of the semiconductor device, characterized in that 제 1 항 또는 제 3 항에 있어서,The method according to claim 1 or 3, 상기 용액에는 반응 조절을 위하여 HCOOH 등의 환원제와 비이상 성장을 조절하기 위하여 BTA(Benzotriazole)을 더 혼합하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.The method for forming a metal wiring of the semiconductor device, characterized in that the solution further mixed with a reducing agent such as HCOOH and BTA (Benzotriazole) to control the abnormal growth to control the reaction.
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Publication number Priority date Publication date Assignee Title
WO2012067955A2 (en) * 2010-11-17 2012-05-24 Intel Corporation Methods for forming planarized hermetic barrier layers and structures formed thereby

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* Cited by examiner, † Cited by third party
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WO2012067955A2 (en) * 2010-11-17 2012-05-24 Intel Corporation Methods for forming planarized hermetic barrier layers and structures formed thereby
WO2012067955A3 (en) * 2010-11-17 2012-08-02 Intel Corporation Methods for forming planarized hermetic barrier layers and structures formed thereby
US8524597B2 (en) 2010-11-17 2013-09-03 Intel Corporation Methods for forming planarized hermetic barrier layers and structures formed thereby

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