KR20040037994A - Method for manufacturing a semiconductor device - Google Patents
Method for manufacturing a semiconductor device Download PDFInfo
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- KR20040037994A KR20040037994A KR1020020066849A KR20020066849A KR20040037994A KR 20040037994 A KR20040037994 A KR 20040037994A KR 1020020066849 A KR1020020066849 A KR 1020020066849A KR 20020066849 A KR20020066849 A KR 20020066849A KR 20040037994 A KR20040037994 A KR 20040037994A
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- 238000000034 method Methods 0.000 title claims abstract description 40
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 238000005468 ion implantation Methods 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 12
- 229920005591 polysilicon Polymers 0.000 claims abstract description 12
- 238000002955 isolation Methods 0.000 claims abstract description 6
- 238000000059 patterning Methods 0.000 claims abstract description 5
- 150000002500 ions Chemical class 0.000 claims description 14
- 239000012535 impurity Substances 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 239000002019 doping agent Substances 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 125000006850 spacer group Chemical group 0.000 description 5
- 238000004140 cleaning Methods 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910017855 NH 4 F Inorganic materials 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 230000006641 stabilisation Effects 0.000 description 2
- 238000011105 stabilization Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- KPSZQYZCNSCYGG-UHFFFAOYSA-N [B].[B] Chemical compound [B].[B] KPSZQYZCNSCYGG-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 PMOS 게이트 전극의 도핑효율을 높이기 위해 실시되는 전처리 이온주입공정에 의해 발생하는 게이트 전극의 패턴의 불안정화 및 마진 미확보를 해결할 수 있는 반도체 소자의 제조방법을 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device capable of solving instability and margin instability of a pattern of a gate electrode generated by a pretreatment ion implantation process performed to increase doping efficiency of a PMOS gate electrode. It is about.
일반적으로, 반도체 소자를 구동시키기 위한 회로는 트랜지스터로 구성되는 스위칭 소자, 캐패시터 및 저항 등으로 구성되어 있다. 회로 중의 논리 게이트(logic gate)소자로는 NMOS(N-type MOS)와 PMOS(P-type MOS) 트랜지스터를 동일 반도체 기판 상에 함께 구성한 CMOS(Complementary Metal-Oxide-Semiconductor) 트랜지스터가 단일의 NMOS나 PMOS 트랜지스터에 비해 보다 많이 사용되어지는 추세이다.In general, a circuit for driving a semiconductor element is composed of a switching element composed of a transistor, a capacitor, a resistor, and the like. Logic gate devices in a circuit include a complementary metal-oxide-semiconductor (CMOS) transistor that consists of an N-type MOS (NMOS) and a P-type MOS (PMOS) transistor on the same semiconductor substrate. More and more used than PMOS transistors.
최근에는 서브 미크론 디자인 룰(sub micron design rule)을 사용하여 CMOS 트랜지스터를 제조하는 경우에, NMOS와 PMOS 트랜지스터 각각의 신뢰성을 개선하기 위해 LDD(Lightly Doped Drain) 접합(junction)을 형성한다. 또한, NMOS의 게이트 전극 재질로서 'n+' 도프드 폴리실리콘(doped polysilicon)을 사용하고, PMOS의 게이트 전극 재질로서 'p+' 도프트 폴리실리콘을 사용하고 있다. 이는, NMOS와 PMOS 트랜지스터의 채널을 모두 표면 채널로써 형성시켜 단채널효과(short channel effect)를 개선하기 위함이다.Recently, in the case of manufacturing a CMOS transistor using a sub micron design rule, a lightly doped drain (LDD) junction is formed to improve the reliability of each of the NMOS and PMOS transistors. In addition, 'n + ' doped polysilicon is used as the gate electrode material of the NMOS, and 'p + ' doped polysilicon is used as the gate electrode material of the PMOS. This is to improve the short channel effect by forming both channels of the NMOS and PMOS transistors as surface channels.
PMOS 게이트 전극의 도핑 효율을 높이기 위해 PMOS 게이트 전극을 형성하기 위한 패터닝 공정의 전처리 공정으로 PMOS 영역의 폴리실리콘에만 'p+' 이온(예컨대, 보론)을 이용한 전처리 이온주입공정을 실시한다. 이후, 소오스 및 드레인 이온주입공정을 PMOS 영역과 NMOS 영역에 대해 각각 실시하여 NMOS 게이트 전극, PMOS 게이트 전극 및 소오스 및 드레인 접합영역이 형성될 영역에 이온을 주입시킨다.In order to increase the doping efficiency of the PMOS gate electrode, a pretreatment ion implantation process using 'p + ' ions (eg, boron) is performed only in polysilicon in the PMOS region as a pretreatment process of forming a PMOS gate electrode. Thereafter, source and drain ion implantation processes are performed for the PMOS region and the NMOS region, respectively, to implant ions into the NMOS gate electrode, the PMOS gate electrode, and the region where the source and drain junction regions are to be formed.
이와 같이, PMOS 게이트 전극에만 전처리 이온주입공정을 실시하는 공정은 여러가지 문제점을 발생시킨다. 즉, 게이트 전극을 형성하기 위한 패터닝공정시 PMOS 게이트 전극과 NMOS 게이트 전극의 임계치수(Critical Demension; CD)가 서로 달라지는 문제가 발생한다. 이는, PMOS 게이트 전극에 'p+' 이온을 미리 주입함에 따라 이온이 주입되지 않은 NMOS 게이트 전극보다 PMOS 게이트 전극이 식각율(etch rate)이 높아지기 때문이다. 이와 같이, PMOS 게이트 전극의 식각율이 높아짐에 따라 NMOS 게이트 전극의 임계치수보다 PMOS 게이트 전극의 임계치수가 작아지고, 또한 프로파일도 작아진다. 이에 따라, NMOS 게이트 전극과 PMOS 게이트 전극의 임계치수가 서로 다르게 프로파일되면, 후속 공정 및 소자 마진(Margin) 확보에 큰 영향을 주게 된다.As described above, the process of performing the pretreatment ion implantation process only on the PMOS gate electrode causes various problems. That is, in the patterning process for forming the gate electrode, there is a problem that the critical dimension (CD) of the PMOS gate electrode and the NMOS gate electrode are different from each other. This is because the etch rate of the PMOS gate electrode is higher than that of the NMOS gate electrode to which ions are not implanted, as the 'p + ' ions are previously injected into the PMOS gate electrode. As described above, as the etching rate of the PMOS gate electrode is increased, the threshold size of the PMOS gate electrode is smaller than that of the NMOS gate electrode, and the profile is also smaller. Accordingly, when the critical dimensions of the NMOS gate electrode and the PMOS gate electrode are profiled differently, it has a great influence on the subsequent process and securing the device margin.
따라서, 본 발명은 상기에서 설명한 종래기술의 문제점을 해결하기 위해 안출된 것으로, PMOS 게이트 전극의 도핑효율을 높이기 위해 실시되는 전처리 이온주입공정에 의해 발생하는 게이트 전극의 패턴의 불안정화 및 마진 미확보를 해결하는데 그 목적이 있다.Accordingly, the present invention has been made to solve the problems of the prior art described above, and solves the instability and margin instability of the pattern of the gate electrode generated by the pretreatment ion implantation process performed to increase the doping efficiency of the PMOS gate electrode. Its purpose is to.
또한, 본 발명은 게이트 전극의 패턴의 안정화 및 마진 확보를 구현하여 반도체 소자의 특성을 개선시키는데 다른 목적이 있다.In addition, the present invention has another object to improve the characteristics of the semiconductor device by implementing the stabilization and margin of the pattern of the gate electrode.
도 1 내지 도 7은 본 발명에 따른 반도체 소자의 제조방법을 설명하기 위해 도시한 반도체 소자의 단면도들이다.1 to 7 are cross-sectional views of a semiconductor device for explaining the method of manufacturing the semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
102 : 반도체 기판 104 : 소자 분리막102 semiconductor substrate 104 device isolation film
106 : HLD 산화막 108 : 게이트 산화막106: HLD oxide film 108: gate oxide film
110 : 폴리실리콘막 112a : NMOS 게이트 전극110 polysilicon film 112a NMOS gate electrode
112b : PMOS 게이트 전극 114 : 저농도 접합영역112b: PMOS gate electrode 114: low concentration junction region
116 : 스페이서 118 : 고농도 접합영역116: spacer 118: high concentration junction region
120a 및 120b : 소오스 및 드레인 접합영역120a and 120b: source and drain junction regions
본 발명의 일측면에 따르면, 반도체 기판을 NMOS 영역과 PMOS 영역으로 분리하기 위한 소자 분리막을 형성하는 단계와, 전체 구조 상부에 게이트 전극 패턴용 산화막을 증착하는 단계와, 상기 산화막을 동일한 폭으로 패터닝하여 상기 NMOS 영역 및 상기 PMOS 영역의 반도체 기판을 노출시키는 단계와, 패터닝된 상기 산화막으로 노출되는 상기 반도체 기판 상에 게이트 산화막을 형성하는 단계와, 패터닝된 상기 산화막을 매립하도록 상기 게이트 산화막 상에 폴리실리콘막을 형성하는 단계와, 상기 산화막을 제거하여 상기 NMOS 영역에 NMOS 게이트 전극을 형성하고, 상기 PMOS 영역에 PMOS 게이트 전극을 형성하는 단계와, 전처리 이온주입공정을 실시하여 상기 PMOS 게이트 전극 또는 상기 NMOS 게이트 전극에 불순물 이온을 도핑시키는 단계와, 상기 NMOS 게이트 전극과 상기 PMOS 게이트 전극의 양측으로 노출되는 상기 반도체 기판에 소오스 및 드레인 접합영역을 형성하는 단계를 포함하는 반도체 소자의 제조방법을 제공한다.According to an aspect of the invention, forming a device isolation film for separating a semiconductor substrate into an NMOS region and a PMOS region, depositing an oxide film for a gate electrode pattern on the entire structure, and patterning the oxide film with the same width Exposing the semiconductor substrates of the NMOS region and the PMOS region, forming a gate oxide film on the semiconductor substrate exposed by the patterned oxide film, and filling the patterned oxide film on the gate oxide film. Forming a silicon film, forming an NMOS gate electrode in the NMOS region by removing the oxide film, forming a PMOS gate electrode in the PMOS region, and performing a pretreatment ion implantation process to perform the PMOS gate electrode or the NMOS. Doping impurity ions into a gate electrode, and said NMOS gate electrode And forming a source and drain junction region in the semiconductor substrate exposed to both sides of the PMOS gate electrode.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 설명하기로 한다. 그러나, 본 발명은 이하에서 개시되는 실시예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 수 있으며, 단지 본 실시예는 본 발명의 개시가 완전하도록하며 통상의 지식을 가진자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이다.Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.
도 1 내지 도 7은 본 발명의 바람직한 실시예에 따른 반도체 소자의 제조방법을 설명하기 위하여 도시한 단면도들이다. 여기서는 그 일례로 CMOS 소자의 듀얼 게이트 전극을 도시한 단면도들이다. 한편, 여기서 동일한 참조번호는 동일한 기능을 하는 동일한 부재를 가리킨다.1 to 7 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention. Here, as an example, it is sectional drawing which shows the dual gate electrode of a CMOS element. On the other hand, the same reference numerals herein refer to the same member having the same function.
도 1을 참조하면, P형 반도체 기판(102)을 NMOS 영역과 PMOS 영역으로 정의하기 위해 STI(Shallow Trench Isolation) 공정을 실시하여 소자 분리막(104)을 형성한다. 그런 다음, NMOS 영역에는 'p-' 불순물인 보론(boron)을 주입하여 P-웰(P-Well)을 형성하고, PMOS 영역에는 'n-' 불순물인 인(phosphorous)을 주입하여 N-웰(N-Well)을 형성한다. 한편, P-웰 및 N-웰을 형성하기 전에 문턱전압 이온주입공정을 실시할 수도 있다.Referring to FIG. 1, a shallow trench isolation (STI) process is performed to define the P-type semiconductor substrate 102 as an NMOS region and a PMOS region to form an isolation layer 104. Then, NMOS region 'p -' - N- well by injecting a (phosphorous) impurities impurities, and by implanting boron (boron) to form a P- well (P-Well), PMOS region has 'n' (N-Well) is formed. Meanwhile, before forming the P-well and the N-well, a threshold voltage ion implantation process may be performed.
도 2를 참조하면, 전체 구조 상부에 HLD(High temperature Low pressure Dielectric) 산화막(106)을 증착한다. HLD 산화막(106)은 게이트 전극(도 6의 '112a' 및 '112b'참조)의 높이를 고려하여 2000 내지 3000Å의 두께로 증착하는 것이 바람직하다.Referring to FIG. 2, a high temperature low pressure dielectric (HLD) oxide layer 106 is deposited on the entire structure. The HLD oxide film 106 is preferably deposited to a thickness of 2000 to 3000 mV in consideration of the heights of the gate electrodes (see '112a' and '112b' in FIG. 6).
도 3을 참조하면, 전체 구조 상부에 포토레지스트(photoresist)막을 도포한 후 포토 마스크(photomask)를 이용한 노광 및 현상공정을 순차적으로 실시하여 포토레지스트 패턴(미도시)을 형성한다. 이때, 포토레지스트 패턴은 NMOS 게이트 전극(112a)과 PMOS 게이트 전극(112b)의 폭의 임계치수(즉, N-CD, P-CD)를 고려하여 형성한다.Referring to FIG. 3, after the photoresist film is applied over the entire structure, a photoresist pattern (not shown) is formed by sequentially performing exposure and development processes using a photomask. In this case, the photoresist pattern is formed in consideration of the critical dimensions (ie, N-CD and P-CD) of the widths of the NMOS gate electrode 112a and the PMOS gate electrode 112b.
이어서, 상기 포토레지스트 패턴을 마스크로 이용한 식각공정을 실시하여 PMOS 영역 및 NMOS 영역의 반도체 기판(102)의 상부 표면이 노출되도록 HLD 산화막(106)을 식각한다. 이때, HLD 산화막(106)은 PMOS 영역 및 NMOS 영역에서 동일한 폭으로 패터닝된다. 이에 따라, 도 6에 도시되는 NMOS 게이트 전극(112a)과 PMOS 게이트 전극(112b)의 폭의 임계치수(N-CD, P-CD)는 서로 동일하게 형성될 수 있다.Subsequently, an etching process using the photoresist pattern as a mask is performed to etch the HLD oxide layer 106 to expose the upper surface of the semiconductor substrate 102 in the PMOS region and the NMOS region. At this time, the HLD oxide film 106 is patterned to the same width in the PMOS region and the NMOS region. Accordingly, the threshold dimensions N-CD and P-CD of the widths of the NMOS gate electrode 112a and the PMOS gate electrode 112b shown in FIG. 6 may be formed to be the same.
도 4를 참조하면, 상기 포토레지스트 패턴은 스트립(strip) 공정에 의해 제거된다. 그런 다음, 전체 구조 상부에 대하여 건식 또는 습식산화방식을 이용한 산화방식을 실시하여 NMOS 영역 및 PMOS 영역으로 노출되는 반도체 기판(102)의 상부에 게이트 산화막(108)을 형성한다.Referring to FIG. 4, the photoresist pattern is removed by a strip process. Then, an oxide method using a dry or wet oxidation method is performed on the entire structure to form a gate oxide film 108 on the semiconductor substrate 102 exposed to the NMOS region and the PMOS region.
이어서, 전체 구조 상부에 폴리실리콘막(110)을 3500 내지 4500Å의 두께로 증착한 후, CMP(Chemical Mechanical Polishing) 방식을 이용한 평탄화 공정을 실시하여 HLD 산화막(106)의 상부를 노출시킨다. 이로써, 폴리실리콘막(110)은 게이트 산화막(106)의 상부에 형성되고, HLD 산화막(106)의 패턴 홀(미도시)을 매립시킨다.Subsequently, after the polysilicon film 110 is deposited to a thickness of 3500 to 4500 kPa over the entire structure, a planarization process using a chemical mechanical polishing (CMP) method is performed to expose the upper portion of the HLD oxide film 106. As a result, the polysilicon film 110 is formed on the gate oxide film 106 to fill the pattern hole (not shown) of the HLD oxide film 106.
도 5를 참조하면, 전체 구조 상부에 도 3에서 설명한 방법으로 포토레지스트 패턴(PR)을 형성한다. 이때, 포토레지스트 패턴(PR)은 NMOS 영역은 덮고 PMOS 영역은 노출되도록 형성된다.Referring to FIG. 5, the photoresist pattern PR is formed on the entire structure by the method described with reference to FIG. 3. In this case, the photoresist pattern PR is formed to cover the NMOS region and expose the PMOS region.
이어서, 포토레지스트 패턴(PR)을 마스크로 이용한 전처리 이온주입공정을 실시하여 PMOS 영역의 폴리실리콘막(110)에 'p+' 이온을 주입한다. 여기서, 'p+' 이온으로는 보론을 이용한다. 이와 반대로, NMOS 영역의 폴리실리콘막(110)에 'n+' 이온을 주입할 수도 있다. 이후, 열처리 공정을 실시하여 폴리실리콘막(110)에 도핑된 이온들을 활성화시킬 수도 있다.Next, a pretreatment ion implantation process using the photoresist pattern PR as a mask is performed to implant 'p + ' ions into the polysilicon film 110 in the PMOS region. Here, boron is used as the 'p + ' ion. On the contrary, 'n + ' ions may be implanted into the polysilicon film 110 in the NMOS region. Thereafter, a heat treatment process may be performed to activate ions doped in the polysilicon layer 110.
도 6을 참조하면, 포토레지스트 패턴(PR)은 스트립 공정에 의해 제거된다. 이후, HLD 산화막(106)은 세정공정 또는 습식식각공정에 의해 제거된다. 이로써, NMOS 영역에는 NMOS 게이트 전극(112a)이 형성되고, PMOS 영역에는 PMOS 게이트 전극(112b)이 형성된다.Referring to FIG. 6, the photoresist pattern PR is removed by a strip process. Thereafter, the HLD oxide film 106 is removed by a cleaning process or a wet etching process. As a result, an NMOS gate electrode 112a is formed in the NMOS region, and a PMOS gate electrode 112b is formed in the PMOS region.
상기의 세정공정 또는 습식식각공정은 BOE(Buffer Oxide Etchant; 100:1 또는 300:1의 비율로 H2O로 희석된 HF와 NH4F의 혼합용액[HF와 NH4F의 혼합비는 1:4 내지 1:7])를 이용하여 실시한다. 또한, 세정공정 또는 습식식각공정은 DHF(Diluted HF; 50:1의 비율로 H20로 희석된 HF용액) 및 SC-1(NH4OH/H2O2/H2O 용액이 소정 비율로 혼합된 용액)을 이용하여 실시할 수도 있다.The cleaning process or the wet etching process is a BOE (Buffer Oxide Etchant; mixed solution of HF and NH 4 F diluted with H 2 O at a ratio of 100: 1 or 300: 1 [The mixing ratio of HF and NH 4 F is 1: 4 to 1: 7]). In addition, the cleaning process or the wet etching process may be performed by using DHF (Diluted HF; HF solution diluted with H 2 0 at a ratio of 50: 1) and SC-1 (NH 4 OH / H 2 O 2 / H 2 O solution). Solution) may be used.
도 7을 참조하면, NMOS 영역 및 PMOS 영역에 얕은 접합영역(shallow junction)인 저농도 접합영역(114)을 각각 형성한다. 이때, NMOS 영역의 저농도 접합영역(114)은 'n-' 이온을 이용한 이온주입공정에 의해 형성된다. 이에 반해, PMOS 영역의 저농도 접합영역(114)은 'p-' 이온을 이용한 이온주입공정에 의해 형성된다.Referring to FIG. 7, low-concentration junction regions 114, which are shallow junctions, are formed in the NMOS region and the PMOS region, respectively. At this time, the lightly doped junction region 114 of the NMOS region is 'n -' is formed by an ion implantation process using the ion. In contrast, the low concentration junction region 114 of the PMOS region is formed by an ion implantation process using 'p − ' ions.
이어서, NMOS 게이트 전극(112a) 및 PMOS 게이트 전극(112b)의 양측벽에 스페이서(116)를 형성한다. 이때, 스페이서(116)는 질화막 또는 산화막과 질화막의 적층구조로 형성할 수도 있다. 한편, 스페이서(116)는 소오스 접합영역과 드레인 접합영역 간에 발생할 수 있는 단채널효과(short channel effect)를 방지하기 위하여 인접하게 형성되는 고농도 접합영역(114) 간의 간격을 일정 거리로 이격시키기 위하여 고농도 이온주입공정시 마스크 역할을 하기도 한다.Subsequently, spacers 116 are formed on both side walls of the NMOS gate electrode 112a and the PMOS gate electrode 112b. In this case, the spacer 116 may be formed of a nitride film or a stacked structure of an oxide film and a nitride film. Meanwhile, the spacer 116 has a high concentration in order to space the gap between the high concentration junction regions 114 formed adjacent to a predetermined distance to prevent short channel effects that may occur between the source junction region and the drain junction region. It also serves as a mask during the ion implantation process.
이어서, 스페이서(116)를 마스크로 이용한 고농도 이온주입공정을 실시하여 NMOS 영역과 PMOS 영역에 깊은 접합영역(depth junction)인 고농도 접합영역(118)을 각각 형성한다. 이때, NMOS 영역의 고농도 접합영역(118)은 'n+' 이온을 이용한 이온주입공정에 의해 형성된다. 이에 반해, PMOS 영역의 고농도 접합영역(118)은 'p+' 이온을 이용한 이온주입공정에 의해 형성된다. 이로써, NMOS 영역과 PMOS 영역에는 소오스 및 드레인 접합영역(120a 및 120b)이 각각 형성된다.Subsequently, a high concentration ion implantation process using the spacer 116 as a mask is performed to form a high concentration junction region 118, which is a deep junction region, in the NMOS region and the PMOS region, respectively. At this time, the high concentration junction region 118 of the NMOS region is formed by an ion implantation process using 'n + ' ions. In contrast, the high concentration junction region 118 of the PMOS region is formed by an ion implantation process using 'p + ' ions. As a result, the source and drain junction regions 120a and 120b are formed in the NMOS region and the PMOS region, respectively.
상기에서 설명한 본 발명의 기술적 사상은 바람직한 실시예들에서 구체적으로 기술되었으나, 상기한 실시예들은 그 설명을 위한 것이며, 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명은 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술적 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical spirit of the present invention described above has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.
이상에서 설명한 바와 같이, 본 발명에서는 HLD 산화막을 증착한 후 패터닝하여 게이트 전극의 패턴을 형성하고, 상기 HLD 산화막의 패턴 홀을 매립하도록 폴리실리콘막을 증착하여 게이트 전극을 형성한 후 상기 게이트 전극에 대해 전처리 이온주입공정을 실시함으로써 게이트 전극의 패턴의 불안정화 및 마진 미확보를 해결할 수 있다.As described above, in the present invention, after depositing and patterning an HLD oxide film, a pattern of a gate electrode is formed, and a polysilicon film is deposited to fill a pattern hole of the HLD oxide film, thereby forming a gate electrode. By performing the pretreatment ion implantation process, the pattern of the gate electrode can be unstable and the margin can not be secured.
또한, 본 발명에서는 게이트 전극의 패턴의 안정화 및 마진 확보를 구현함으로써 반도체 소자의 특성을 개선시킬 수 있다.In addition, in the present invention, it is possible to improve the characteristics of the semiconductor device by implementing the stabilization of the pattern of the gate electrode and ensuring the margin.
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