KR20040022344A - Method for manufacturing air gap of semiconductor device - Google Patents

Method for manufacturing air gap of semiconductor device Download PDF

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KR20040022344A
KR20040022344A KR1020020053619A KR20020053619A KR20040022344A KR 20040022344 A KR20040022344 A KR 20040022344A KR 1020020053619 A KR1020020053619 A KR 1020020053619A KR 20020053619 A KR20020053619 A KR 20020053619A KR 20040022344 A KR20040022344 A KR 20040022344A
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South Korea
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air gap
insulator
semiconductor device
photoresist
via profile
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KR1020020053619A
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Korean (ko)
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KR100652308B1 (en
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오상훈
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아남반도체 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for fabricating an air gap of a semiconductor device is provided to reduce the whole capacitance of an interlevel layer by forming an air gap in the interlevel layer of a metal interconnection structure of the semiconductor device. CONSTITUTION: Photoresist is formed on the surface of the first insulator(12) burying the first metal interconnection(10) except an air gap formation region. The air gap formation region on the first insulator is etched by a predetermined depth to form a via profile. The photoresist is eliminated. The second insulator(16) is formed on the resultant structure to stop up the opening of the via profile. A planarization process is performed on the second insulator.

Description

반도체 소자의 에어 갭 제조 방법{METHOD FOR MANUFACTURING AIR GAP OF SEMICONDUCTOR DEVICE}Method for manufacturing air gap of semiconductor device {METHOD FOR MANUFACTURING AIR GAP OF SEMICONDUCTOR DEVICE}

본 발명은 반도체 소자(semiconductor device)의 에어 갭(air gap) 제조 방법에 관한 것으로, 특히, 반도체 소자의 금속 배선 구조의 인터레벨층(interlevel layer)의 캐패시턴스(capacitance)를 줄이기 위한 에어 갭을 제조하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an air gap of a semiconductor device, and more particularly, to manufacturing an air gap for reducing capacitance of an interlevel layer of a metal wiring structure of a semiconductor device. It is about how to.

디바이스 디자인(device design)이 타이트(tight)해지면서 금속 배선 구조와 인터/인트라층 캐패시턴스(inter/intra layer capacitance)에 의한 RC 딜레이(delay)가 이슈(issue)화되고 있다. RC 딜레이는 디바이스의 고속화를 저해하는 요소이다. 이로 인해 인터/인트라층의 캐패시턴스를 줄이기 위한 로우-K 머티리얼(low-K material)에 대한 연구가 진행되고 있으나 현재 확실한 로우-K 머티리얼이 선택되지 않아 실제 공정에 적용하기에 많은 어려움이 있어왔다.As device designs become tight, RC delays due to metal wiring structures and inter / intra layer capacitances are becoming an issue. The RC delay is a factor that hinders the speed of the device. Because of this, research on low-K materials to reduce the capacitance of the inter / intra layer is being conducted. However, since a certain low-K material is not selected, it has been difficult to apply to a real process.

따라서, 기존에 공인된 머티리얼을 사용하면서도 로우-K 머티리얼을 사용하는 것과 같은 특성을 나타낼 수 있는 에어 갭에 대한 연구가 일부 회사에서 활발하게 전개되고 있다.Therefore, some companies are actively researching air gaps that can exhibit the same characteristics as using low-K materials while using previously approved materials.

TEOS 계열의 옥사이드(oxide)에서 SiC 계열의 로우-K 머티리얼이 개발되고 있다.SiC-based low-K materials are being developed from TEOS-based oxides.

종래의 기술에 있어서는 TEOS 계열을 사용하면서도 에어 갭을 형성하여 로우-K를 구현하는 방법이 있었으나 인트라레벨 덴스 에어리어(intralevel dense area)에만 에어 갭을 형성할 수 있기 때문에, 전체적인 캐패시턴스를 감소시키기에는 문제가 되어왔다. 즉, 인터레벨층에서는 에어 갭을 형성하기가 어렵기 때문에, 실제 공정에서 얻고자하는 로우 캐패시턴스를 구현하기가 어렵다.In the prior art, there is a method of implementing low-K by forming an air gap while using the TEOS series, but since the air gap can be formed only in the intralevel dense area, there is a problem in reducing the overall capacitance. Has been. That is, since it is difficult to form an air gap in the interlevel layer, it is difficult to implement a low capacitance desired in an actual process.

본 발명은 상술한 결점을 해결하기 위하여 안출한 것으로, 반도체 소자의 금속 배선 구조의 인터레벨층에 에어 갭을 형성하여 인터레벨층의 전체적인 캐패시턴스를 줄이기 위한 에어 갭을 제조하는 반도체 소자의 에어 갭 제조 방법을 제공하는 데 그 목적이 있다.DISCLOSURE OF THE INVENTION The present invention has been made to solve the above-described drawbacks. The present invention provides an air gap fabrication method for forming an air gap in an interlevel layer of a metal wiring structure of a semiconductor device, thereby manufacturing an air gap for reducing the overall capacitance of the interlevel layer. The purpose is to provide a method.

이와 같은 목적을 달성하기 위한 본 발명은, 제 1 금속 배선을 묻고 있는 제 1 절연체 위 에어 갭이 형성될 영역을 제외한 표면에 포토 레지스트를 형성하는 제 1 단계; 상기 제 1 절연체 위 에어 갭이 형성될 영역을 일정 깊이 식각하여 비아프로파일을 형성하는 제 2 단계; 상기 포토 레지스트를 제거하는 제 3 단계; 전표면에 제 2 절연체를 형성하여 상기 비아 프로파일의 개구부를 막는 제 4 단계; 및 상기 제 2 절연체에 대해서 평탄화 공정을 실시하는 제 5 단계를 포함하는 것을 특징으로 한다.The present invention for achieving the above object, the first step of forming a photoresist on the surface except for the region where the air gap on the first insulator buried in the first metal wiring; A second step of forming a via profile by etching a region where the air gap on the first insulator is to be formed to a predetermined depth; A third step of removing the photoresist; Forming a second insulator on an entire surface to close the opening of the via profile; And a fifth step of performing a planarization process on the second insulator.

도 1a 내지 도 1c는 본 발명에 따른 반도체 소자의 에어 갭 제조 방법을 공정 단계별로 나타낸 단면도,1A through 1C are cross-sectional views illustrating an air gap manufacturing method of a semiconductor device according to an exemplary embodiment of the present invention;

도 2는 본 발명에 따른 반도체 소자의 에어 갭 제조 방법에 의해 만들어진 인터레벨 에어 갭을 나타낸 단면도.2 is a cross-sectional view showing an interlevel air gap made by an air gap manufacturing method of a semiconductor device according to the present invention.

이하, 첨부된 도면을 참조하여 본 발명에 따른 실시예를 상세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 1a 내지 도 1c는 본 발명에 따른 반도체 소자의 에어 갭 제조 방법을 공정 단계별로 나타낸 단면도이다.1A to 1C are cross-sectional views illustrating an air gap manufacturing method of a semiconductor device according to an exemplary embodiment of the present invention.

먼저, 도 1a와 같이 비아 플러그(via plug)와 연결된 제 1 금속 배선(10)을 묻고 있는 제 1 절연체(산화막)(12) 위 에어 갭이 형성될 영역을 제외한 표면에 포토 레지스트(14)를 형성한다.First, as shown in FIG. 1A, a photoresist 14 is disposed on a surface of the first insulator (oxide film) 12, except for a region where an air gap is to be formed. Form.

도 1b와 같이 건식 식각 공정을 수행해서 제 1 절연체(12) 위 에어 갭이 형성될 영역을 일정 깊이 식각하여 비아 프로파일(via profile)을 형성한다.As shown in FIG. 1B, the dry etching process is performed to etch a region where the air gap on the first insulator 12 is to be formed to a predetermined depth to form a via profile.

도 1c와 같이 포토 레지스트(14)를 제거한다. 전표면에 제 2 절연체(산화막)(16)를 형성하여 비아 프로파일의 개구부를 막는다. 제 2 절연체(16)에 대해서 CMP 공정(Chemical Mechanical Polishing process, 화학적 기계적 연마 공정)을 실시하여 에어 갭을 완성한다.As shown in FIG. 1C, the photoresist 14 is removed. A second insulator (oxide film) 16 is formed on the entire surface to close the opening of the via profile. The air gap is completed by performing a CMP process (Chemical Mechanical Polishing process) on the second insulator 16.

도 2는 본 발명에 따른 반도체 소자의 에어 갭 제조 방법에 의해 만들어진 인터레벨 에어 갭을 나타낸 단면도로, 제 1 절연체(12)를 선택적으로 제거하여 비아 홀(via hole)을 선택적으로 형성한 후, 이 선택적으로 형성된 비아 홀을 금속으로 채운다. 이어, 제 2 금속 배선을 수행하면 인터레벨 에어 갭이 제 절연체(12) 속에 정렬되어 있음을 알 수 있다.2 is a cross-sectional view showing an interlevel air gap made by an air gap manufacturing method of a semiconductor device according to the present invention. After selectively removing the first insulator 12 to selectively form via holes, FIG. This selectively formed via hole is filled with metal. Subsequently, when the second metal wiring is performed, it can be seen that the interlevel air gap is aligned in the insulator 12.

이상에서 설명한 바와 같이, 본 발명은 반도체 소자의 금속 배선 구조의 인터레벨층에 에어 갭을 형성하여 인터레벨층의 전체적인 캐패시턴스를 줄인다. 따라서, 새로운 머티리얼에 대한 공정 이슈가 필요없을 뿐만 아니라 원하는 로우 캐패시턴스를 용이하게 구현할 수 있기 때문에, RC 딜레이가 개선되는 효과가 있다. 또한, 고속 디바이스 개발이 용이해 진다.As described above, the present invention forms an air gap in the interlevel layer of the metal wiring structure of the semiconductor element to reduce the overall capacitance of the interlevel layer. Therefore, the RC delay is improved because not only a process issue for the new material is required, but also a desired low capacitance can be easily implemented. In addition, high speed device development is facilitated.

Claims (4)

제 1 금속 배선을 묻고 있는 제 1 절연체 위 에어 갭이 형성될 영역을 제외한 표면에 포토 레지스트를 형성하는 제 1 단계;A first step of forming a photoresist on a surface of the first insulator, except for a region in which an air gap is to be formed, on the first insulator buried in the first metal wire; 상기 제 1 절연체 위 에어 갭이 형성될 영역을 일정 깊이 식각하여 비아 프로파일을 형성하는 제 2 단계;A second step of forming a via profile by etching a region where the air gap on the first insulator is to be formed to a predetermined depth; 상기 포토 레지스트를 제거하는 제 3 단계;A third step of removing the photoresist; 전표면에 제 2 절연체를 형성하여 상기 비아 프로파일의 개구부를 막는 제 4 단계; 및Forming a second insulator on an entire surface to close the opening of the via profile; And 상기 제 2 절연체에 대해서 평탄화 공정을 실시하는 제 5 단계를 포함하는 반도체 소자의 에어 갭 제조 방법.And a fifth step of performing a planarization process on the second insulator. 제 1 항에 있어서, 상기 절연체는 산화막인 것을 특징으로 하는 반도체 소자의 에어 갭 제조 방법.The method of manufacturing an air gap of a semiconductor device according to claim 1, wherein the insulator is an oxide film. 제 1 항에 있어서, 상기 제 2 단계는 건식 식각 공정을 수행해서 상기 제 1 절연체 위 에어 갭이 형성될 영역을 일정 깊이 식각하여 비아 프로파일을 형성하는 것을 특징으로 하는 반도체 소자의 에어 갭 제조 방법.The method of claim 1, wherein in the second step, a via profile is formed by performing a dry etching process to etch a predetermined depth of the region where the air gap on the first insulator is to be formed to form a via profile. 제 1 항에 있어서, 상기 평탄화 공정은 CMP 공정인 것을 특징으로 하는 반도체 소자의 에어 갭 제조 방법.The method of claim 1, wherein the planarization process is a CMP process.
KR1020020053619A 2002-09-05 2002-09-05 Method for manufacturing air gap of semiconductor device KR100652308B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9524937B2 (en) 2013-12-30 2016-12-20 Samsung Electronics Co., Ltd. Semiconductor devices and methods of fabricating the same

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2728073B2 (en) * 1995-12-27 1998-03-18 日本電気株式会社 Method for manufacturing semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9524937B2 (en) 2013-12-30 2016-12-20 Samsung Electronics Co., Ltd. Semiconductor devices and methods of fabricating the same
US9842803B2 (en) 2013-12-30 2017-12-12 Samsung Electronics Co., Ltd. Semiconductor devices including gaps between conductive patterns
US10497647B2 (en) 2013-12-30 2019-12-03 Samsung Electronics Co., Ltd. Semiconductor devices and methods of fabricating the same

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