TW201810526A - Semiconductor structures and method for fabricating the same - Google Patents
Semiconductor structures and method for fabricating the same Download PDFInfo
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本揭露係有關於一種半導體結構，特別是有關於一種具有分離溝槽之半導體結構及其製造方法。 The present disclosure relates to a semiconductor structure, and more particularly to a semiconductor structure having a separation trench and a method of fabricating the same.
在目前的半導體製程中，溝槽(trench)的製作經常置於前段製程(front end of line，FEOL)。由於前段製程(FEOL)包含諸多高溫程序，例如，形成電晶體元件的各項步驟，因此，當製作單一且較大線寬的溝槽並將單一氧化材料填入於其中時，溫度高、低變化所造成熱漲冷縮的結果，常導致溝槽與基板間的界面因內應力作用而形成結構上的差排缺陷(dislocation defect)，使得後續完成的裝置元件經常面臨漏電問題。 In current semiconductor processes, the fabrication of trenches is often placed in the front end of line (FEOL). Since the front-end process (FEOL) contains many high-temperature programs, for example, the steps of forming a transistor element, when a single and large line width trench is formed and a single oxidized material is filled therein, the temperature is high and low. As a result of the thermal expansion and contraction caused by the change, the interface between the trench and the substrate is often caused by internal stress to form a structural dislocation defect, so that subsequently completed device components often face leakage problems.
為有效控制絕緣層上覆矽(silicon on insulator，SOI)結構中絕緣結構的內應力影響，既有溝槽圖案區域常須填入複合材料以避免大量製程缺陷的產生，且，為考量溝槽圖案設計的便利性，通常會允許溝槽圖案可以有十字交錯的情況，然，溝槽的十字交錯區域若未填平，當後續的金屬內連線跨越此交會處時，極有可能造成跨線短路。因此，須使用更厚的複合材料並搭配化學機械研磨(CMP)的研磨處理方能完全填滿溝槽，致製造成本增加。 In order to effectively control the internal stress of the insulating structure in the silicon on insulator (SOI) structure, the trench pattern region often needs to be filled with the composite material to avoid a large number of process defects, and the trench is considered. The convenience of the pattern design usually allows the groove pattern to be cross-staggered. However, if the cross-interlaced area of the groove is not filled, when the subsequent metal interconnection crosses the intersection, it is highly likely to cause a cross. The line is shorted. Therefore, it is necessary to use a thicker composite material and a chemical mechanical polishing (CMP) grinding process to completely fill the grooves, resulting in an increase in manufacturing cost.
此外，為符合某些電路設計的應用需求，必要時須打開絕緣層上覆矽(SOI)的埋入氧化層(buried oxide，BOX)且連通上、下矽基板施予不同電壓，而構成所謂的頂側接觸窗(top-side contact，TSC)，以改變或穩定元件特性，然，既有的溝槽設計僅具備提供元件之間的絕緣功能。 In addition, in order to meet the application requirements of certain circuit designs, it is necessary to open a buried oxide (BOX) on the insulating layer (SOI) and connect the upper and lower substrates to different voltages. The top-side contact (TSC) is used to change or stabilize the component characteristics. However, the existing trench design only provides insulation between the components.
因此，開發一種可解決因溝槽十字交錯造成跨線短路的問題、具備適當絕緣效果且在施加特定低電壓或高電壓情況下仍可維持元件電性穩定的半導體結構，是業界亟需努力的方向。 Therefore, it is an urgent need for the industry to develop a semiconductor structure that can solve the problem of cross-line short circuit caused by trench cross-stacking, has an appropriate insulating effect, and can maintain the electrical stability of the device under application of a specific low voltage or high voltage. direction.
本揭露之一實施例，提供一種半導體結構，包括：一第一基板；一氧化層，形成於該第一基板上；一第二基板，形成於該氧化層上；複數個半導體裝置，形成於該第二基板中；以及複數個溝槽，形成於該第二基板中並填入有一絕緣材料，其中該等溝槽彼此分離，且該等溝槽之其中之一包圍該等半導體裝置之其中之一。 An embodiment of the present disclosure provides a semiconductor structure including: a first substrate; an oxide layer formed on the first substrate; a second substrate formed on the oxide layer; and a plurality of semiconductor devices formed on And a plurality of trenches formed in the second substrate and filled with an insulating material, wherein the trenches are separated from each other, and one of the trenches surrounds the semiconductor device one.
本揭露之一實施例，提供一種半導體結構，包括：一第一基板；一氧化層，形成於該第一基板上；一第二基板，形成於該氧化層上；複數個半導體裝置，形成於該第二基板中；複數個第一溝槽，形成於該第二基板中並填入有一絕緣材料，其中該等第一溝槽彼此分離，且該等第一溝槽之其中之一包圍該等半導體裝置之其中之一；一接觸窗，形成於該第二基板中並穿過該氧化層，與該第一基板連接，其中該接觸窗填入有一導電材料；以及一第三溝槽，形成於該第二基板中並填入 有該絕緣材料，其中該第三溝槽包圍該接觸窗。 An embodiment of the present disclosure provides a semiconductor structure including: a first substrate; an oxide layer formed on the first substrate; a second substrate formed on the oxide layer; and a plurality of semiconductor devices formed on a plurality of first trenches formed in the second substrate and filled with an insulating material, wherein the first trenches are separated from each other, and one of the first trenches surrounds the second trench One of the semiconductor devices; a contact window formed in the second substrate and passing through the oxide layer, connected to the first substrate, wherein the contact window is filled with a conductive material; and a third trench, Formed in the second substrate and filled in There is the insulating material, wherein the third trench surrounds the contact window.
本揭露之一實施例，提供一種半導體結構之製造方法，包括：提供一絕緣層上覆矽(silicon on insulator，SOI)結構，其包括一第一矽基板、一氧化層、以及一第二矽基板，其中該氧化層形成於該第一矽基板上，該第二矽基板形成於該氧化層上；形成複數個第一溝槽、一第二溝槽、以及一第三溝槽於該第二矽基板中，其中該等第一溝槽彼此分離，且該第三溝槽包圍該第二溝槽；形成一絕緣材料於該第二基板上，並填滿該等第一溝槽與該第三溝槽，及填入部分之該第二溝槽中；以該絕緣材料為一罩幕，對該第二溝槽進行蝕刻，以使該第二溝槽延伸穿過該氧化層，與該第一基板連接；以及填入一導電材料於該第二溝槽中，以電性連接該第一基板。 An embodiment of the present disclosure provides a method of fabricating a semiconductor structure, including: providing a silicon on insulator (SOI) structure including a first germanium substrate, an oxide layer, and a second germanium a substrate, wherein the oxide layer is formed on the first germanium substrate, the second germanium substrate is formed on the oxide layer; a plurality of first trenches, a second trench, and a third trench are formed in the substrate In the second substrate, wherein the first trenches are separated from each other, and the third trench surrounds the second trench; forming an insulating material on the second substrate and filling the first trenches with the a third trench, and filling the portion of the second trench; the insulating material is a mask, the second trench is etched to extend the second trench through the oxide layer, and The first substrate is connected; and a conductive material is filled in the second trench to electrically connect the first substrate.
為同時兼顧降低溝槽結構內應力的影響及避免溝槽圖案交會處的凹陷區域形成，本揭露設計出新穎的溝槽圖案(即，包圍半導體裝置的溝槽彼此分離不交會，如第1A圖所示)，藉由縮減溝槽線寬，以矽基板取代習知技術填入溝槽的複合材料，溝槽中，僅須填入例如氧化物的單種絕緣材料，可減少溝槽填充材料的用量及厚度，且不會形成深溝槽十字交會的區域，無須再增加填充材料的用量及厚度，在整體厚度一齊下降的情況下，可減少化學機械研磨(CMP)的研磨量，進而改善研磨後的厚度均勻性。 In order to simultaneously reduce the influence of the stress in the trench structure and avoid the formation of the recessed regions at the intersection of the trench patterns, the present disclosure devises a novel trench pattern (ie, the trenches surrounding the semiconductor device are separated from each other, as shown in FIG. 1A). Shown), by reducing the groove line width, replacing the composite material of the trench with a germanium substrate by a conventional technique, in which only a single insulating material such as an oxide must be filled, and the trench filling material can be reduced. The amount and thickness of the deep groove cross-section will not be formed, no need to increase the amount and thickness of the filler material, and the overall thickness can be reduced, the chemical mechanical polishing (CMP) grinding amount can be reduced, thereby improving the grinding Thickness uniformity after.
為連通絕緣層上覆矽(SOI)的埋入氧化層(buried oxide，BOX)的上、下矽基板形成頂側接觸窗(top-side contact，TSC)，本揭露使用大、小線寬並存的溝槽圖案設計，頂側接觸 窗(TSC)為較大線寬，而較細線寬的環狀溝槽則作為絕緣保護，增加環狀溝槽數量的目的是當頂側接觸窗(TSC)須施予特定電壓(低電壓或高電壓)而非接地模式時，須有足夠的絕緣保護，避免頂側接觸窗(TSC)與半導體元件區產生直接的交互影響，同時定義大、小溝槽的優點可減少一次蝕刻溝槽的程序，使用單一材料填滿小線寬溝槽後，再以既有的硬罩幕為保護層蝕刻大線寬溝槽，接著，導入導電材料即可形成頂側接觸窗(TSC)。 A top-side contact (TSC) is formed for the upper and lower ruthenium substrates of the buried oxide (BOX) of the insulating layer (SOI), and the present invention uses both large and small line widths. Grooved pattern design, top side contact The window (TSC) is a larger line width, and the thinner line width of the annular groove is used as insulation protection. The purpose of increasing the number of annular grooves is to apply a specific voltage (low voltage or when the top side contact window (TSC) is applied. High voltage), not grounding mode, must have sufficient insulation protection to avoid direct interaction between the top side contact window (TSC) and the semiconductor component area, and define the advantages of large and small trenches to reduce the process of etching the trench once. After filling the small line width trench with a single material, the large line width trench is etched with the existing hard mask as a protective layer, and then the conductive material is introduced to form a top side contact window (TSC).
此外，本揭露使用大、小線寬並存的溝槽圖案設計，同時定義大、小溝槽，先使用單一材料填滿小線寬溝槽後，以光罩定義欲蝕刻的大線寬溝槽位置，再以光阻為屏障蝕刻大線寬溝槽，小線寬溝槽可在光阻保護下避免外露，接著，導入導電材料即可形成頂側接觸窗(TSC)。 In addition, the present disclosure uses a groove pattern design in which large and small line widths coexist, and defines large and small grooves. After filling a small line width groove with a single material, the mask is used to define a large line width groove position to be etched. Then, the large line width trench is etched by using the photoresist as a barrier, and the small line width trench can be exposed under the photoresist protection, and then the conductive material can be introduced to form the top side contact window (TSC).
為讓本發明之上述目的、特徵及優點能更明顯易懂，下文特舉一較佳實施例，並配合所附的圖式，作詳細說明如下。 The above described objects, features and advantages of the present invention will become more apparent and understood.
10‧‧‧半導體結構 10‧‧‧Semiconductor structure
12‧‧‧第一(矽)基板 12‧‧‧First (矽) substrate
14‧‧‧氧化層 14‧‧‧Oxide layer
16‧‧‧第二(矽)基板 16‧‧‧second (矽) substrate
18、20、22、24‧‧‧半導體裝置 18, 20, 22, 24‧‧‧ semiconductor devices
26、28、30、32、34‧‧‧(第一)溝槽 26, 28, 30, 32, 34‧‧ (first) trench
36‧‧‧絕緣材料 36‧‧‧Insulation materials
38‧‧‧接觸窗(第二溝槽) 38‧‧‧Contact window (second groove)
40‧‧‧導電材料 40‧‧‧Electrical materials
42‧‧‧第三溝槽 42‧‧‧ third trench
44‧‧‧圖案化硬罩幕層 44‧‧‧ patterned hard mask layer
46‧‧‧圖案化光阻層 46‧‧‧ patterned photoresist layer
W1‧‧‧第一溝槽的寬度 W1‧‧‧ width of the first groove
W2‧‧‧第二溝槽的寬度 W2‧‧‧ width of the second groove
W3‧‧‧第三溝槽的寬度 W3‧‧‧The width of the third groove
Wc‧‧‧接觸窗的寬度 Wc‧‧ ‧ the width of the contact window
第1A圖係根據本揭露之一實施例，一種半導體結構之上視圖；第1B圖為第1A圖沿A-A’剖面線所得之該半導體結構之剖面示意圖；第2A圖係根據本揭露之一實施例，一種半導體結構之上視圖； 第2B圖為第2A圖沿A-A’剖面線所得之該半導體結構之剖面示意圖；第3A圖係根據本揭露之一實施例，一種半導體結構之上視圖；第3B圖為第3A圖沿A-A’剖面線所得之該半導體結構之剖面示意圖；第4A圖係根據本揭露之一實施例，一種半導體結構之上視圖；第4B圖為第4A圖沿A-A’剖面線所得之該半導體結構之剖面示意圖；第5A~5D圖係根據本揭露之一實施例，一種半導體結構製備方法之剖面示意圖；以及第6A~6D圖係根據本揭露之一實施例，一種半導體結構製備方法之剖面示意圖。 1A is a top view of a semiconductor structure according to an embodiment of the present disclosure; FIG. 1B is a schematic cross-sectional view of the semiconductor structure taken along line A-A' of FIG. 1A; FIG. 2A is a view according to the present disclosure. An embodiment, a top view of a semiconductor structure; 2B is a schematic cross-sectional view of the semiconductor structure taken along line A-A' of FIG. 2A; FIG. 3A is a top view of the semiconductor structure according to an embodiment of the present disclosure; FIG. 3B is a view along the 3A A cross-sectional view of the semiconductor structure obtained by the A-A' hatching; FIG. 4A is a top view of a semiconductor structure according to an embodiment of the present disclosure; and FIG. 4B is a cross-sectional view taken along line A-A' of FIG. 4A FIG. 5A to FIG. 5D are schematic cross-sectional views showing a method of fabricating a semiconductor structure according to an embodiment of the present disclosure; and FIGS. 6A-6D are diagrams illustrating a method of fabricating a semiconductor structure according to an embodiment of the present disclosure. Schematic diagram of the section.
請參閱第1A與1B圖，根據本揭露之一實施例，提供一種半導體結構10。第1A圖為半導體結構10的上視圖，第1B圖則為第1A圖沿A-A’剖面線所得的半導體結構10的剖面示意圖。 Referring to FIGS. 1A and 1B, in accordance with an embodiment of the present disclosure, a semiconductor structure 10 is provided. Fig. 1A is a top view of the semiconductor structure 10, and Fig. 1B is a schematic cross-sectional view of the semiconductor structure 10 taken along line A-A' of Fig. 1A.
如第1A與1B圖所示，在本實施例中，半導體結構10包括一第一基板12、一氧化層14、一第二基板16、複數個半導體裝置(18、20、22、24)、以及複數個溝槽(26、28、30、32、34)。氧化層14形成於第一基板12上。第二基板16形成於氧化層14上。半導體裝置(18、20、22、24)形成於第二基板16中。 溝槽(26、28、30、32、34)形成於第二基板16中並填入有一絕緣材料36。值得注意的是，溝槽(26、28、30、32、34)彼此分離，且溝槽(26、28、30、32)的其中之一包圍半導體裝置(18、20、22、24)的其中之一，即每一半導體裝置為一溝槽所包圍，例如，溝槽26包圍半導體裝置18，溝槽28包圍半導體裝置20，溝槽30包圍半導體裝置22，以及溝槽32包圍半導體裝置24，如第1A圖所示。 As shown in FIGS. 1A and 1B, in the present embodiment, the semiconductor structure 10 includes a first substrate 12, an oxide layer 14, a second substrate 16, and a plurality of semiconductor devices (18, 20, 22, 24). And a plurality of grooves (26, 28, 30, 32, 34). The oxide layer 14 is formed on the first substrate 12. The second substrate 16 is formed on the oxide layer 14. Semiconductor devices (18, 20, 22, 24) are formed in the second substrate 16. The trenches (26, 28, 30, 32, 34) are formed in the second substrate 16 and filled with an insulating material 36. It is noted that the trenches (26, 28, 30, 32, 34) are separated from one another and one of the trenches (26, 28, 30, 32) surrounds the semiconductor device (18, 20, 22, 24) One of them, that is, each semiconductor device is surrounded by a trench, for example, the trench 26 surrounds the semiconductor device 18, the trench 28 surrounds the semiconductor device 20, the trench 30 surrounds the semiconductor device 22, and the trench 32 surrounds the semiconductor device 24. As shown in Figure 1A.
在部分實施例中，第一基板12與第二基板16可為矽基板，使得半導體結構10為一絕緣層上覆矽(silicon on insulator，SOI)結構。 In some embodiments, the first substrate 12 and the second substrate 16 may be a germanium substrate such that the semiconductor structure 10 is a silicon on insulator (SOI) structure.
在部分實施例中，半導體裝置(18、20、22、24)可包括各種高電壓或低電壓元件，其包括，但不限定於，場效電晶體(field-effect transistor，FET)或雙極性接面電晶體(bipolar junction transistor，BJT)。 In some embodiments, the semiconductor device (18, 20, 22, 24) may comprise various high voltage or low voltage components including, but not limited to, field-effect transistors (FETs) or bipolar Bipolar junction transistor (BJT).
在部分實施例中，溝槽(26、28、30、32、34)的寬度大體介於0.6~1.0微米。 In some embodiments, the width of the grooves (26, 28, 30, 32, 34) is generally between 0.6 and 1.0 microns.
在部分實施例中，溝槽(26、28、30、32、34)僅填入有絕緣材料36。 In some embodiments, the trenches (26, 28, 30, 32, 34) are only filled with an insulating material 36.
在部分實施例中，絕緣材料36可包括各種適合的金屬氧化物。 In some embodiments, insulating material 36 can comprise a variety of suitable metal oxides.
請參閱第2A與2B圖，根據本揭露之一實施例，提供一種半導體結構10。第2A圖為半導體結構10的上視圖，第2B圖則為第2A圖沿A-A’剖面線所得的半導體結構10的剖面示意圖。 Referring to Figures 2A and 2B, in accordance with an embodiment of the present disclosure, a semiconductor structure 10 is provided. Fig. 2A is a top view of the semiconductor structure 10, and Fig. 2B is a schematic cross-sectional view of the semiconductor structure 10 taken along line A-A' of Fig. 2A.
如第2A與2B圖所示，在本實施例中，半導體結構10包括一第一基板12、一氧化層14、一第二基板16、複數個半導體裝置(18、20、22、24)、複數個第一溝槽(26、28、30、32、34)、一接觸窗38、以及一第三溝槽42。氧化層14形成於第一基板12上。第二基板16形成於氧化層14上。半導體裝置(18、20、22、24)形成於第二基板16中。第一溝槽(26、28、30、32、34)形成於第二基板16中並填入有一絕緣材料36。值得注意的是，第一溝槽(26、28、30、32、34)彼此分離，且第一溝槽(26、28、30、32)的其中之一包圍半導體裝置(18、20、22、24)的其中之一。也就是說，每一半導體裝置為一溝槽所包圍，例如，溝槽26包圍半導體裝置18，溝槽28包圍半導體裝置20，溝槽30包圍半導體裝置22，以及溝槽32包圍半導體裝置24，如第2A圖所示。 As shown in FIGS. 2A and 2B, in the present embodiment, the semiconductor structure 10 includes a first substrate 12, an oxide layer 14, a second substrate 16, and a plurality of semiconductor devices (18, 20, 22, 24). A plurality of first trenches (26, 28, 30, 32, 34), a contact window 38, and a third trench 42. The oxide layer 14 is formed on the first substrate 12. The second substrate 16 is formed on the oxide layer 14. Semiconductor devices (18, 20, 22, 24) are formed in the second substrate 16. The first trenches (26, 28, 30, 32, 34) are formed in the second substrate 16 and filled with an insulating material 36. It is noted that the first trenches (26, 28, 30, 32, 34) are separated from each other, and one of the first trenches (26, 28, 30, 32) surrounds the semiconductor device (18, 20, 22) One of 24). That is, each semiconductor device is surrounded by a trench, for example, the trench 26 surrounds the semiconductor device 18, the trench 28 surrounds the semiconductor device 20, the trench 30 surrounds the semiconductor device 22, and the trench 32 surrounds the semiconductor device 24, As shown in Figure 2A.
此外，接觸窗38形成於第二基板16中並穿過氧化層14，與第一基板12連接。接觸窗38填入有一導電材料40。第三溝槽42形成於第二基板16中並填入有絕緣材料36。值得注意的是，第三溝槽42包圍接觸窗38。 Further, a contact window 38 is formed in the second substrate 16 and passes through the oxide layer 14 to be connected to the first substrate 12. The contact window 38 is filled with a conductive material 40. The third trench 42 is formed in the second substrate 16 and filled with an insulating material 36. It is worth noting that the third groove 42 surrounds the contact window 38.
在部分實施例中，第一基板12與第二基板16可為矽基板，使得半導體結構10為一絕緣層上覆矽(silicon on insulator，SOI)結構。 In some embodiments, the first substrate 12 and the second substrate 16 may be a germanium substrate such that the semiconductor structure 10 is a silicon on insulator (SOI) structure.
在部分實施例中，半導體裝置(18、20、22、24)可包括各種高電壓或低電壓元件，其包括，但不限定於，場效電晶體(field-effect transistor，FET)或雙極性接面電晶體(bipolar junction transistor，BJT)。 In some embodiments, the semiconductor device (18, 20, 22, 24) may comprise various high voltage or low voltage components including, but not limited to, field-effect transistors (FETs) or bipolar Bipolar junction transistor (BJT).
在部分實施例中，第一溝槽(26、28、30、32、34)的寬度W1與第三溝槽42的寬度W3大體介於0.6~1.0微米。 In some embodiments, the width W1 of the first trench (26, 28, 30, 32, 34) and the width W3 of the third trench 42 are substantially between 0.6 and 1.0 micron.
在部分實施例中，第一溝槽(26、28、30、32、34)與第三溝槽42僅填入有絕緣材料36。 In some embodiments, the first trench (26, 28, 30, 32, 34) and the third trench 42 are only filled with an insulating material 36.
在部分實施例中，絕緣材料36可包括各種適合的金屬氧化物。 In some embodiments, insulating material 36 can comprise a variety of suitable metal oxides.
在部分實施例中，接觸窗38的寬度Wc大體大於第一溝槽(26、28、30、32、34)的寬度W1與第三溝槽42的寬度W3。 In some embodiments, the width Wc of the contact window 38 is substantially greater than the width W1 of the first trench (26, 28, 30, 32, 34) and the width W3 of the third trench 42.
在部分實施例中，接觸窗38的寬度Wc大體為2.0微米。 In some embodiments, the width Wc of the contact window 38 is generally 2.0 microns.
在部分實施例中，第一溝槽(26、28、30、32、34)的寬度W1與第三溝槽42的寬度W3大體相同。 In some embodiments, the width W1 of the first trench (26, 28, 30, 32, 34) is substantially the same as the width W3 of the third trench 42.
在部分實施例中，導電材料40可包括各種適合的金屬材料。 In some embodiments, the electrically conductive material 40 can comprise a variety of suitable metallic materials.
在此實施例中，接觸窗38為一頂側接觸窗(top-side contact，TSC)。 In this embodiment, the contact window 38 is a top-side contact (TSC).
在此實施例中，第一溝槽(26、28、30、32、34)與第三溝槽42部分重疊，例如，第一溝槽34與第三溝槽42的其中一側重疊，如第2A圖所示。 In this embodiment, the first trenches (26, 28, 30, 32, 34) partially overlap the third trenches 42, for example, the first trenches 34 overlap with one side of the third trenches 42, such as Figure 2A shows.
在此實施例中，當對接觸窗38施予一特定低電壓時，半導體元件區(即，包括半導體裝置(18、20、22、24)的區域)藉由第一溝槽(26、28、30、32、34)與第三溝槽42的設置可獲得足夠的絕緣保護。 In this embodiment, when a specific low voltage is applied to the contact window 38, the semiconductor element region (i.e., the region including the semiconductor device (18, 20, 22, 24)) is passed through the first trench (26, 28). , 30, 32, 34) and the arrangement of the third trench 42 can obtain sufficient insulation protection.
請參閱第3A與3B圖，根據本揭露之一實施例，提供一種半導體結構10。第3A圖為半導體結構10的上視圖，第3B圖則為第3A圖沿A-A’剖面線所得的半導體結構10的剖面示意圖。 Referring to Figures 3A and 3B, in accordance with an embodiment of the present disclosure, a semiconductor structure 10 is provided. Fig. 3A is a top view of the semiconductor structure 10, and Fig. 3B is a schematic cross-sectional view of the semiconductor structure 10 taken along line A-A' of Fig. 3A.
如第3A與3B圖所示，在本實施例中，半導體結構10包括一第一基板12、一氧化層14、一第二基板16、複數個半導體裝置(18、20、22、24)、複數個第一溝槽(26、28、30、32、34)、一接觸窗38、以及一第三溝槽42。氧化層14形成於第一基板12上。第二基板16形成於氧化層14上。半導體裝置(18、20、22、24)形成於第二基板16中。第一溝槽(26、28、30、32、34)形成於第二基板16中並填入有一絕緣材料36。值得注意的是，第一溝槽(26、28、30、32、34)彼此分離，且第一溝槽(26、28、30、32)的其中之一包圍半導體裝置(18、20、22、24)的其中之一。也就是說，每一半導體裝置為一溝槽所包圍，例如，溝槽26包圍半導體裝置18，溝槽28包圍半導體裝置20，溝槽30包圍半導體裝置22，以及溝槽32包圍半導體裝置24，如第3A圖所示。 As shown in the third embodiment, the semiconductor structure 10 includes a first substrate 12, an oxide layer 14, a second substrate 16, and a plurality of semiconductor devices (18, 20, 22, 24). A plurality of first trenches (26, 28, 30, 32, 34), a contact window 38, and a third trench 42. The oxide layer 14 is formed on the first substrate 12. The second substrate 16 is formed on the oxide layer 14. Semiconductor devices (18, 20, 22, 24) are formed in the second substrate 16. The first trenches (26, 28, 30, 32, 34) are formed in the second substrate 16 and filled with an insulating material 36. It is noted that the first trenches (26, 28, 30, 32, 34) are separated from each other, and one of the first trenches (26, 28, 30, 32) surrounds the semiconductor device (18, 20, 22) One of 24). That is, each semiconductor device is surrounded by a trench, for example, the trench 26 surrounds the semiconductor device 18, the trench 28 surrounds the semiconductor device 20, the trench 30 surrounds the semiconductor device 22, and the trench 32 surrounds the semiconductor device 24, As shown in Figure 3A.
此外，接觸窗38形成於第二基板16中並穿過氧化層14，與第一基板12連接。接觸窗38填入有一導電材料40。第三溝槽42形成於第二基板16中並填入有絕緣材料36。值得注意的是，第三溝槽42包圍接觸窗38。 Further, a contact window 38 is formed in the second substrate 16 and passes through the oxide layer 14 to be connected to the first substrate 12. The contact window 38 is filled with a conductive material 40. The third trench 42 is formed in the second substrate 16 and filled with an insulating material 36. It is worth noting that the third groove 42 surrounds the contact window 38.
在部分實施例中，第一基板12與第二基板16可為矽基板，使得半導體結構10為一絕緣層上覆矽(silicon on insulator，SOI)結構。 In some embodiments, the first substrate 12 and the second substrate 16 may be a germanium substrate such that the semiconductor structure 10 is a silicon on insulator (SOI) structure.
在部分實施例中，半導體裝置(18、20、22、24)可包括各種高電壓或低電壓元件，其包括，但不限定於，場效電晶體(field-effect transistor，FET)或雙極性接面電晶體(bipolar junction transistor，BJT)。 In some embodiments, the semiconductor device (18, 20, 22, 24) may comprise various high voltage or low voltage components including, but not limited to, field-effect transistors (FETs) or bipolar Bipolar junction transistor (BJT).
在部分實施例中，第一溝槽(26、28、30、32、34)的寬度W1與第三溝槽42的寬度W3大體介於0.6~1.0微米。 In some embodiments, the width W1 of the first trench (26, 28, 30, 32, 34) and the width W3 of the third trench 42 are substantially between 0.6 and 1.0 micron.
在部分實施例中，第一溝槽(26、28、30、32、34)與第三溝槽42僅填入有絕緣材料36。 In some embodiments, the first trench (26, 28, 30, 32, 34) and the third trench 42 are only filled with an insulating material 36.
在部分實施例中，絕緣材料36可包括各種適合的金屬氧化物。 In some embodiments, insulating material 36 can comprise a variety of suitable metal oxides.
在部分實施例中，接觸窗38的寬度Wc大體大於第一溝槽(26、28、30、32、34)的寬度W1與第三溝槽42的寬度W3。 In some embodiments, the width Wc of the contact window 38 is substantially greater than the width W1 of the first trench (26, 28, 30, 32, 34) and the width W3 of the third trench 42.
在部分實施例中，接觸窗38的寬度Wc大體為2.0微米。 In some embodiments, the width Wc of the contact window 38 is generally 2.0 microns.
在部分實施例中，第一溝槽(26、28、30、32、34)的寬度W1與第三溝槽42的寬度W3大體相同。 In some embodiments, the width W1 of the first trench (26, 28, 30, 32, 34) is substantially the same as the width W3 of the third trench 42.
在部分實施例中，導電材料40可包括各種適合的金屬材料。 In some embodiments, the electrically conductive material 40 can comprise a variety of suitable metallic materials.
在此實施例中，接觸窗38為一頂側接觸窗(top-side contact，TSC)。 In this embodiment, the contact window 38 is a top-side contact (TSC).
在此實施例中，第一溝槽(26、28、30、32、34)與第三溝槽42分離，例如，第一溝槽34未與第三溝槽42的任何一側重疊，如第3A圖所示。 In this embodiment, the first trench (26, 28, 30, 32, 34) is separated from the third trench 42, for example, the first trench 34 does not overlap with either side of the third trench 42, such as Figure 3A shows.
在此實施例中，當對接觸窗38施予一特定高電壓時，半導體元件區(即，包括半導體裝置(18、20、22、24)的區域)藉由第一溝槽(26、28、30、32、34)與第三溝槽42的設置可獲得足夠的絕緣保護。 In this embodiment, when a specific high voltage is applied to the contact window 38, the semiconductor element region (i.e., the region including the semiconductor device (18, 20, 22, 24)) is passed through the first trench (26, 28). , 30, 32, 34) and the arrangement of the third trench 42 can obtain sufficient insulation protection.
請參閱第4A與4B圖，根據本揭露之一實施例，提供一種半導體結構10。第4A圖為半導體結構10的上視圖，第4B圖則為第4A圖沿A-A’剖面線所得的半導體結構10的剖面示意圖。 Referring to Figures 4A and 4B, in accordance with an embodiment of the present disclosure, a semiconductor structure 10 is provided. Fig. 4A is a top view of the semiconductor structure 10, and Fig. 4B is a schematic cross-sectional view of the semiconductor structure 10 taken along line A-A' of Fig. 4A.
如第4A與4B圖所示，在本實施例中，半導體結構10包括一第一基板12、一氧化層14、一第二基板16、複數個半導體裝置(18、20、22、24)、複數個第一溝槽(26、28、30、32、34)、一接觸窗38、以及一第三溝槽42。氧化層14形成於第一基板12上。第二基板16形成於氧化層14上。半導體裝置(18、20、22、24)形成於第二基板16中。第一溝槽(26、28、30、32、34)形成於第二基板16中並填入有一絕緣材料36。值得注意的是，第一溝槽(26、28、30、32、34)彼此分離，且第一溝槽(26、28、30、32)的其中之一包圍半導體裝置(18、20、22、24)的其中之一。也就是說，每一半導體裝置為一溝槽所包圍，例如，溝槽26包圍半導體裝置18，溝槽28包圍半導體裝置20，溝槽30包圍半導體裝置22，以及溝槽32包圍半導體裝置24，如第4A圖所示。 As shown in FIGS. 4A and 4B, in the present embodiment, the semiconductor structure 10 includes a first substrate 12, an oxide layer 14, a second substrate 16, and a plurality of semiconductor devices (18, 20, 22, 24). A plurality of first trenches (26, 28, 30, 32, 34), a contact window 38, and a third trench 42. The oxide layer 14 is formed on the first substrate 12. The second substrate 16 is formed on the oxide layer 14. Semiconductor devices (18, 20, 22, 24) are formed in the second substrate 16. The first trenches (26, 28, 30, 32, 34) are formed in the second substrate 16 and filled with an insulating material 36. It is noted that the first trenches (26, 28, 30, 32, 34) are separated from each other, and one of the first trenches (26, 28, 30, 32) surrounds the semiconductor device (18, 20, 22) One of 24). That is, each semiconductor device is surrounded by a trench, for example, the trench 26 surrounds the semiconductor device 18, the trench 28 surrounds the semiconductor device 20, the trench 30 surrounds the semiconductor device 22, and the trench 32 surrounds the semiconductor device 24, As shown in Figure 4A.
此外，接觸窗38形成於第二基板16中並穿過氧化層14，與第一基板12連接。接觸窗38填入有一導電材料40。第三溝槽42形成於第二基板16中並填入有絕緣材料36。值得注意 的是，第三溝槽42包圍接觸窗38。 Further, a contact window 38 is formed in the second substrate 16 and passes through the oxide layer 14 to be connected to the first substrate 12. The contact window 38 is filled with a conductive material 40. The third trench 42 is formed in the second substrate 16 and filled with an insulating material 36. Noteworthy The third groove 42 surrounds the contact window 38.
在部分實施例中，第一基板12與第二基板16可為矽基板，使得半導體結構10為一絕緣層上覆矽(silicon on insulator，SOI)結構。 In some embodiments, the first substrate 12 and the second substrate 16 may be a germanium substrate such that the semiconductor structure 10 is a silicon on insulator (SOI) structure.
在部分實施例中，半導體裝置(18、20、22、24)可包括各種高電壓或低電壓元件，其包括，但不限定於，場效電晶體(field-effect transistor，FET)或雙極性接面電晶體(bipolar junction transistor，BJT)。 In some embodiments, the semiconductor device (18, 20, 22, 24) may comprise various high voltage or low voltage components including, but not limited to, field-effect transistors (FETs) or bipolar Bipolar junction transistor (BJT).
在部分實施例中，第一溝槽(26、28、30、32、34)的寬度W1與第三溝槽42的寬度W3大體介於0.6~1.0微米。 In some embodiments, the width W1 of the first trench (26, 28, 30, 32, 34) and the width W3 of the third trench 42 are substantially between 0.6 and 1.0 micron.
在部分實施例中，第一溝槽(26、28、30、32、34)與第三溝槽42僅填入有絕緣材料36。 In some embodiments, the first trench (26, 28, 30, 32, 34) and the third trench 42 are only filled with an insulating material 36.
在部分實施例中，絕緣材料36可包括各種適合的金屬氧化物。 In some embodiments, insulating material 36 can comprise a variety of suitable metal oxides.
在部分實施例中，接觸窗38的寬度Wc大體大於第一溝槽(26、28、30、32、34)的寬度W1與第三溝槽42的寬度W3。 In some embodiments, the width Wc of the contact window 38 is substantially greater than the width W1 of the first trench (26, 28, 30, 32, 34) and the width W3 of the third trench 42.
在部分實施例中，接觸窗38的寬度Wc大體為2.0微米。 In some embodiments, the width Wc of the contact window 38 is generally 2.0 microns.
在部分實施例中，第一溝槽(26、28、30、32、34)的寬度W1與第三溝槽42的寬度W3大體相同。 In some embodiments, the width W1 of the first trench (26, 28, 30, 32, 34) is substantially the same as the width W3 of the third trench 42.
在部分實施例中，導電材料40可包括各種適合的金屬材料。 In some embodiments, the electrically conductive material 40 can comprise a variety of suitable metallic materials.
在此實施例中，第一溝槽(26、28、30、32、34) 與第三溝槽42部分重疊，例如，第一溝槽(28、34)與第三溝槽42的其中兩側重疊，如第4A圖所示。 In this embodiment, the first groove (26, 28, 30, 32, 34) Partially overlapping with the third trench 42, for example, the first trench (28, 34) overlaps both sides of the third trench 42, as shown in FIG. 4A.
請參閱第2A、2B圖及第5A~5D圖，根據本揭露之一實施例，提供一種半導體結構10(如第2A、2B圖所示)的製造方法。第5A~5D圖係為半導體結構10製備方法的剖面示意圖。 Referring to FIGS. 2A, 2B and 5A-5D, a method of fabricating a semiconductor structure 10 (as shown in FIGS. 2A and 2B) is provided in accordance with an embodiment of the present disclosure. 5A-5D are schematic cross-sectional views showing a method of fabricating the semiconductor structure 10.
請參閱第5A圖，提供一絕緣層上覆矽(silicon on insulator，SOI)結構10’。 Referring to Figure 5A, a silicon on insulator (SOI) structure 10' is provided.
如第5A圖所示，絕緣層上覆矽(silicon on insulator，SOI)結構10’包括一第一矽基板12、一氧化層14、以及一第二矽基板16。氧化層14形成於第一矽基板12上。第二矽基板16形成於氧化層14上。 As shown in FIG. 5A, a silicon on insulator (SOI) structure 10' includes a first germanium substrate 12, an oxide layer 14, and a second germanium substrate 16. The oxide layer 14 is formed on the first tantalum substrate 12. The second germanium substrate 16 is formed on the oxide layer 14.
形成一圖案化硬罩幕層(hard mask film)44於第二矽基板16上。 A patterned hard mask film 44 is formed on the second germanium substrate 16.
在部分實施例中，藉由例如化學氣相沈積(chemical vapor deposition，CVD)或物理氣相沈積(physical vapor deposition，PVD)製程，以及圖案化製程形成圖案化硬罩幕層44於第二矽基板16上。 In some embodiments, the patterned hard mask layer 44 is formed on the second layer by, for example, a chemical vapor deposition (CVD) or a physical vapor deposition (PVD) process, and a patterning process. On the substrate 16.
在部分實施例中，圖案化硬罩幕層44可包括，但不限定於，氧化矽、氮化矽、碳化矽、氮氧化矽(SiON)、氮碳化矽(SiCN)、氮碳氧化矽(SiOCN)、鉭(Ta)、氮化鉭(TaN)、鈦(Ti)、氮化鈦(TiN)、氧化鋁(Al2O3)、氮化硼(BN)、氫倍半矽氧烷(hydrogen silsesquioxane，HSQ)或其他適合的高蝕刻選擇性材料。 In some embodiments, the patterned hard mask layer 44 may include, but is not limited to, hafnium oxide, tantalum nitride, tantalum carbide, niobium oxynitride (SiON), niobium oxynitride (SiCN), niobium oxynitride ( SiOCN), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), aluminum oxide (Al 2 O 3 ), boron nitride (BN), hydrogen sesquioxane ( Hydrogen silsesquioxane, HSQ) or other suitable high etch selective materials.
藉由圖案化硬罩幕層44，對第二矽基板16進行蝕刻製程，以於第二矽基板16中形成複數個第一溝槽(26、28、30、32、34)、一第二溝槽38、以及一第三溝槽42。值得注意的是，第一溝槽(26、28、30、32、34)彼此分離，且第三溝槽42包圍第二溝槽38。 The second germanium substrate 16 is etched by patterning the hard mask layer 44 to form a plurality of first trenches (26, 28, 30, 32, 34) and a second in the second germanium substrate 16. A trench 38 and a third trench 42. It is noted that the first trenches (26, 28, 30, 32, 34) are separated from one another and the third trenches 42 surround the second trenches 38.
在部分實施例中，第一溝槽(26、28、30、32、34)的寬度W1與第三溝槽42的寬度W3大體介於0.6~1.0微米。 In some embodiments, the width W1 of the first trench (26, 28, 30, 32, 34) and the width W3 of the third trench 42 are substantially between 0.6 and 1.0 micron.
在部分實施例中，第二溝槽38的寬度W2大體大於第一溝槽(26、28、30、32、34)的寬度W1與第三溝槽42的寬度W3。 In some embodiments, the width W2 of the second trench 38 is substantially greater than the width W1 of the first trench (26, 28, 30, 32, 34) and the width W3 of the third trench 42.
在部分實施例中，第二溝槽38的寬度W2大體為2.0微米。 In some embodiments, the width W2 of the second trench 38 is generally 2.0 microns.
在部分實施例中，第一溝槽(26、28、30、32、34)的寬度W1與第三溝槽42的寬度W3大體相同。 In some embodiments, the width W1 of the first trench (26, 28, 30, 32, 34) is substantially the same as the width W3 of the third trench 42.
在此實施例中，第一溝槽(26、28、30、32、34)與第三溝槽42部分重疊，例如，第一溝槽34與第三溝槽42的其中一側重疊，如第2A圖所示。 In this embodiment, the first trenches (26, 28, 30, 32, 34) partially overlap the third trenches 42, for example, the first trenches 34 overlap with one side of the third trenches 42, such as Figure 2A shows.
在其他實施例中，第一溝槽(26、28、30、32、34)與第三溝槽42亦可分離，例如，第一溝槽34未與第三溝槽42的任何一側重疊，如第3A圖所示。 In other embodiments, the first trenches (26, 28, 30, 32, 34) and the third trenches 42 may also be separated, for example, the first trenches 34 are not overlapped with either side of the third trenches 42. As shown in Figure 3A.
請參閱第5B圖，形成一絕緣材料36於第二矽基板16上，並填滿第一溝槽(26、28、30、32、34)與第三溝槽42，及填入部分的第二溝槽38中，例如，填入第二溝槽38的側壁與底部。 Referring to FIG. 5B, an insulating material 36 is formed on the second germanium substrate 16 and fills the first trenches (26, 28, 30, 32, 34) and the third trenches 42, and the filling portion In the two grooves 38, for example, the side walls and the bottom of the second groove 38 are filled.
在部分實施例中，藉由例如化學氣相沈積(chemical vapor deposition，CVD)或物理氣相沈積(physical vapor deposition，PVD)製程形成絕緣材料36於第二矽基板16上，並填滿第一溝槽(26、28、30、32、34)與第三溝槽42，及填入部分的第二溝槽38中。 In some embodiments, the insulating material 36 is formed on the second germanium substrate 16 by, for example, a chemical vapor deposition (CVD) or a physical vapor deposition (PVD) process, and fills the first The trenches (26, 28, 30, 32, 34) and the third trenches 42, and the second trenches 38 of the filled portions.
在部分實施例中，第一溝槽(26、28、30、32、34)與第三溝槽42僅填入有絕緣材料36。 In some embodiments, the first trench (26, 28, 30, 32, 34) and the third trench 42 are only filled with an insulating material 36.
在部分實施例中，絕緣材料36可包括各種適合的介電材料，例如鋇鍶鈦化物(barium strontium titanate，BST)或二氧化矽。 In some embodiments, the insulating material 36 can comprise a variety of suitable dielectric materials, such as barium strontium titanate (BST) or cerium oxide.
請參閱第5C圖，以絕緣材料36為一罩幕，對第二溝槽38進行蝕刻製程，以使第二溝槽38延伸穿過氧化層14，與第一矽基板12連接。 Referring to FIG. 5C, the second trench 38 is etched by using the insulating material 36 as a mask to extend the second trench 38 through the oxide layer 14 to be connected to the first germanium substrate 12.
請參閱第5D圖，填入一導電材料40於第二溝槽38中，形成一接觸窗38，以電性連接第一矽基板12。 Referring to FIG. 5D, a conductive material 40 is filled in the second trench 38 to form a contact window 38 for electrically connecting the first germanium substrate 12.
在部分實施例中，藉由例如化學氣相沈積(chemical vapor deposition，CVD)或物理氣相沈積(physical vapor deposition，PVD)製程，以及回蝕刻(etch-back)製程填入導電材料40於第二溝槽38中。 In some embodiments, the conductive material 40 is filled in by a chemical vapor deposition (CVD) or physical vapor deposition (PVD) process, and an etch-back process. Two grooves 38.
在部分實施例中，導電材料40可包括各種適合的金屬材料。 In some embodiments, the electrically conductive material 40 can comprise a variety of suitable metallic materials.
在此實施例中，接觸窗38為一頂側接觸窗(top-side contact，TSC)。 In this embodiment, the contact window 38 is a top-side contact (TSC).
至此，即完成半導體結構10(如第2A、2B圖所示) 的製作。 At this point, the semiconductor structure 10 is completed (as shown in Figures 2A and 2B). Production.
請參閱第2A、2B圖及第6A~6D圖，根據本揭露之一實施例，提供一種半導體結構10(如第2A、2B圖所示)的製造方法。第6A~6D圖係為半導體結構10製備方法的剖面示意圖。 Referring to FIGS. 2A, 2B and 6A-6D, in accordance with an embodiment of the present disclosure, a method of fabricating a semiconductor structure 10 (as shown in FIGS. 2A and 2B) is provided. 6A to 6D are schematic cross-sectional views showing a method of fabricating the semiconductor structure 10.
請參閱第6A圖，提供一絕緣層上覆矽(silicon on insulator，SOI)結構10’。 Referring to Figure 6A, a silicon on insulator (SOI) structure 10' is provided.
如第6A圖所示，絕緣層上覆矽(silicon on insulator，SOI)結構10’包括一第一矽基板12、一氧化層14、以及一第二矽基板16。氧化層14形成於第一矽基板12上。第二矽基板16形成於氧化層14上。 As shown in Fig. 6A, a silicon on insulator (SOI) structure 10' includes a first germanium substrate 12, an oxide layer 14, and a second germanium substrate 16. The oxide layer 14 is formed on the first tantalum substrate 12. The second germanium substrate 16 is formed on the oxide layer 14.
形成一圖案化硬罩幕層(hard mask film)44於第二矽基板16上。 A patterned hard mask film 44 is formed on the second germanium substrate 16.
在部分實施例中，藉由例如化學氣相沈積(chemical vapor deposition，CVD)或物理氣相沈積(physical vapor deposition，PVD)製程，以及圖案化製程形成圖案化硬罩幕層44於第二矽基板16上。 In some embodiments, the patterned hard mask layer 44 is formed on the second layer by, for example, a chemical vapor deposition (CVD) or a physical vapor deposition (PVD) process, and a patterning process. On the substrate 16.
在部分實施例中，圖案化硬罩幕層44可包括，但不限定於，氧化矽、氮化矽、碳化矽、氮氧化矽(SiON)、氮碳化矽(SiCN)、氮碳氧化矽(SiOCN)、鉭(Ta)、氮化鉭(TaN)、鈦(Ti)、氮化鈦(TiN)、氧化鋁(Al2O3)、氮化硼(BN)、氫倍半矽氧烷(hydrogen silsesquioxane，HSQ)或其他適合的高蝕刻選擇性材料。 In some embodiments, the patterned hard mask layer 44 may include, but is not limited to, hafnium oxide, tantalum nitride, tantalum carbide, niobium oxynitride (SiON), niobium oxynitride (SiCN), niobium oxynitride ( SiOCN), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), aluminum oxide (Al 2 O 3 ), boron nitride (BN), hydrogen sesquioxane ( Hydrogen silsesquioxane, HSQ) or other suitable high etch selective materials.
藉由圖案化硬罩幕層44，對第二矽基板16進行蝕 刻製程，以於第二矽基板16中形成複數個第一溝槽(26、28、30、32、34)、一第二溝槽38、以及一第三溝槽42。值得注意的是，第一溝槽(26、28、30、32、34)彼此分離，且第三溝槽42包圍第二溝槽38。 Etching the second germanium substrate 16 by patterning the hard mask layer 44 The engraving process is to form a plurality of first trenches (26, 28, 30, 32, 34), a second trench 38, and a third trench 42 in the second germanium substrate 16. It is noted that the first trenches (26, 28, 30, 32, 34) are separated from one another and the third trenches 42 surround the second trenches 38.
在部分實施例中，第一溝槽(26、28、30、32、34)的寬度W1與第三溝槽42的寬度W3大體介於0.6~1.0微米。 In some embodiments, the width W1 of the first trench (26, 28, 30, 32, 34) and the width W3 of the third trench 42 are substantially between 0.6 and 1.0 micron.
在部分實施例中，第二溝槽38的寬度W2大體大於第一溝槽(26、28、30、32、34)的寬度W1與第三溝槽42的寬度W3。 In some embodiments, the width W2 of the second trench 38 is substantially greater than the width W1 of the first trench (26, 28, 30, 32, 34) and the width W3 of the third trench 42.
在部分實施例中，第二溝槽38的寬度W2大體為2.0微米。 In some embodiments, the width W2 of the second trench 38 is generally 2.0 microns.
在部分實施例中，第一溝槽(26、28、30、32、34)的寬度W1與第三溝槽42的寬度W3大體相同。 In some embodiments, the width W1 of the first trench (26, 28, 30, 32, 34) is substantially the same as the width W3 of the third trench 42.
在此實施例中，第一溝槽(26、28、30、32、34)與第三溝槽42部分重疊，例如，第一溝槽34與第三溝槽42的其中一側重疊，如第2A圖所示。 In this embodiment, the first trenches (26, 28, 30, 32, 34) partially overlap the third trenches 42, for example, the first trenches 34 overlap with one side of the third trenches 42, such as Figure 2A shows.
在其他實施例中，第一溝槽(26、28、30、32、34)與第三溝槽42亦可分離，例如，第一溝槽34未與第三溝槽42的任何一側重疊，如第3A圖所示。 In other embodiments, the first trenches (26, 28, 30, 32, 34) and the third trenches 42 may also be separated, for example, the first trenches 34 are not overlapped with either side of the third trenches 42. As shown in Figure 3A.
請參閱第6B圖，形成一絕緣材料36於第二矽基板16上，並填滿第一溝槽(26、28、30、32、34)與第三溝槽42，及填入部分的第二溝槽38中，例如，填入第二溝槽38的側壁與底部。 Referring to FIG. 6B, an insulating material 36 is formed on the second germanium substrate 16 and fills the first trenches (26, 28, 30, 32, 34) and the third trenches 42, and the filling portion In the two grooves 38, for example, the side walls and the bottom of the second groove 38 are filled.
在部分實施例中，藉由例如化學氣相沈積 (chemical vapor deposition，CVD)或物理氣相沈積(physical vapor deposition，PVD)製程形成絕緣材料36於第二矽基板16上，並填滿第一溝槽(26、28、30、32、34)與第三溝槽42，及填入部分的第二溝槽38中。 In some embodiments, by, for example, chemical vapor deposition (chemical vapor deposition, CVD) or physical vapor deposition (PVD) process to form an insulating material 36 on the second germanium substrate 16 and fill the first trench (26, 28, 30, 32, 34) And the third groove 42, and the second groove 38 of the filling portion.
在部分實施例中，第一溝槽(26、28、30、32、34)與第三溝槽42僅填入有絕緣材料36。 In some embodiments, the first trench (26, 28, 30, 32, 34) and the third trench 42 are only filled with an insulating material 36.
在部分實施例中，絕緣材料36可包括各種適合的介電材料，例如鋇鍶鈦化物(barium strontium titanate，BST)或二氧化矽。 In some embodiments, the insulating material 36 can comprise a variety of suitable dielectric materials, such as barium strontium titanate (BST) or cerium oxide.
形成一圖案化光阻層46於絕緣材料36上，露出第二溝槽38。 A patterned photoresist layer 46 is formed on the insulating material 36 to expose the second trenches 38.
在部分實施例中，藉由例如塗佈製程，以及圖案化製程形成圖案化光阻層46於絕緣材料36上。 In some embodiments, the patterned photoresist layer 46 is formed on the insulating material 36 by, for example, a coating process, and a patterning process.
請參閱第6C圖，以圖案化光阻層46為一罩幕，對第二溝槽38進行蝕刻製程，以使第二溝槽38延伸穿過氧化層14，與第一矽基板12連接。 Referring to FIG. 6C, the photoresist layer 46 is patterned as a mask, and the second trench 38 is etched to extend the second trench 38 through the oxide layer 14 to be connected to the first germanium substrate 12.
移除殘留的圖案化光阻層46，露出第二矽基板16上的絕緣材料36。 The residual patterned photoresist layer 46 is removed to expose the insulating material 36 on the second germanium substrate 16.
請參閱第6D圖，填入一導電材料40於第二溝槽38中，形成一接觸窗38，以電性連接第一矽基板12。 Referring to FIG. 6D, a conductive material 40 is filled in the second trench 38 to form a contact window 38 for electrically connecting the first germanium substrate 12.
在部分實施例中，藉由例如化學氣相沈積(chemical vapor deposition，CVD)或物理氣相沈積(physical vapor deposition，PVD)製程，以及回蝕刻(etch-back)製程填入導電材料40於第二溝槽38中。 In some embodiments, the conductive material 40 is filled in by a chemical vapor deposition (CVD) or physical vapor deposition (PVD) process, and an etch-back process. Two grooves 38.
在部分實施例中，導電材料40可包括各種適合的金屬材料。 In some embodiments, the electrically conductive material 40 can comprise a variety of suitable metallic materials.
在此實施例中，接觸窗38為一頂側接觸窗(top-side contact，TSC)。 In this embodiment, the contact window 38 is a top-side contact (TSC).
至此，即完成半導體結構10(如第2A、2B圖所示)的製作。 Thus, the fabrication of the semiconductor structure 10 (shown in Figures 2A and 2B) is completed.
為同時兼顧降低溝槽結構內應力的影響及避免溝槽圖案交會處的凹陷區域形成，本揭露設計出新穎的溝槽圖案(即，包圍半導體裝置的溝槽彼此分離不交會，如第1A圖所示)，藉由縮減溝槽線寬，以矽基板取代習知技術填入溝槽的複合材料，溝槽中，僅須填入例如氧化物的單種絕緣材料，可減少溝槽填充材料的用量及厚度，且不會形成深溝槽十字交會的區域，無須再增加填充材料的用量及厚度，在整體厚度一齊下降的情況下，可減少化學機械研磨(CMP)的研磨量，進而改善研磨後的厚度均勻性。 In order to simultaneously reduce the influence of the stress in the trench structure and avoid the formation of the recessed regions at the intersection of the trench patterns, the present disclosure devises a novel trench pattern (ie, the trenches surrounding the semiconductor device are separated from each other, as shown in FIG. 1A). Shown), by reducing the groove line width, replacing the composite material of the trench with a germanium substrate by a conventional technique, in which only a single insulating material such as an oxide must be filled, and the trench filling material can be reduced. The amount and thickness of the deep groove cross-section will not be formed, no need to increase the amount and thickness of the filler material, and the overall thickness can be reduced, the chemical mechanical polishing (CMP) grinding amount can be reduced, thereby improving the grinding Thickness uniformity after.
為連通絕緣層上覆矽(SOI)的埋入氧化層(buried oxide，BOX)的上、下矽基板形成頂側接觸窗(top-side contact，TSC)，本揭露使用大、小線寬並存的溝槽圖案設計，頂側接觸窗(TSC)為較大線寬，而較細線寬的環狀溝槽則作為絕緣保護，增加環狀溝槽數量的目的是當頂側接觸窗(TSC)須施予特定電壓(低電壓或高電壓)而非接地模式時，須有足夠的絕緣保護，避免頂側接觸窗(TSC)與半導體元件區產生直接的交互影響，同時定義大、小溝槽的優點可減少一次蝕刻溝槽的程序，使用單一材料填滿小線寬溝槽後，再以既有的硬罩幕為保護層 蝕刻大線寬溝槽，接著，導入導電材料即可形成頂側接觸窗(TSC)。 A top-side contact (TSC) is formed for the upper and lower ruthenium substrates of the buried oxide (BOX) of the insulating layer (SOI), and the present invention uses both large and small line widths. The groove pattern design, the top side contact window (TSC) is a larger line width, and the thin line width of the annular groove is used as insulation protection, and the number of annular grooves is increased for the top side contact window (TSC). When a specific voltage (low voltage or high voltage) is to be applied instead of the grounding mode, sufficient insulation protection shall be provided to avoid direct interaction between the top side contact window (TSC) and the semiconductor component area, and to define large and small trenches. The advantage is that the process of etching the trench can be reduced once, after filling the small line width trench with a single material, and then using the existing hard mask as the protective layer A large line width trench is etched, and then a conductive material is introduced to form a top side contact window (TSC).
此外，本揭露使用大、小線寬並存的溝槽圖案設計，同時定義大、小溝槽，先使用單一材料填滿小線寬溝槽後，以光罩定義欲蝕刻的大線寬溝槽位置，再以光阻為屏障蝕刻大線寬溝槽，小線寬溝槽可在光阻保護下避免外露，接著，導入導電材料即可形成頂側接觸窗(TSC)。 In addition, the present disclosure uses a groove pattern design in which large and small line widths coexist, and defines large and small grooves. After filling a small line width groove with a single material, the mask is used to define a large line width groove position to be etched. Then, the large line width trench is etched by using the photoresist as a barrier, and the small line width trench can be exposed under the photoresist protection, and then the conductive material can be introduced to form the top side contact window (TSC).
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 While the invention has been described above in terms of several preferred embodiments, it is not intended to limit the scope of the present invention, and any one of ordinary skill in the art can make any changes without departing from the spirit and scope of the invention. And the scope of the present invention is defined by the scope of the appended claims.
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