KR20030089591A - metal wiring structure and method for fabricating the same in semiconductor device - Google Patents

metal wiring structure and method for fabricating the same in semiconductor device Download PDF

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Publication number
KR20030089591A
KR20030089591A KR1020020027038A KR20020027038A KR20030089591A KR 20030089591 A KR20030089591 A KR 20030089591A KR 1020020027038 A KR1020020027038 A KR 1020020027038A KR 20020027038 A KR20020027038 A KR 20020027038A KR 20030089591 A KR20030089591 A KR 20030089591A
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South Korea
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metal
layer
metal wiring
titanium
semiconductor device
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KR1020020027038A
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Korean (ko)
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이선수
최승수
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삼성전자주식회사
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Priority to KR1020020027038A priority Critical patent/KR20030089591A/en
Publication of KR20030089591A publication Critical patent/KR20030089591A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A metal interconnection structure of a semiconductor device is provided to prevent a metal void and improve adhesion of an interconnection by forming a structure of a dual layer composed of a titanium nitride layer and a titanium layer. CONSTITUTION: The titanium nitride layer(35) that functions to prevent the void and intensify adhesion is formed between a metal interconnection layer(40) and the titanium layer(30) formed on a metal plug(20) and an intermetal dielectric(10). The metal plug is made of a tungsten material. The metal interconnection layer is made of an aluminum material. The metal interconnection has a pitch not greater than 0.32 micrometer.

Description

반도체 소자의 금속배선 구조 및 그의 제조방법{metal wiring structure and method for fabricating the same in semiconductor device}Metal wiring structure and method for fabricating the same in semiconductor device

본 발명은 반도체 소자의 제조에 관한 것으로, 특히 반도체 소자의 금속배선 구조 및 그의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the manufacture of semiconductor devices, and more particularly, to a metal wiring structure of a semiconductor device and a method of manufacturing the same.

반도체 소자의 집적도가 향상되고 동작 스피드가 고속화됨에 따라 금속 배선의 품질확보를 위한 웨팅 레이어 구조가 중요한 이슈로 대두되고 있다.As the degree of integration of semiconductor devices is improved and the operating speed is increased, a wetting layer structure for securing the quality of metal wiring has emerged as an important issue.

통상적으로 텅스텐 재질의 콘택 플러그를 씨엠피 공정을 진행하여 만들고, 그런 다음에 알루미늄 배선을 하게 되는데, 그 금속 배선은 통상적으로 0.32 미크론 미터이하의 피치에서 행해지는 금속 배선 작업이다. 이 경우에 배선 접착력 개선을 위하여 티타늄 레이어가 사용된다. 그런데, 후속의 열 다발(heat budget)을 통한 알루미늄 및 티타늄의 화합물 막 형성으로 인해 상부에 증착된 알루미늄 층의 두께는 얇아진다. 따라서, 일렉트로마이그레이션(electromigration)현상에 기인하여 메탈 보이드(void)가 생성되는 문제점이 있다.Tungsten contact plugs are typically made through a CMP process, followed by aluminum wiring, which is typically a metal wiring operation at pitches below 0.32 microns. In this case a titanium layer is used to improve wiring adhesion. However, the thickness of the aluminum layer deposited thereon becomes thin due to the compound film formation of aluminum and titanium through subsequent heat budgets. Therefore, there is a problem that metal voids are generated due to the electromigration phenomenon.

도 1은 통상적인 금속 배선의 공정단면 구조도이고, 도 2는 도 1에 따른 메탈 보이드 형성의 문제를 보인 확대 단면도이다.1 is a cross-sectional view illustrating a process cross-section of a conventional metal wiring, and FIG. 2 is an enlarged cross-sectional view illustrating a problem of metal void formation according to FIG. 1.

먼저, 도 1을 참조하면, 화학적 기계적 폴리싱(CMP) 공정을 수행하여 층간금속절연막(IMD:10)에 형성된 콘택 홀에 텅스텐 플러그(20)를 만든 후에는 금속배선공정이 진행된다. 상기 금속배선공정에서 상기 층간금속절연막(10)과 하부에 데포지션될 배선층과의 접착력 향상을 위해 먼저 티타늄 레이어(30)를 형성한 다음에 알루미늄 재질의 금속배선 레이어(40)를 형성하게 된다. 이 경우에 단일의 상기 티타늄 레이어(30)를 형성하고, 그 상부에 알루미늄 증착을 행하면 도 2에서 참조부호 A1에서 보여지는 바와 같이 메탈 보이드가 생성되어 버린다. 이러한 것은 열 다발을 통한 알루미늄과 티타늄의 화합물 막의 형성으로 인해 알루미늄 층의 두께가 얇아짐에 따라 일렉트로마이그레이션 현상이 발생하기 때문인 것으로 관찰되었다.First, referring to FIG. 1, after a tungsten plug 20 is formed in a contact hole formed in an interlayer metal insulating layer IMD: 10 by performing a chemical mechanical polishing (CMP) process, a metal wiring process is performed. In the metal wiring process, in order to improve adhesion between the interlayer metal insulating film 10 and the wiring layer to be deposited on the lower portion, the titanium layer 30 is first formed, and then the metal wiring layer 40 made of aluminum is formed. In this case, when the single titanium layer 30 is formed, and aluminum deposition is performed thereon, metal voids are generated as shown by reference numeral A1 in FIG. 2. This was observed because the electromigration phenomenon occurs as the thickness of the aluminum layer becomes thin due to the formation of a compound film of aluminum and titanium through the heat bundle.

따라서, 금속 배선의 품질 확보를 위하여 개선된 웨팅(wetting) 구조가 요망된다. 즉, 메탈 보이드의 생성을 방지하여 금속배선의 신뢰성을 개선하는 기술이 절실히 요구되는 것이다.Therefore, there is a need for an improved wetting structure to ensure the quality of metal wiring. That is, a technique for improving the reliability of metal wiring by preventing the generation of metal voids is urgently required.

따라서, 본 발명의 목적은 종래의 문제를 해결할 수 있는 반도체 소자의 금속배선 구조 및 그의 제조방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a metallization structure of a semiconductor device and a method of manufacturing the same, which can solve the conventional problems.

본 발명의 다른 목적은 금속배선 제조에서 메탈 보이드의 생성을 방지할 수 있는 방법을 제공함에 있다.Another object of the present invention is to provide a method for preventing the generation of metal voids in the manufacture of metallization.

본 발명의 또 다른 목적은 금속배선의 신뢰성 개선을 위해 접착력을 강화하고 메탈 보이드 발생을 제거 또는 최소화할 수 있는 반도체 소자의 금속배선 구조 및 그의 제조방법을 제공함에 있다.It is still another object of the present invention to provide a metallization structure of a semiconductor device and a method for manufacturing the same, which can enhance adhesion and remove or minimize generation of metal voids in order to improve reliability of metallization.

상기한 목적들을 달성하기 위한 본 발명의 일 양태(one aspect)에 따라, 메탈 보이드를 방지하고 접착력을 개선할 수 있는 반도체 소자의 금속배선 구조는, 금속 플러그와 층간금속절연막의 상부에 형성된 티타늄 막과 금속 배선층 사이에 보이드 생성 방지용 질화티타늄 레이어가 형성된 것을 특징으로 한다.According to one aspect of the present invention for achieving the above object, the metal wiring structure of the semiconductor device that can prevent the metal voids and improve the adhesion, the titanium film formed on the metal plug and the interlayer metal insulating film And a titanium nitride layer for preventing voids formed between the metal wiring layer and the metal wiring layer.

또한, 본 발명의 다른 양태에 따라, 반도체 소자의 금속배선 형성방법은, 금속 플러그와 층간금속절연막의 상부에 형성된 티타늄 막 상에 질화티타늄 레이어를 형성 한 다음에 금속 배선층을 증착하는 것을 특징으로 한다.In addition, according to another aspect of the present invention, a method for forming a metal wiring of a semiconductor device is characterized by depositing a metal wiring layer after forming a titanium nitride layer on the titanium film formed on the metal plug and the interlayer metal insulating film. .

도 1은 통상적인 반도체 소자의 금속 배선의 공정단면 구조도1 is a process cross-sectional structure diagram of a metal wiring of a conventional semiconductor device

도 2는 도 1에 따른 메탈 보이드 형성의 문제를 보인 확대단면도2 is an enlarged cross-sectional view illustrating a problem of metal void formation according to FIG. 1;

도 3은 본 발명의 실시 예에 따른 금속 배선의 공정단면 구조도3 is a cross-sectional view of a process structure of a metal wiring according to an embodiment of the present invention;

도 4는 도 3에 따라 메탈 보이드 형성으로부터 프리한 확대단면도4 is an enlarged cross-sectional view free from metal void formation according to FIG.

이하에서는 본 발명에 따른 반도체 소자의 금속배선 구조 및 그의 제조방법에 대한 바람직한 실시 예가 첨부한 도면을 참조로 상세히 설명될 것이다.Hereinafter, a preferred embodiment of a metallization structure and a method of manufacturing the semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

먼저, 본 발명에서는 메탈 보이드를 방지하고 접착력을 개선하기 위하여, 금속 플러그와 층간금속절연막의 상부에 형성된 티타늄 막과 금속 배선층 사이에 보이드 생성 방지용 질화티타늄 레이어를 형성한 것이 특징이다. 여기서, 상기 금속 플러그는 텅스텐 재질일 수 있으며, 상기 금속 배선층은 알루미늄 재질일 수 있다.First, in the present invention, in order to prevent metal voids and to improve adhesion, a titanium nitride layer for preventing voids is formed between the metal film and the titanium film formed on the metal plug and the interlayer metal insulating film. Here, the metal plug may be a tungsten material, and the metal wiring layer may be an aluminum material.

도 3은 본 발명의 실시 예에 따른 금속 배선의 공정단면 구조도로서, 금속 플러그(20)와 층간금속절연막(10)의 상부에 형성된 티타늄 막(30) 상에 질화티타늄 레이어(35)를 형성한 다음에 금속 배선층(40)을 증착하는 것이 나타나 있다.3 is a cross-sectional view illustrating a process cross-section of a metal wiring according to an embodiment of the present invention, in which a titanium nitride layer 35 is formed on a titanium film 30 formed on the metal plug 20 and the interlayer metal insulating film 10. Next, the deposition of the metal wiring layer 40 is shown.

상기 층간금속절연막(10)의 하부에는 반도체 트랜지스터 소자등이 기판에 형성되어있지만, 설명의 간략을 위해 도면에서는 생략되어 있다. 상기 금속 플러그(20)는 상기 층간금속절연막(10)에 형성된 콘택 홀에 텅스텐을 채우고 그 상부에 있는 텅스텐 층을 씨엠피 공정으로 제거하는 것에 의해 형성된다. 상기 티타늄 막(30)의 형성공정까지는 종래의 구조와 동일하게 할 수 있으며, 본 발명의 실시 예에서는 상기 티타늄 막(30)의 상부에 알루미늄 재질의 금속을 바로 증착하지 아니하고, 메탈 보이드 형성 방지 및 접착력 강화를 위한 웨팅 구조 형성용 재질로서 질화티타늄 막(35)을 증착하는 것이다. 상기 막(35)의 두께는 상기 막(30)의 두께보다 얇게 형성하는 것이 바람직하다.A semiconductor transistor element or the like is formed on the substrate under the interlayer metal insulating film 10, but is omitted in the drawings for the sake of simplicity. The metal plug 20 is formed by filling tungsten in a contact hole formed in the interlayer metal insulating layer 10 and removing the tungsten layer on the upper portion thereof through a CMP process. Until the process of forming the titanium film 30 can be the same as the conventional structure, in the embodiment of the present invention does not directly deposit the metal of the aluminum material on the titanium film 30, preventing the formation of metal voids and It is to deposit a titanium nitride film 35 as a material for forming a wetting structure for enhancing the adhesion. The thickness of the film 35 is preferably formed to be thinner than the thickness of the film 30.

상기 막(35)의 형성에 의해 티타늄 층과 후속의 알루미늄과의 반응이 생기지 않아 TiAlx의 고용체가 형성되지 않으므로 알루미늄 층의 두께는 줄어들지 않는다. 그럼에 의해 메탈 보이드의 형성이 원천적으로 방지된다.The formation of the film 35 does not cause a reaction between the titanium layer and subsequent aluminum, so that a solid solution of TiAlx is not formed, so that the thickness of the aluminum layer is not reduced. This prevents the formation of metal voids inherently.

도 4는 도 3에 따라 메탈 보이드 형성으로부터 프리한 확대단면도로서, 금속배선은 0.32㎛ 이하의 피치로 설계되는 경우에 메탈 보이드의 발생이 전혀 없이 양호한 프로파일을 가짐을 확인할 수 있다.FIG. 4 is an enlarged cross-sectional view free from metal void formation according to FIG. 3, where the metal wiring has a good profile without any occurrence of metal voids when designed with a pitch of 0.32 μm or less. FIG.

상기한 바와 같이, 금속 플러그와 층간금속절연막의 상부에 형성된 티타늄 막 상에 질화티타늄 레이어를 형성한 다음에 금속 배선층을 증착하는 것에 의해 메탈 보이드가 방지되고 접착력이 개선된다.As described above, metal voids are prevented and adhesion is improved by forming a titanium nitride layer on the titanium film formed on the metal plug and the interlayer metal insulating film, and then depositing a metal wiring layer.

상기한 설명에서는 본 발명의 바람직한 실시예를 도면을 참조하여 설명하였지만, 해당 기술 분야의 숙련된 당업자는 아래의 특허 청구의 범위에 기재된 본 발명의 기술적 사상 및 영역으로부터 벗어나지 않는 범위 내에서 본 발명을 다양하게 수정 및 변경시킬 수 있음을 이해할 수 있을 것이다.In the foregoing description, a preferred embodiment of the present invention has been described with reference to the drawings, but those skilled in the art will appreciate the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. It will be understood that various modifications and changes can be made.

상기한 바와 같이, 반도체 소자의 금속배선 구조 및 그의 제조방법에 따르면, 질화티타늄 막 및 티타늄 막의 2중 층 구조에 기인하여, 메탈 보이드가 방지되고, 배선 접착력이 개선되는 효과가 있다.As described above, according to the metallization structure of the semiconductor element and the manufacturing method thereof, due to the double layer structure of the titanium nitride film and the titanium film, metal voids are prevented and the wiring adhesion is improved.

Claims (6)

반도체 소자의 금속배선 구조에 있어서,In the metallization structure of a semiconductor device, 금속 플러그와 층간금속절연막의 상부에 형성된 티타늄 막과 금속 배선층 사이에 접착강화 및 보이드 생성 방지용으로서 기능하는 질화티타늄 레이어가 형성된 것을 특징으로 하는 구조.And a titanium nitride layer formed between the metal plug and the titanium film formed on the interlayer metal insulating film and the metal wiring layer to prevent adhesion reinforcement and void formation. 제1항에 있어서,The method of claim 1, 상기 금속 플러그는 텅스텐 재질이며, 상기 금속 배선층은 알루미늄 재질임을 특징으로 하는 구조.The metal plug is a tungsten material, the metal wiring layer is characterized in that the aluminum material. 제1항에 있어서, 상기 금속배선은 0.32㎛ 이하의 피치를 가짐을 특징으로 하는 구조.The structure of claim 1, wherein the metal wiring has a pitch of 0.32 μm or less. 반도체 소자의 금속배선 형성방법에 있어서,In the metal wiring formation method of a semiconductor element, 금속 플러그와 층간금속절연막의 상부에 형성된 티타늄 막 상에 질화티타늄 레이어를 형성한 다음에 금속 배선층을 증착하는 것을 특징으로 하는 방법.Forming a titanium nitride layer on the titanium film formed on the metal plug and the interlayer metal insulating film, and then depositing a metal wiring layer. 제4항에 있어서,The method of claim 4, wherein 상기 금속 플러그는 텅스텐 재질이며, 상기 금속 배선층은 알루미늄 재질임을 특징으로 하는 방법.And the metal plug is made of tungsten and the metal wiring layer is made of aluminum. 제4항에 있어서, 상기 금속배선은 0.32㎛ 이하의 피치를 가짐을 특징으로 하는 방법.The method of claim 4, wherein the metal wiring has a pitch of 0.32 μm or less.
KR1020020027038A 2002-05-16 2002-05-16 metal wiring structure and method for fabricating the same in semiconductor device KR20030089591A (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06260441A (en) * 1993-03-03 1994-09-16 Nec Corp Manufacture of semiconductor device
KR20010004803A (en) * 1999-06-29 2001-01-15 김영환 Method for forming metal line of a semiconductor device
KR20010018072A (en) * 1999-08-17 2001-03-05 박종섭 Method of forming a tungsten line in a semiconductor device
KR20020032400A (en) * 2000-10-26 2002-05-03 마츠시타 덴끼 산교 가부시키가이샤 Semiconductor device and method for fabricating semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06260441A (en) * 1993-03-03 1994-09-16 Nec Corp Manufacture of semiconductor device
KR20010004803A (en) * 1999-06-29 2001-01-15 김영환 Method for forming metal line of a semiconductor device
KR20010018072A (en) * 1999-08-17 2001-03-05 박종섭 Method of forming a tungsten line in a semiconductor device
KR20020032400A (en) * 2000-10-26 2002-05-03 마츠시타 덴끼 산교 가부시키가이샤 Semiconductor device and method for fabricating semiconductor device

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