KR20030075783A - High efficient solar cell and fabrication method thereof - Google Patents
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- KR20030075783A KR20030075783A KR1020020015152A KR20020015152A KR20030075783A KR 20030075783 A KR20030075783 A KR 20030075783A KR 1020020015152 A KR1020020015152 A KR 1020020015152A KR 20020015152 A KR20020015152 A KR 20020015152A KR 20030075783 A KR20030075783 A KR 20030075783A
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- 238000000034 method Methods 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 239000004065 semiconductor Substances 0.000 claims abstract description 20
- 238000005530 etching Methods 0.000 claims description 10
- 239000000126 substance Substances 0.000 claims description 5
- 238000010297 mechanical methods and process Methods 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims description 2
- 239000000243 solution Substances 0.000 description 13
- 229910004298 SiO 2 Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052698 phosphorus Inorganic materials 0.000 description 5
- 239000011574 phosphorus Substances 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 230000031700 light absorption Effects 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 101710134784 Agnoprotein Proteins 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000003929 acidic solution Substances 0.000 description 2
- 239000000654 additive Substances 0.000 description 2
- 239000003085 diluting agent Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000005215 recombination Methods 0.000 description 2
- 230000006798 recombination Effects 0.000 description 2
- 229910017855 NH 4 F Inorganic materials 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000003054 catalyst Substances 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 238000001878 scanning electron micrograph Methods 0.000 description 1
- 238000004626 scanning electron microscopy Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 239000004094 surface-active agent Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0236—Special surface textures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Abstract
Description
본 발명은 태양전지 및 그 제조방법에 관한 것으로, 더욱 상세하게는 고효울 태양전지 및 그 제조방법에 관한 것이다.The present invention relates to a solar cell and a manufacturing method thereof, and more particularly to a high efficiency solar cell and a manufacturing method thereof.
태양 전지는 광전지(photovoltaic device)로서, 반도체의 p-n 접합 원리를 이용하여 태양광을 전기적 에너지로 변환하는 반도체 소자이다. 태양전지의 효율을 향상시키기 위해서는 입사되는 태양광을 최대한으로 흡수할 수 있도록 하여야 한다.A solar cell is a photovoltaic device that converts sunlight into electrical energy using the p-n junction principle of a semiconductor. In order to improve the efficiency of the solar cell should be able to absorb the maximum incident sunlight.
입사된 태양광에 의해 생성된 전하를 수집하기 위해 태양전지의 전면에는 금속 전극이 형성된다. 금속 전극은 입사되는 태양광을 투과시키기 못하고 반사시키며, 이로 인해 금속 전극이 전면에서 차지하는 면적만큼 태양광을 흡수하지 못하여 태양전지의 효율이 떨어지는 쉐이딩 손실(shading loss)이 발생한다. 따라서 이러한 쉐이딩 손실을 줄이기 위해서는 전극의 면적을 최소화하는 것이 필요하다.Metal electrodes are formed on the front surface of the solar cell to collect charges generated by incident sunlight. The metal electrode does not transmit the incident sunlight and reflects it, and thus, the metal electrode does not absorb sunlight as much as the area occupied by the front surface of the metal electrode, resulting in shading loss in which the solar cell is less efficient. Therefore, it is necessary to minimize the area of the electrode to reduce this shading loss.
그러나, 전극의 면적이 너무 작을 경우 전극과 기판 사이의 접착력이 약해져 태양전지의 신뢰성을 저하시키므로 일정 수준 이하로 접촉면적을 감소시키는 것은 불가능하다.However, if the area of the electrode is too small, the adhesive force between the electrode and the substrate is weakened to reduce the reliability of the solar cell, it is impossible to reduce the contact area below a certain level.
전극과 기판 사이에서 전자와 정공의 재결합으로 인해 효율이 감소되는 것을 방지하기 위해 전극 형성 방법의 개선을 제안한 기술이 미국 특허 제5,279,682호에 개시되어 있다. 그러나 여기서도 전극의 접촉 면적 감소에 한계가 있다.A technique is proposed in US Pat. No. 5,279,682 which proposes an improvement in the method of forming an electrode to prevent a decrease in efficiency due to recombination of electrons and holes between the electrode and the substrate. However, here too, there is a limit in reducing the contact area of the electrode.
따라서, 태양전지의 효율 향상을 위해서는 접촉 면적을 줄이면서 접착력이 우수한 전극 개발이 절실히 요청되고 있는 실정이다.Therefore, in order to improve the efficiency of the solar cell, there is an urgent need to develop an electrode having excellent adhesion while reducing the contact area.
접착력 향상 방법을 제안한 기술이 미국 특허 제4,694,115호에 개시되어 있으나, 여기서도 접착력 향상에 한계가 있다.Although a technique for suggesting a method for improving adhesion is disclosed in US Pat. No. 4,694,115, there is a limit in improving adhesion as well.
종래 고효율 태양전지의 기판인 p형의 실리콘 웨이퍼의 표면은 광흡수를 높이기 위해 텍스처링(texturing)되어 있고 기판의 상면에는 인(P) 도핑에 의해 n층이 형성되어 있으며, n층 상에는 표면 부동화(passivation) 및 반사방지 효과를 위해 SiO2층이 형성되어 있다.The surface of a p-type silicon wafer, which is a substrate of a conventional high efficiency solar cell, is textured to increase light absorption, n layers are formed on the upper surface of the substrate by doping with phosphorus (P), and surface immobilization is performed on the n layers. SiO 2 layer is formed for passivation and antireflection effect.
전극 부분에는 SiO2층이 오프닝(opening)되어 그 하부에 형성된 고농도 인도핑된 영역인 n+영역을 노출시키는 전극 패턴이 형성되어 있으며, 전극 패턴을 통해 n+영역과 연결되도록 전면 전극이 형성되어 있다. 이 때, n+영역은 전극 패턴에 비해 넓은 폭으로 형성되어 있다.In the electrode portion, an SiO 2 layer is opened to form an electrode pattern exposing an n + region, which is a heavily doped region formed below, and a front electrode is formed to be connected to the n + region through the electrode pattern. have. At this time, the n + region is formed to be wider than the electrode pattern.
이와 같은 종래 고효율 태양전지에서는 전극과 기판 사이의 접착력 한계로 인해 접촉 저항이 증가하고 제품의 신뢰성이 저하되는 문제점이 있었다.In the conventional high efficiency solar cell, there is a problem in that contact resistance is increased and reliability of a product is lowered due to the adhesion limit between the electrode and the substrate.
특히, 도금법으로 전극을 형성할 경우 전극의 접착력 저하 문제가 심해지며 따라서 제품의 신뢰성이 매우 낮은 문제점이 있었다.In particular, when the electrode is formed by the plating method, the problem of lowering the adhesive strength of the electrode is severe, and thus there is a problem in that the reliability of the product is very low.
본 발명은 상기한 바와 같은 문제점을 해결하기 위한 것으로, 그 목적은 태양전지의 전극과 기판 사이의 접촉면적을 줄이면서 접착력이 우수한 전극을 형성하여 태양전지의 효율을 향상시키는 데 있다.The present invention is to solve the problems as described above, the object is to improve the efficiency of the solar cell by forming an electrode with excellent adhesion while reducing the contact area between the electrode and the substrate of the solar cell.
도 1은 본 발명의 일실시예에 따른 고효율 태양전지를 도시한 단면도이다.1 is a cross-sectional view showing a high efficiency solar cell according to an embodiment of the present invention.
도 2는 도 1에서 전극 패턴을 도시한 도면이다.FIG. 2 is a diagram illustrating an electrode pattern in FIG. 1.
도 3a 및 도 3b는 화학적 식각 방법으로 형성된 요철을 관측한 주사전자현미경 사진이다.3A and 3B are scanning electron micrographs of irregularities formed by chemical etching.
상기한 바와 같은 목적을 달성하기 위하여, 본 발명에서는 실리콘 웨이퍼의 표면에 에치핏(etch pit)을 형성하여 표면 요철을 부여한 후, 그 위에 금속 전극을 형성하는 것을 특징으로 한다.In order to achieve the above object, the present invention is characterized by forming an etch pit on the surface of the silicon wafer to impart surface irregularities, and then form a metal electrode thereon.
이하, 본 발명에 따른 고효율 태양전지 및 그 제조방법에 대해 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a high efficiency solar cell and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.
먼저, 본 발명에 따른 고효율 태양전지의 구성에 대해 설명한다.First, the configuration of the high efficiency solar cell according to the present invention will be described.
도 1은 본 발명의 일실시예에 따른 고효율 태양전지를 도시한 단면도이고, 도 2는 도 1에서 전극 패턴을 도시한 도면이다.1 is a cross-sectional view showing a high efficiency solar cell according to an embodiment of the present invention, Figure 2 is a view showing an electrode pattern in FIG.
도 1에 도시된 바와 같이, 제1도전형, 일 예로 p형 실리콘 웨이퍼(1)의 표면은 광흡수를 높이기 위해 텍스처링(texturing)되어 있고 전면에는 실리콘 웨이퍼(1)와 반대 도전형이 제2도전형, 일예로 n층(2)이 인(P) 도핑에 의해 형성되어 있다. n층(2)의 상부에는 표면 부동화(passivation) 및 반사방지 효과를 위해 SiO2층(3)이 형성되어 있으며, 전면 전극이 형성될 부분에는 SiO2층(3)이 일부분 오프닝된 전극 패턴(4)이 형성되어 있다. 전면 전극(5)은 전극 패턴(4)을 통해 그 하부의 고농도 인 도핑된 n+영역(6)과 접촉하도록 형성되어 있다.As shown in FIG. 1, the surface of the first conductive type, for example, the p-type silicon wafer 1 is textured to increase light absorption and the front surface of the second conductive type opposite to the silicon wafer 1 is formed. In the conductive type, for example, the n layer 2 is formed by phosphorus (P) doping. The SiO 2 layer 3 is formed on the n layer 2 for the surface passivation and antireflection effect, and the electrode pattern in which the SiO 2 layer 3 is partially opened is formed on the portion where the front electrode is to be formed. 4) is formed. The front electrode 5 is formed to be in contact with the doped n + region 6 at the lower portion through the electrode pattern 4.
본 발명에서는 전극 패턴(4)에 의해 노출된 n+영역(6)의 상면에 도 2에 도시된 바와 같이 요철이 형성되어 있으며, 이러한 표면 요철은 화학적 방법 또는 기계적 방법으로 형성된 것이다. 이 때 요철의 최상부와 최하부 사이의 단차는 10 ㎛ 이하인 것이 바람직하다.In the present invention, irregularities are formed on the upper surface of the n + region 6 exposed by the electrode pattern 4 as shown in FIG. 2, and the surface irregularities are formed by a chemical method or a mechanical method. At this time, the step between the top and bottom of the unevenness is preferably 10 µm or less.
이와 같이 전극 패턴의 바닥면에 표면 요철이 형성되어 있으면, 전극 패턴과 그 상부에 형성되는 전극과의 접착성이 대폭 향상된다.Thus, when surface unevenness | corrugation is formed in the bottom surface of an electrode pattern, the adhesiveness of an electrode pattern and the electrode formed in the upper part will improve significantly.
그러면, 상기한 바와 같은 본 발명에 따른 고효율 태양전지의 제조 방법에 대해 상세히 설명한다.Then, the manufacturing method of the high efficiency solar cell which concerns on this invention as mentioned above is demonstrated in detail.
먼저, 표면에서의 광흡수를 높이기 위해 p형의 실리콘 웨이퍼(1)의 표면을 텍스처링한 후 기판의 전면에 인(P)을 도핑하여 n층(2)을 형성한다.First, in order to increase light absorption at the surface, the surface of the p-type silicon wafer 1 is textured, and then the n layer 2 is formed by doping phosphorus (P) on the entire surface of the substrate.
다음, 포토리소그래피 공정으로 제1산화막 마스크를 이용하여 n층(2) 상에고농도로 인을 주입하여 n+영역(6)을 형성하고 제1산화막 마스크를 제거한 후, n+영역(6)을 포함하여 n층(2) 상부 전면에 SiO2층(3)을 형성한다. 이어서, 제1산화막 마스크보다 좁은 오프닝 폭을 가지는 제2산화막 마스크를 이용하여 제2산화막 마스크의 오프닝된 부분이 n+영역(6)의 중심부분에 위치하도록 정렬한 상태에서 SiO2층(3)을 식각하여 전극 패턴(4)을 형성한다.Subsequently, phosphorus is implanted at a high concentration on the n layer 2 using a first oxide mask by a photolithography process to form n + region 6 and the first oxide mask is removed, and then n + region 6 is removed. To form an SiO 2 layer 3 on the entire upper surface of the n layer 2. Subsequently, using the second oxide mask having an opening width narrower than that of the first oxide mask, the SiO 2 layer 3 is aligned so that the opened portion of the second oxide mask is positioned at the center portion of the n + region 6. Is etched to form the electrode pattern 4.
다음, 전극 패턴(4)에 의해 노출된 n+영역(6)의 상면에 요철을 가지도록, 식각 용액 내에 기판을 침지하는 화학적 방법 또는 표면을 가공하여 표면에 홈을 형성하는 기계적 방법으로 표면처리한다.Next, the surface treatment is performed by a chemical method of immersing the substrate in the etching solution or a mechanical method of forming a groove on the surface so as to have irregularities on the upper surface of the n + region 6 exposed by the electrode pattern 4. do.
화학적 방법의 경우, 등방성 또는 이방성 식각 용액에 기판을 수초 내지 수분 동안 침지하여 전극 패턴을 제외한 다른 부분의 손상없이 전극 패턴의 표면만을 식각할 수 있으며, 전극 패턴의 표면에는 에치핏이 수십~수백 개가 10㎛ 이하의 깊이로 형성된다.In the chemical method, the substrate is immersed in an isotropic or anisotropic etching solution for several seconds to several minutes to etch only the surface of the electrode pattern without damaging other parts except the electrode pattern, and the surface of the electrode pattern has tens to hundreds of etch-fits. It is formed to a depth of 10 μm or less.
일예로, 표면 텍스처링을 위한 식각시 사용한 식각용액과 동일한 KOH용액(물에 대하여 KOH가 8중량% 포함)에 기판을 침지하여 70℃의 온도에서 1mm/min의 식각속도로 식각하여 에치핏을 형성할 수 있다.For example, the substrate is immersed in the same KOH solution (including 8 wt% KOH in water) as the etching solution used for etching for surface texturing, and etched by etching at an etching rate of 1 mm / min at a temperature of 70 ° C. can do.
또 다른 예로서, 산성용액인 HF(70% 희석액):HNO3(70% 희석액):H2O 가 12:1:5 인 용액에 첨가제로서 AgNO3, NaNO2, I2중의 하나 이상을 전체 용액의 1% 미만으로 첨가된 식각용액에 기판을 수직으로 침지하고 기판의 흔들림이 없는 상태의상온에서 7~8 mm/min의 식각속도로 식각할 수 있다. 이 때 AgNO3및 I2는 촉매제로서 첨가된 것이고, NaNO2는 표면 활성제로서 첨가된 것이다. 식각한 다음에는 후처리로서, 금속이나 SixFxOx등의 불순물을 제거하기 위해 NH4F:HNO3가 1:30인 용액에 약 1분 동안 침지하고, HF:HNO3가 1:30인 용액에 약 1분 동안 침지한 후 희석 KOH 용액에 약 1~4분 동안 침지한다.As another example, one or more of AgNO 3 , NaNO 2 , and I 2 as additives may be added to a solution having an acidic solution of HF (70% diluent): HNO 3 (70% diluent): H 2 O of 12: 1: 5. The substrate is vertically immersed in the etching solution added to less than 1% of the solution, and the substrate may be etched at an etching rate of 7 to 8 mm / min at room temperature without shaking the substrate. AgNO 3 and I 2 are added as catalysts and NaNO 2 is added as surface active agents. After etching, it is immersed in a solution of NH 4 F: HNO 3 1:30 for about 1 minute to remove impurities such as metal or Si x F x O x as a post treatment, and HF: HNO 3 is 1: Immerse in 30 phosphorus solution for about 1 minute and then immerse in dilute KOH solution for about 1-4 minutes.
상기한 바와 같은 화학적 방법으로 요철을 형성한 다음, 그 표면을 주사전자현미경으로 관측한 결과가 도 3a 및 도 3b에 도시되어 있으며, 도 3a 및 도 3b는 각각 KOH 용액 및 HF:HNO3:H2O 가 12:1:5 인 용액에 첨가제로서 AgNO3, NaNO2, I2가 전체 용액의 1% 미만으로 첨가된 산성 용액을 이용하여 식각된 경우이다.After forming the unevenness by the chemical method as described above, the surface was observed by scanning electron microscopy, and the results are shown in FIGS. 3A and 3B, and FIGS. 3A and 3B are KOH solution and HF: HNO 3 : H, respectively. This is the case when AgNO 3 , NaNO 2 , I 2 are added as an additive to a solution having 2 O of 12: 1: 5 using an acidic solution added to less than 1% of the total solution.
한편, 본 발명의 다른 실시예에서는 전극 패턴(4)의 하부에 형성된 n+영역(6)을 전극 패턴(4)과 동일한 폭으로 형성할 수도 있다.Meanwhile, in another embodiment of the present invention, the n + region 6 formed under the electrode pattern 4 may be formed to have the same width as the electrode pattern 4.
이 경우에는 n층(2) 형성 후, n층(2)의 상부 전면에 SiO2층(3)을 형성하고, 그 다음 마스크를 이용하여 SiO2층(3)의 일부분을 식각하여 전극 패턴(4)을 형성한 후, 전극 패턴(4)을 통해 노출된 n층(2)의 상면에 요철을 형성하고, 고농도로 인을 도핑하여 n+영역(6)을 형성한 다음, Ag 또는 Cu를 도금하여 전면 전극을 형성한다.In this case, after the n layer 2 is formed, an SiO 2 layer 3 is formed on the entire upper surface of the n layer 2, and then a part of the SiO 2 layer 3 is etched using a mask to form an electrode pattern ( 4) and then, irregularities are formed on the upper surface of the n layer 2 exposed through the electrode pattern 4, and the phosphorous is doped at a high concentration to form the n + region 6, and then Ag or Cu is formed. Plating to form the front electrode.
이와 같이 도금법을 이용하여 전면 전극을 형성할 경우, 표면 요철에 따른 전극의 접착력 향상 효과가 뚜렷하게 나타나기 때문에, 종래 표면 요철 형성 없이매끈하게 연마된 표면 위에 전극을 형성하던 것에 비해 태양전지의 신뢰성이 매우 향상된다.When the front electrode is formed using the plating method as described above, the effect of improving the adhesive strength of the electrode due to the surface irregularities is apparent, so that the reliability of the solar cell is much higher than that of the electrode on the smoothly polished surface without forming the surface irregularities. Is improved.
또한, 이러한 도금법을 이용하여 전면 전극을 형성할 경우, n+영역 형성을 위한 별도의 포토리소그래피 공정이 필요치 않으므로 형성된 n+영역의 폭이 전극 패턴의 폭과 동일하며, 따라서 종래에 비해 n+영역과 전극과의 접촉 면적을 줄일 수 있기 때문에 재결합 전류를 감소시켜 태양전지의 변환 효율 향상에 기여할 수 있다.In the case of forming a front electrode using such a plating method, n + a separate photolithography process is the width of the n + regions formed so necessary for the area to form the same as the width of the electrode pattern, and therefore as compared with the conventional n + region Since the contact area with the electrode can be reduced, the recombination current can be reduced, thereby contributing to the improvement of the conversion efficiency of the solar cell.
상기한 바와 같이, 본 발명에 따라 전극 패턴에 의해 노출되는 막 표면에 요철을 형성하면, 전극과 기판의 접착성이 향상되어 접촉 저항이 감소되는 효과가 있으며, 따라서 제품의 신뢰성 및 수율이 향상되는 효과가 있다.As described above, when the irregularities are formed on the surface of the film exposed by the electrode pattern according to the present invention, the adhesion between the electrode and the substrate is improved, thereby reducing the contact resistance, thus improving the reliability and yield of the product. It works.
또한, 접착성이 향상되어 전극과 기판의 접촉 면적을 줄일 수 있으므로, 전극의 면적만큼 빛의 흡수가 차단되는 쉐이딩 로스(shading loss)를 줄일 수 있으며 이로 인해 태양전지의 효율이 향상되는 효과가 있다.In addition, since the adhesion is improved to reduce the contact area between the electrode and the substrate, it is possible to reduce the shading loss (blocking loss) in which light absorption is blocked by the area of the electrode, thereby improving the efficiency of the solar cell. .
또한, 전극과 기판의 접촉 면적 감소에 의해 개방전압이 약 10~40 mV 정도 향상되는 효과가 있다.In addition, the opening voltage is improved by about 10 to 40 mV by reducing the contact area between the electrode and the substrate.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100735951B1 (en) * | 2005-02-17 | 2007-07-06 | 세이코 엡슨 가부시키가이샤 | Method for forming film pattern, method for manufacturing device |
| KR101067807B1 (en) * | 2010-08-27 | 2011-09-27 | 코오롱글로텍주식회사 | Solar cell and manufacturing method for solar sell's electrode |
| KR20220083435A (en) | 2020-12-11 | 2022-06-20 | 정봉교 | Wave shape solar cell silicon wafer and its manufacturing method |
| KR20220092158A (en) | 2020-12-24 | 2022-07-01 | 정봉교 | Solar-cell and Solar-cell module manufacturing method |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100735951B1 (en) * | 2005-02-17 | 2007-07-06 | 세이코 엡슨 가부시키가이샤 | Method for forming film pattern, method for manufacturing device |
| KR101067807B1 (en) * | 2010-08-27 | 2011-09-27 | 코오롱글로텍주식회사 | Solar cell and manufacturing method for solar sell's electrode |
| WO2012026650A1 (en) * | 2010-08-27 | 2012-03-01 | 코오롱글로텍주식회사 | Solar battery cell and method for forming electrode thereof |
| KR20220083435A (en) | 2020-12-11 | 2022-06-20 | 정봉교 | Wave shape solar cell silicon wafer and its manufacturing method |
| KR20220092158A (en) | 2020-12-24 | 2022-07-01 | 정봉교 | Solar-cell and Solar-cell module manufacturing method |
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