KR20030057886A - Method of forming a isolation layer in semiconductor device - Google Patents
Method of forming a isolation layer in semiconductor device Download PDFInfo
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- KR20030057886A KR20030057886A KR1020010087988A KR20010087988A KR20030057886A KR 20030057886 A KR20030057886 A KR 20030057886A KR 1020010087988 A KR1020010087988 A KR 1020010087988A KR 20010087988 A KR20010087988 A KR 20010087988A KR 20030057886 A KR20030057886 A KR 20030057886A
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- 238000000034 method Methods 0.000 title claims abstract description 57
- 238000002955 isolation Methods 0.000 title claims abstract description 42
- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 21
- 238000004140 cleaning Methods 0.000 claims abstract description 11
- 230000003647 oxidation Effects 0.000 claims abstract description 11
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 11
- 238000000151 deposition Methods 0.000 claims abstract description 3
- 238000005530 etching Methods 0.000 claims abstract 2
- 230000004888 barrier function Effects 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 150000004767 nitrides Chemical class 0.000 abstract description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 3
- 230000000452 restraining effect Effects 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 230000002159 abnormal effect Effects 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 238000009279 wet oxidation reaction Methods 0.000 description 3
- 229910019142 PO4 Inorganic materials 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-K phosphate Chemical compound [O-]P([O-])([O-])=O NBIIXXVUZAFLBC-UHFFFAOYSA-K 0.000 description 2
- 239000010452 phosphate Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000004381 surface treatment Methods 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
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Abstract
Description
본 발명은 반도체 소자의 소자 분리막 형성 방법에 관한 것으로, 특히 STI(Shallow Trench Isolation) 구조에서 발생되는 모트(Moat)를 억제할 수 있는 반도체 소자의 소자 분리막 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a device isolation film of a semiconductor device, and more particularly, to a method of forming a device isolation film of a semiconductor device capable of suppressing a moat generated in a shallow trench isolation (STI) structure.
일반적으로, 반도체 기판 상에 트랜지스터와 커패시터 등을 형성하기 위해 반도체 기판에는 전기적으로 통전이 가능한 활성 영역(Active Region)과 전기적으로 통전되는 것을 방지하고, 소자를 서로 분리하기 위한 소자 분리 영역(Isolation Region)을 형성한다.In general, in order to form transistors, capacitors, and the like on the semiconductor substrate, an isolation region for preventing electrically conduction from an electrically conducting active region and an isolation region for separating the elements from each other. ).
반도체 소자 분리 방법으로는 LOCOS(Local Oxidation Of Silicon) 소자 분리 방식이 이용되고 있다. LOCOS 소자 분리 방식은 질화막을 마스크로 해서 반도체 기판 자체를 열산화시키기 때문에 공정이 간소해서 산화막의 소자 응력 문제가 적고, 생성되는 산화막 질이 좋다는 큰 이점이 있다. 그러나, LOCOS 소자 분리 방식을 이용하면 소자 분리 영역이 차지하는 면적이 크기 때문에 미세화에 한계가 있을 뿐만 아니라, 버즈 비크(bird's beak)가 발생하는 문제가 있다.LOCOS (Local Oxidation Of Silicon) device isolation method is used as a semiconductor device isolation method. Since the LOCOS device isolation method thermally oxidizes the semiconductor substrate itself using a nitride film as a mask, the process is simple and there is a great advantage that the element stress problem of the oxide film is small, and the oxide film quality produced is good. However, when the LOCOS device isolation method is used, the area of the device isolation region is large, thereby limiting the miniaturization and causing a bird's beak.
이러한, 문제를 해결하기 위해 LOCOS 소자 분리 방식을 대체하는 소자 분리 기술로서 최근에는 0.25㎛ 테크놀로지(Technology) STI(Shallow Trench Isolation) 소자 분리 방식이 널리 사용되고 있다. STI 소자 분리 방식은 반응성 이온 식각(Reactive Ion Etching; RIE)이나 플라즈마 식각과 같은 건식 식각 기술을 사용하여 반도체 기판 내에 트랜치를 형성하고, 이 트랜치에 절연막을 채우는 방법으로, 반도체 기판 내에 트랜치를 만들어 절연물을 집어 넣기 때문에 버즈 비크와 관련된 문제가 없어진다. 또한, 절연막이 채워진 트랜치는 표면을 평탄하게 하므로 소자 분리 영역이 차지하는 면적이 작아서 미세화에 유리한 방법이다.In order to solve such a problem, a 0.25 μm technology STI (Shallow Trench Isolation) device isolation method has been widely used as a device isolation technology to replace the LOCOS device isolation method. STI device isolation is a method of forming trenches in a semiconductor substrate by using dry etching techniques such as reactive ion etching (RIE) or plasma etching, and filling the trench with an insulating film. The problem is eliminated because of the Buzz Beek. In addition, since the trench filled with the insulating film has a flat surface, the area occupied by the device isolation region is small, which is advantageous for miniaturization.
도 1a 내지 1g는 종래 기술에 따른 반도체 소자의 소자 분리막 형성 방법을 설명하기 위해 도시한 반도체 소자의 단면도이다.1A to 1G are cross-sectional views of a semiconductor device for explaining a method of forming a device isolation film of a semiconductor device according to the prior art.
도 1a를 참조하면, 반도체 기판(10) 상부 표면의 결정 결함 및 표면 처리를 위해 고온에서 건식 또는 습식 산화방식을 실시하여 반도체 기판(10) 상에 140Å의 두께로 패드 산화막(12)을 형성한다. 이어서, 상기 패드 산화막(12) 상에 LP-CVD(Low Pressure Chemical Vapor Deposition) 방법으로 1000Å 정도의 두께로 패드 질화막(14)을 형성한다. 한편, 반도체 기판(10)에 대해 패드 산화막(12)을 형성하기전 DHF(Diluted HF; 50:1의 비율로 H20로 희석된 HF용액)을 이용한 전처리 세정공정을 실시하여 반도체 기판(10)을 세정한다.Referring to FIG. 1A, a pad oxide film 12 is formed on the semiconductor substrate 10 to have a thickness of 140 Å by performing dry or wet oxidation at a high temperature for crystal defects and surface treatment of the upper surface of the semiconductor substrate 10. . Subsequently, the pad nitride layer 14 is formed on the pad oxide layer 12 by a low pressure chemical vapor deposition (LP-CVD) method with a thickness of about 1000 GPa. Before the pad oxide film 12 is formed on the semiconductor substrate 10, a pretreatment cleaning process using DHF (diluted HF; HF solution diluted with H 2 0 at a ratio of 50: 1) is performed to perform the semiconductor substrate 10. )).
도 1b를 참조하면, 아이솔레이션(ISO) 마스크를 이용한 STI 공정을 실시하여 상기 패드 질화막(14) 및 패드 산화막(12)을 포함한 반도체 기판(10)의 소정 부위를 식각하여 반도체 기판(10) 내에 3500Å의 깊이로 트랜치(16)를 형성한다. 이로써, 반도체 기판(10)은 활성 영역과 소자 분리 영역으로 분리된다.Referring to FIG. 1B, a predetermined portion of the semiconductor substrate 10 including the pad nitride layer 14 and the pad oxide layer 12 is etched by performing an STI process using an isolation (ISO) mask to produce 3500 내에 in the semiconductor substrate 10. Form trench 16 to a depth of. As a result, the semiconductor substrate 10 is separated into an active region and an element isolation region.
도 1c를 참조하면, 트랜치(16) 저면의 모서리 부위와 패드 산화막(12)과 접촉되는 모서리 부위를 라운딩(Rounding) 처리하기 위해 건식 또는 습식 산화방식으로 트랜치(16)의 내부면의 실리콘을 산화시켜 월 산화막(18)을 형성한다. 한편, 월산화막(18)을 형성하기 전에 트랜치(16)의 내부면에 형성된 자연산화막을 제거하기 위해 DHF 용액을 이용한 전처리 세정공정을 실시한다.Referring to FIG. 1C, silicon of the inner surface of the trench 16 is oxidized by dry or wet oxidation to round the corner portions of the bottom surface of the trench 16 and the corner portions contacting the pad oxide layer 12. To form a month oxide film 18. Meanwhile, before forming the monthly oxide film 18, a pretreatment cleaning process using a DHF solution is performed to remove the native oxide film formed on the inner surface of the trench 16.
도 1d 및 1e를 참조하면, 전체 구조 상부에 트랜치(16) 내부에 보이드(Void)가 발생하지 않도록 갭 필링(Gap filling) 공정으로 실시하여 HDP(High Density Plasma) 산화막(20)을 형성한다. 이어서, 패드 질화막(14)을 식각 베리어층(Stop barrier)으로 평탄화 공정(CMP; Chemical mechanical pholishing)을 실시하여 HDP 산화막(20)을 연마하여 패드 질화막(14)을 경계로 HDP 산화막(20)을 고립시킨다.1D and 1E, the HDP (High Density Plasma) oxide film 20 is formed by performing a gap filling process so that voids do not occur inside the trench 16 over the entire structure. Subsequently, the pad nitride layer 14 is subjected to a planarization process (CMP; chemical mechanical pholishing) with an etch barrier layer, thereby polishing the HDP oxide layer 20 so that the HDP oxide layer 20 is bordered on the pad nitride layer 14. Isolate.
도 1f 및 1g를 참조하면, 전체 구조 상부에 패드 산화막(12)을 식각 베리어층으로 H3PO4(인산) 딥 아웃(Dip out)을 이용한 스트립공정을 실시하여 패드 질화막(14)을 제거한다. 이로써, 상부 구조가 돌출 형태를 갖는 HDP 산화막(20)이 형성된다. 이어서, 전체 구조 상부에 HF 딥 아웃을 이용한 세정공정을 실시하여 패드 산화막(12)을 제거하는 동시에 HDP 산화막(20)의 돌출부를 소정 폭을 갖도록 식각하여 소자 분리막(22)을 형성한다.Referring to FIGS. 1F and 1G, the pad nitride layer 14 is removed by using a pad oxide layer 12 on the entire structure by using H 3 PO 4 (phosphate) dip out as an etch barrier layer. . As a result, the HDP oxide film 20 having the upper structure protruding is formed. Subsequently, a cleaning process using an HF dip out is performed on the entire structure to remove the pad oxide layer 12 and to etch the protrusion of the HDP oxide layer 20 to have a predetermined width to form the device isolation layer 22.
이와 같이, 종래 기술의 STI 소자 분리 방식에서는 모든 공정 전에 HF 용액을 이용한 전처리 세정공정이 실시됨에 따라 트랜치 모서리 부위의 HDP 산화막이 오버 식각(Over Etch)되어 침식되는 현상이 발생한다. 이렇게 침식된 트랜치 모서리 부위로 전기장(Electric Field; EF)이 집중되어 소자의 비정상적인 동작, 예를 들어, 험프(Hump) 및 역 좁은 폭 효과(Inverse narrow width effect)를 유발한다.As described above, in the prior art STI device isolation method, as the pretreatment cleaning process using the HF solution is performed before all the processes, the HDP oxide layer of the trench edge portion is over-etched and eroded. The electric field (EF) is concentrated at the eroded trench edges, causing abnormal operation of the device, for example, the Hump and Inverse narrow width effects.
따라서, 본 발명은 상기의 문제를 해결하기 위해 안출된 것으로, 아이솔레이션(Isolation)을 위해 사용되는 패드 질화막 대신에 비정질 실리콘층을 형성한 후 라운딩 산화공정을 실시하여 트랜치 모서리 부위의 실리콘을 충분히 산화시켜 트렌치 모서리 부위에서 발생하는 모트(Moat)를 억제함으로써 소자의 비 정상적인 동작에 따른 소자 특성을 개선할 수 있는 반도체 소자의 소자 분리막 형성 방법을 제공하는데 그 목적이 있다.Accordingly, the present invention has been made to solve the above problem, and instead of forming a pad nitride film used for isolation, an amorphous silicon layer is formed, followed by a rounding oxidation process to sufficiently oxidize silicon in the trench corners. It is an object of the present invention to provide a method for forming a device isolation layer of a semiconductor device capable of improving device characteristics due to abnormal operation of the device by suppressing a moat generated at a corner of a trench.
도 1a 내지 1g는 종래 기술에 따른 반도체 소자의 소자 분리막 형성 방법을 설명하기 위해 도시한 반도체 소자의 단면도이다.1A to 1G are cross-sectional views of a semiconductor device for explaining a method of forming a device isolation film of a semiconductor device according to the prior art.
도 2a 내지 2g는 본 발명에 따른 반도체 소자의 소자 분리막 형성 방법을 설명하기 위해 도시한 반도체 소자의 단면도이다.2A through 2G are cross-sectional views of a semiconductor device for explaining the method of forming a device isolation film of the semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
10, 100 : 반도체 기판 12, 102 : 패드 산화막10, 100: semiconductor substrate 12, 102: pad oxide film
14 : 패드 질화막 16, 106 : 트랜치14 pad nitride film 16, 106 trench
18, 108 : 월 산화막 20, 112 : HDP 산화막18, 108: month oxide film 20, 112: HDP oxide film
22, 114 : 소자 분리막 104 : 비정질 실리콘층22, 114: device isolation film 104: amorphous silicon layer
110 : 실리콘 산화막110: silicon oxide film
본 발명은 반도체 기판 상에 패드 산화막을 형성하는 단계; 상기 패드 산화막 상에 비정질 실리콘층을 형성하는 단계; 상기 반도체 기판에 트랜치를 형성하는 단계; 상기 트랜치의 내부면과 상기 비정질 실리콘층에 산화막을 형성하기 위해 산화공정을 실시하는 단계; 전체 구조 상부에 트랜치 절연막을 증착한 후 평탄화 공정을 실시하여 상기 트랜치 절연막을 고립시키는 단계; 및 상기 비정질 실리콘층을 제거한 후 세정공정을 실시하여 소자 분리막을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.The present invention comprises the steps of forming a pad oxide film on a semiconductor substrate; Forming an amorphous silicon layer on the pad oxide film; Forming a trench in the semiconductor substrate; Performing an oxidation process to form an oxide film on the inner surface of the trench and the amorphous silicon layer; Depositing a trench insulating film over the entire structure and performing a planarization process to isolate the trench insulating film; And removing the amorphous silicon layer to perform a cleaning process to form an isolation layer.
이하 첨부된 도면을 참조하여 본 발명의 바람직한 실시 예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2g는 본 발명의 실시예에 따른 STI 소자 분리 방식을 이용한 반도체 소자의 소자 분리막 형성 방법을 설명하기 위해 도시한 반도체 소자의 단면도이다2A through 2G are cross-sectional views of a semiconductor device for explaining a method of forming a device isolation layer of a semiconductor device using an STI device isolation method according to an exemplary embodiment of the present invention.
도 2a를 참조하면, 반도체 기판(100) 상부 표면의 결정 결함 및 표면 처리를 위해 고온에서 건식 또는 습식 산화방식을 실시하여 반도체 기판(100) 상에 80Å 내지 200Å의 두께로 패드 산화막(12)을 형성한다. 이어서, 상기 패드 산화막(12) 상에 반도체 기판(100)의 실리콘(Si)보다 산화율(Oxidation Rate)이 빠른 비정질 실리콘층(104)을 1200 내지 2000Å의 두께로 형성한다.Referring to FIG. 2A, the pad oxide layer 12 is formed on the semiconductor substrate 100 at a thickness of 80 kPa to 200 kPa by performing a dry or wet oxidation method at a high temperature for crystal defects and surface treatment of the upper surface of the semiconductor substrate 100. Form. Subsequently, an amorphous silicon layer 104 having an oxidation rate faster than that of silicon (Si) of the semiconductor substrate 100 is formed on the pad oxide layer 12 to a thickness of 1200 to 2000 GPa.
한편, 반도체 기판(100)에 대해 패드 산화막(102)을 형성하기전 DHF(Diluted HF; 50:1의 비율로 H20로 희석된 HF용액)을 이용한 전처리 세정공정을 실시하여 반도체 기판(100)을 세정한다.Before the pad oxide layer 102 is formed on the semiconductor substrate 100, a pretreatment cleaning process using DHF (Diluted HF; HF solution diluted with H 2 0 at a ratio of 50: 1) is performed to perform the semiconductor substrate 100. )).
도 2b를 참조하면, 아이솔레이션(ISO) 마스크를 이용한 STI 공정을 실시하여 상기 비정질 실리콘층(104) 및 패드 산화막(102)을 포함한 반도체 기판(100)의 소정 부위를 식각하여 반도체 기판(100) 내에 3500Å의 깊이로 트랜치(106)를 형성한다. 이로써, 반도체 기판(100)은 활성 영역과 소자 분리 영역으로 분리된다.Referring to FIG. 2B, a predetermined portion of the semiconductor substrate 100 including the amorphous silicon layer 104 and the pad oxide layer 102 is etched by performing an STI process using an isolation (ISO) mask to etch the inside of the semiconductor substrate 100. The trench 106 is formed to a depth of 3500 kPa. As a result, the semiconductor substrate 100 is separated into an active region and a device isolation region.
도 2c를 참조하면, 트랜치(106) 저면의 모서리 부위와 패드 산화막(102)과 접촉되는 모서리 부위를 라운딩(Rounding) 처리하여 200Å의 두께로 측벽 산화막(108)을 형성하는 동시에 상기 비정질 실리콘층(104) 상에 실리콘 산화막(110)을 형성하기 위해 산소(O2)를 이용한 건식 산화방식을 실시한다. 한편,측벽 산화막(108)을 형성하기 전에 트랜치(106)의 내부면에 형성된 자연산화막을 제거하기 위해 DHF 용액을 이용한 전처리 세정공정을 실시한다.Referring to FIG. 2C, the edge portion of the bottom surface of the trench 106 and the edge portion in contact with the pad oxide layer 102 are rounded to form a sidewall oxide layer 108 having a thickness of 200 μs. In order to form the silicon oxide film 110 on the 104, a dry oxidation method using oxygen (O 2 ) is performed. On the other hand, before the side wall oxide film 108 is formed, a pretreatment cleaning process using a DHF solution is performed to remove the native oxide film formed on the inner surface of the trench 106.
도 2d를 참조하면, 전체 구조 상부에 트랜치(106) 내부에 보이드(Void)가 발생하지 않도록 HDPCVD(High Density Plasma Chemical Vapor Deposition) 방식으로 갭 필링(Gap filling)하여 트랜치 절연막용으로 HDP(High Density Plasma) 산화막(112)을 형성한다.Referring to FIG. 2D, gap filling is performed by HDPCVD (High Density Plasma Chemical Vapor Deposition) to prevent voids from occurring in the trench 106 in the upper portion of the entire structure. Plasma) oxide film 112 is formed.
도 2e를 참조하면, CMP(Chemical mechanical pholishing)를 이용한 평탄화 공정을 실시하여 비정질 실리콘층(104)이 600 내지 1400Å의 두께로 잔재하도록 HDP 산화막(112), 실리콘 산화막(110) 및 비정질 실리콘층(104)을 연마하여 비정질 실리콘층(104)을 경계로 HDP 산화막(112)을 고립시킨다.Referring to FIG. 2E, the planarization process using chemical mechanical pholishing (CMP) is performed to leave the amorphous silicon layer 104 at a thickness of 600 to 1400 Pa. 104 is polished to isolate the HDP oxide film 112 at the boundary of the amorphous silicon layer 104.
도 2f를 참조하면, 전체 구조 상부에 패드 산화막(102)을 식각 베리어층으로 H3PO4(인산) 딥 아웃(Dip out)을 이용한 스트립공정을 실시하여 비정질 실리콘층(104)을 제거한다. 이로써, 상부 구조가 돌출 형태를 갖는 HDP 산화막(112)이 형성된다.Referring to FIG. 2F, the amorphous silicon layer 104 is removed by performing a strip process using a H 3 PO 4 (phosphate) dip out as an etch barrier layer using the pad oxide layer 102 on the entire structure. As a result, the HDP oxide film 112 having the upper structure protruding is formed.
도 2g를 참조하면, 전체 구조 상부에 HF 딥 아웃을 이용한 세정공정을 실시하여 패드 산화막(102)을 제거하는 동시에 HDP 산화막(112)의 돌출부를 식각하여 도시된 'B'와 같은 프로파일(Profile)을 갖는 소자 분리막(114)을 형성한다.Referring to FIG. 2G, a cleaning process using HF dip out is performed on the entire structure to remove the pad oxide layer 102 and simultaneously etch a protrusion of the HDP oxide layer 112. An isolation film 114 having a film is formed.
상기에서 설명한 바와 같이, 본 발명은 아이솔레이션(Isolation)을 위해 사용되는 패드 질화막 대신에 비정질 실리콘층을 형성한 후 라운딩 산화공정을 실시하여 트랜치 모서리 부위의 실리콘을 충분히 산화시켜 트렌치 모서리 부위에서 발생하는 모트(Moat)를 억제함으로써 소자의 비 정상적인 동작에 따른 소자 특성을 개선할 수 있다.As described above, the present invention forms an amorphous silicon layer instead of the pad nitride film used for isolation, and then performs a rounding oxidation process to sufficiently oxidize silicon in the trench corners to generate a mortity in the trench corners. By suppressing (Moat), it is possible to improve device characteristics due to abnormal operation of the device.
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| KR100519648B1 (en) * | 2003-12-10 | 2005-10-07 | 동부아남반도체 주식회사 | Method For Manufacturing Semiconductor Devices |
| KR100671667B1 (en) * | 2004-06-14 | 2007-01-18 | 주식회사 하이닉스반도체 | Method of forming an isolation layer in a semiconductor device |
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| KR0146629B1 (en) * | 1994-12-29 | 1998-11-02 | 김주용 | Method for forming field oxide film of semiconductor device |
| KR19980084300A (en) * | 1997-05-22 | 1998-12-05 | 윤종용 | Device isolation film formation method using a reflection suppression film |
| KR100318461B1 (en) * | 1998-10-13 | 2002-02-19 | 박종섭 | Semiconductor device isolation method |
| KR100559042B1 (en) * | 1999-10-07 | 2006-03-10 | 주식회사 하이닉스반도체 | Method of shallow trench isolation film in a semiconductor device |
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| KR100671667B1 (en) * | 2004-06-14 | 2007-01-18 | 주식회사 하이닉스반도체 | Method of forming an isolation layer in a semiconductor device |
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