KR20050063338A - Method for manufacturing isolation of semiconductor device - Google Patents
Method for manufacturing isolation of semiconductor device Download PDFInfo
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- KR20050063338A KR20050063338A KR1020030094730A KR20030094730A KR20050063338A KR 20050063338 A KR20050063338 A KR 20050063338A KR 1020030094730 A KR1020030094730 A KR 1020030094730A KR 20030094730 A KR20030094730 A KR 20030094730A KR 20050063338 A KR20050063338 A KR 20050063338A
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- 238000000034 method Methods 0.000 title claims abstract description 50
- 238000002955 isolation Methods 0.000 title claims description 29
- 239000004065 semiconductor Substances 0.000 title claims description 22
- 238000004519 manufacturing process Methods 0.000 title description 3
- 150000004767 nitrides Chemical class 0.000 claims abstract description 40
- 239000000758 substrate Substances 0.000 claims abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 10
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 10
- 239000010703 silicon Substances 0.000 claims abstract description 10
- 238000000151 deposition Methods 0.000 claims abstract description 6
- 238000000059 patterning Methods 0.000 claims abstract description 4
- 238000005498 polishing Methods 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 3
- 238000004140 cleaning Methods 0.000 abstract description 5
- 238000005137 deposition process Methods 0.000 abstract 1
- 230000005684 electric field Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Element Separation (AREA)
Abstract
본 발명은 상기와 같은 목적을 실현하기 위한 본 발명은 실리콘 기판에 패드 산화막 및 패드 질화막을 증착하는 단계와； 상기 패드 질화막을 패터닝하여 패터닝된 패드 질화막을 식각마스크로 실리콘 기판에 소정 깊이의 트렌치를 형성하는 단계와； 상기 트렌치 내부를 매립 산화막으로 매립하는 단계와； 상기 매립 산화막에 대한 에치백 공정으로 트렌치 내부에 매립 산화막이 소정 깊이 식각 되도록 하는 단계와； 상기 에치백 공정후에 매립 질화막을 증착한 후 평탄화 공정을 진행하는 단계와； 상기 패드 질화막을 제거하는 단계를 포함하여 구성됨으로써，STI를 매립 산화막과 매립 질화막의 이중막으로 증착하고 매립 산화막을 연마 정지막으로 매립 질화막을 평탄화 하여 STI 상부를 질화막으로 절연시켜 후속 습식 공정 또는 세정 공정시에 STI 상부의 손실을 방지할 수 있다． The present invention for achieving the above object is a step of depositing a "pad" oxide film and a "pad nitride" film on a silicon substrate; "pattern" said pad nitride film by patterning said pad nitride film to a silicon substrate with a predetermined depth of etch mask; A step of forming and burying the inside of the trench with an oxide film; and a step of etching the oxide film into the trench to etch the inside of the trench in a predetermined depth; and depositing the nitride film after the etch back deposition process. And a step of carrying out the post-planarization process; and the step of removing the pad nitride film. The buried nitride film can be leveled with a stop film to insulate the top of the STI with a nitride film to prevent loss of the top of the STI during subsequent wet or cleaning processes.
Description
본 발명은 반도체 소자의 소자 분리막 형성 방법에 관한 것으로， 보다 상세하게는 STI 상부의 산화막 손실에 따른 모트 발생을 방지함으로써 소자의 험프 현상 및 문턱 전압 저하 현상을 방지할 수 있는 반도체 소자의 소자 분리막 형성 방법에 관한 것이다.The present invention relates to a method of forming a device isolation layer of a semiconductor device, and more specifically, to forming a device isolation layer of a semiconductor device, which can prevent the hum phenomena and the threshold voltage drop of the device by preventing the occurrence of a mottling caused by the loss of the oxide film on the top of the STI. It's about how.
일반적으로 반도체 기판 상에 트랜지스터와 커패시터등 반도체 소자를 형성하기 위하여 기판에 소자 분리막을 형성함으로써 전기적으로 통전이 가능한 활성 영역(Active region)과 전기적으로 통전되는 것을 방지하고 소자를 서로 분리하도록 하는 소자분리 영역(Isolation region)을 형성하게 된다.Generally, in order to form a semiconductor device such as a transistor and a capacitor on a semiconductor substrate, a device isolation layer is formed on the substrate to prevent the device from being electrically connected to an active region that is electrically energized and to separate the devices from each other. It forms an isolation region.
소자 분리 공정은 크게 반도체 기판에 패드 산화막과 질화막을 마스크 공정으로 질화막을 식각하고 그 식각된 부위에 산화 공정을 진행하여 소자분리막을 형성하는 LOCOS(Local Oxidation of Silicon) 공정과, 반도체 기판에 일정한 깊이를 갖는 트렌치를 형성하고 나서 이 트렌치에 산화 물질을 증착시키고 CMP 공정을 통해 산화막의 불필요한 부분을 식각하여 소자 분리막을 형성하는 STI(Shallow Trench Isolation) 공정이 있다.The device isolation process is largely a local oxide of silicon (LOCOS) process in which a nitride oxide is etched using a pad oxide film and a nitride film on a semiconductor substrate and an oxidation process is performed on the etched portion to form a device isolation film. There is a STI (Shallow Trench Isolation) process in which an oxide material is deposited on the trench and then an unnecessary portion of the oxide film is etched through the CMP process to form an isolation layer.
LOCOS 공정은 장시간 고온 산화로 인하여 채널저지 이온의 측면 확산 및 측면 산화에 의해 소자의 전기적인 특성을 저하시키는 원인으로 작용하는 버즈 빅(Bird's Beak)이 발생하여 약 0.25㎛ 이하의 공정에는 한계가 있다. The LOCOS process has a limitation in the process of about 0.25 μm or less due to the occurrence of Bird's Beak, which acts as a cause of deterioration of the electrical characteristics of the device due to side diffusion and lateral oxidation of channel blocking ions due to prolonged high temperature oxidation. .
LOCOS의 이러한 문제점을 해결하기 위해 현재 0.25㎛ 이하의 미세 공정에서는 소자 분리 형성 방법으로 STI(Shallow Trench Isolation) 공정이 많이 사용되고 있다. 다면 상기 STI 공정 적용시에는 LOCOS의 단점인 버즈 빅은 발생하지 않고 절연 특성이 우수하지만, 탑 코너(Top Corner) 및 바텀 코너(Bottom Coener)에 스트레스가 집중되어 소자 특성이 저하되는 문제점이 있다.In order to solve this problem of LOCOS, the Shtre Trench Isolation (STI) process is widely used as a device isolation method in the micro process of 0.25 μm or less. When the STI process is applied, the Buzz big, which is a disadvantage of LOCOS, does not occur and the insulation property is excellent, but stress is concentrated on the top corner and the bottom corner, resulting in a deterioration of device characteristics.
또한, 트렌치의 탑코너 에서의 에지 모트의 발생으로 소자의 비정상적 동작을 유발하는 험프(HUMP), INWE 현상이 발생하는데 험프 현상은 액티브 코너에서 전기장의 집중으로 인해 생기는 현상이고, INWE(Inverse Narrow Width Effect)는 트랜지스터의 폭이 감소함에 따라 문턱 전압이 변화하는 현상이다.In addition, Hump and INWE phenomenon, which causes abnormal operation of the device, occurs due to edge mortity in the top corner of the trench. Hump phenomenon is caused by the concentration of electric field in the active corner, and INWE (Inverse Narrow Width) Effect) is a phenomenon in which the threshold voltage changes as the width of the transistor decreases.
이에 따라 현재 코너 라운딩을 개선하는 방안으로 STI (Shallow Trench Isolation) 식각시 탑 코너 라운딩을 하거나 CMP 후에 HDP 산화막의 밀도를 증가시키기 위한 어닐 공정을 통한 코너 라운딩 방법 등이 이용되고 있으나, 이러한 방법에 의해서도 STI의 탑코너에서 발생하는 에지 모트(Edge Moat)를 억제할 수 없는 문제점이 있었다.Accordingly, the corner rounding method through an annealing process to improve the top corner rounding during shallow trench isolation (STI) etching or to increase the density of the HDP oxide layer after CMP has been used as a method for improving corner rounding. There was a problem in that edge moat generated at the top corner of STI could not be suppressed.
이와 같은 종래 기술에 의한 반도체 소자의 소자 분리막 형성 공정시 발생하는 문제점을 아래에 도시된 도면을 통해 설명하면 다음과 같다.The problem occurring during the device isolation film forming process of the semiconductor device according to the related art will be described below with reference to the accompanying drawings.
도1은 종래 기술에 형성된 반도체 소자의 소자 분리막을 나타낸 도면으로, 여기에 도시된 바와 같이, 종래의 기술에 의한 소자 분리막 형성시 A와 같이 트렌치 탑코너의 에지 부위에 모트(Moat) 형상이 발생하며, 디자인 룰의 감소에 따라 INWE(Inverse Narrow Width Effect)로 인해 채널 영역에 게이트의 전기장이 A 부분과 같이 중첩되어 전계 효과 증가를 야기 시킨다. 이로 인하여 셀 트랜지스터에서 리프레시 특성이 저하될 뿐만 아니라 문턱 전압을 저하시켜, 누설 전류 발생을 야기시키는 문제점이 있었다. 1 is a view showing a device isolation film of a semiconductor device formed in the prior art, as shown here, in the formation of the device isolation film according to the prior art, a moat shape occurs in the edge portion of the trench top corner as shown in A In addition, as the design rule decreases, the inverse narrow width effect (INWE) causes the electric field of the gate to overlap with the A portion, causing an increase in the field effect. As a result, not only the refresh characteristics of the cell transistors are lowered, but also the threshold voltages are lowered, thereby causing leakage currents.
또한, 모트는 후속 세정 공정을 통하여 크기가 증가하게되며, LDD 식각 공정후에 STI 소자 분리막의 손실을 유발하여 STI 측벽을 노출시키게 된다. 이로 인하여 후속 실리사이드 공정시 액티브 측벽에 실리사이드가 형성되어 소오스/드레인 접합에서의 누설 전류 증가를 초래한다. In addition, the mort is increased in size through a subsequent cleaning process, which causes the loss of the STI device isolation layer after the LDD etching process to expose the STI sidewall. This results in the formation of silicide on the active sidewalls in subsequent silicide processes resulting in increased leakage current at the source / drain junction.
그리고, 스텍형 캐패시터를 적용하는 SoC 제품인 MXDL에서 스텍 캐패시터의 높이 만 비트라인 콘택의 깊이를 증가시키기 되어, 깊은 콘택 형성시 액티브와의 오정렬이 발생하에 되어 액티브 측벽에 텅스텐 플러그가 접합되어 누설 전류를 증가시키는 문제점이 있었다. In addition, only the height of the stack capacitor increases the depth of the bit line contact in the MXDL, an SoC product that employs a stack type capacitor, and when a deep contact is formed, misalignment with the active occurs, and a tungsten plug is bonded to the active sidewall to prevent leakage current. There was an issue to increase.
상기와 같은 문제점을 해결하기 위한 본 발명은 STI를 매립 산화막과 매립 질화막으로 형성하되 매립 산화막 상부를 질화막으로 절연시킴으로써， 후속 습식 공정 또는 세정 공정시에 STI 상부의 손실을 방지함으로써， 모트 발생을 억제할 수 있도록 하는 반도체 소자의 소자 분리막 형성 방법을 제공하기 위한 것이다. In order to solve the above problems, the present invention forms an STI with a buried oxide and a buried nitride, but insulates the upper part of the buried oxide with a nitride film to prevent the occurrence of suppression by preventing the loss of the upper part of the STI during the subsequent wet process or cleaning process. It is intended to provide a method of forming a device isolation layer of a semiconductor device that can be made possible.
상기와 같은 목적을 실현하기 위한 본 발명은 실리콘 기판에 패드 산화막 및 패드 질화막을 증착하는 단계와； 상기 패드 질화막을 패터닝하여 패터닝된 패드 질화막을 식각마스크로 실리콘 기판에 소정 깊이의 트렌치를 형성하는 단계와； 상기 트렌치 내부를 매립 산화막으로 매립하는 단계와； 상기 매립 산화막에 대한 에치백 공정으로 트렌치 내부에 매립 산화막이 소정 깊이 식각 되도록 하는 단계와； 상기 에치백 공정후에 매립 질화막을 증착한 후 평탄화 공정을 진행하는 단계와； 상기 패드 질화막을 제거하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 소자 분리막 형성 방법에 관한 것이다.The present invention for realizing the above object comprises the steps of depositing a pad oxide film and a pad nitride film on a silicon substrate; patterning the pad nitride film to form a patterned pad nitride film with an etching mask to form a trench of a predetermined depth. And the step of embedding the inside of the trench into the buried oxide film and the step of etching the buried oxide inside the trench to etch a predetermined depth deeply into the buried oxide film and depositing the nitride film after the buried process after the etch back process. The present invention relates to a method for forming a device isolation film for a semiconductor device, characterized by including a step of advancing and a step of removing the pad nitride film.
상기 본 발명에 의한 반도체 소자의 소자 분리막 형성 방법에 의하면， STI를 매립 산화막과 매립 질화막의 이중막으로 증착하고 매립 산화막을 연마 정지막으로 매립 질화막을 평탄화 하여 STI 상부를 질화막으로 절연시킴으로써， 후속 습식 공정 또는 세정 공정시에 STI 상부의 손실을 방지할 수 있다． According to the method for forming a device isolation film of a semiconductor device according to the present invention, STI is deposited into a double layer of a buried oxide film and a buried nitride film, and the buried oxide film is flattened with a polishing film by an insulating film, and then the upper surface of the STI is wetted by a nitriding film. It is possible to prevent the loss of the upper part of the STI during the process or cleaning process.
이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 설명한다. 또한 본 실시예는 본 발명의 권리범위를 한정하는 것은 아니고, 단지 예시로 제시된 것이며 종래 구성과 동일한 부분은 동일한 부호 및 명칭을 사용한다. Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is presented by way of example only and the same parts as in the conventional configuration using the same reference numerals and names.
도２a 내지 도２f는 본 발명에 의한 반도체 소자의 소자 분리막 형성 방법 제조 방법을 순차적으로 나타낸 공정 단면도이다．2A to 2F are cross-sectional views sequentially showing a method of forming a device isolation film and manufacturing method of a semiconductor device according to the present invention.
도２a에 도시된 바와 같이 실리콘 기판（２００）상에 후속 증착되는 패드 질화막과에 의한 실리콘 기판의 스트레스 완화용으로 패드 산화막(210)을 성장시킨 후에 그 상부에 패드 질화막(220)을 ２００∼１５００Å의 두께로 증착한다. 상기 패드 질화막(220)은 후속 트렌치 식각시 식각 마스크로 이용된다．이때，상기 패드 산화막（２１０）은 후속 매립 산화막 연마 공정시의 연마 정지막으로 이용하기 위하여 ５００∼１5００Å의 두께로 형성한다． As shown in FIG. 2A, the pad nitride film 210 is subsequently deposited on the silicon substrate 200 and the pad oxide film 210 is grown for the stress relief of the silicon substrate by the pad nitride film 200, and then the pad nitride film 220 is formed on the top of the film. Evaporate to the thickness of. The pad nitride film 220 is used as an etch mask in subsequent trench etching. The pad nitride oxide film 21 is formed to a thickness of 500 to 1500 to be used as a polishing polishing stop film during the subsequent buried buried oxide polishing process.
이어서, 상기 패드 질화막(220)에 대한 패터닝 공정을 진행하고 상기 패터닝된 패드 질화막(220)을 식각 마스크로 이용하여 패드 산화막을 식각한 후 연속하여 도２b에 도시된 바와 같이 실리콘 기판에 소정 깊이의 트렌치(230)를 형성한다.Subsequently, a patterning process is performed on the pad nitride film 220, the pad oxide film is etched using the patterned pad nitride film 220 as an etch mask, and subsequently, the pad nitride film 220 is continuously formed on the silicon substrate as shown in FIG. 2B. Form the trench 230.
그런 다음 상기 트렌치 식각 공정 시 실리콘기판(200)이 받은 데미지(damage)를 완화하기 위해 트렌치 내벽에 사이드월 산화막을 형성하는 공정을 더 진행할 수 있다． Then, the step of forming a sidewall oxide film on the inner wall of the trench may be further performed to alleviate the damage received by the silicon substrate 200 during the trench etching process.
이어서, 도２c에 도시된 바와 같이 상기 트렌치가 충분히 매립되도록 매립 산화막(240)을 증착한다. Next, as shown in FIG. 2C, a buried oxide film 240 is deposited to sufficiently fill the trench.
상기 매립 산화막(240)에 대해 전면 에치백 공정을 실시하여 도２d에 도시된 바와 같이 상기 매립 산화막이 트렌치 내부에 ３０００Å 두께 남도록 한다．The buried oxide film 240 is subjected to a full etch back process so that the buried oxide film remains 300 nm inside the trench as shown in FIG. 2D.
그후, 도２e에 도시된 바와 같이 매립 질화막（２５０）을 상기 결과물 전면에 １０００∼２０００Å 두께로 증착한다． Then, as shown in Fig. 2E, a buried nitride film 250 is deposited on the front surface of the resultant with a thickness of 100 to 200 thick.
그런 다음， 상기 패드 산화막（２１０）을 연마 정지막으로 이용하여 화학 기계적 연마 공정으로 상기 패드 질화막（２５０）을 평탄화한 후에 도 2f에 도시된 바와 같이 패드 질화막（２２０）을 HF 용액을 이용한 습식 식각 공정을 진행하여 제거한다． Then, using the above-mentioned pad oxide film (110) as a polishing stop film, and then using the chemical mechanical polishing process, after flattening the above-mentioned pad nitride film (25), the solution was prepared by etching the pad nitride film (20) as shown in Fig. 2f. Run the process to remove it.
이와 같이 본 발명에 의한 반도체 소자의 소자 분리막 형성 방법에 의하면，트렌치를 매립 산화막과 매립 질화막으로 매립하고 나서， 패드 산화막을 연마 정지막으로 이용한 평탄화 공정을 진행함으로써 매립 질화막으로 STI 상부를 절연시킴으로써， 패드 질화막 습식 식각 공정 및 세정 공정시에 발생할 수 있는 STI 모트를 원천 방지할 수 있다． As described above, according to the present invention, the method of forming a device isolation layer of a semiconductor device is carried out by filling a trench with a buried oxide film and a buried nitride film, and then filling the pad with the oxide film by using a flattening process as a polishing film to insulate the insulating film into the TI film. The pads can be used to prevent STI motors from occurring during wet etching and cleaning processes.
. .
상기한 바와 같이 본 발명은 STI 탑 코너부의 모트를 방지함으로써 액티브 에지의 전기장 집중에 의한 험프 현상을 방지할 수 있는 이점이 있다． As described above, the present invention has the advantage of preventing the hump phenomenon caused by the concentration of the electric field of the active edge by preventing the STI tower corner portion of the motor.
또한， 후속 습식 식각시에 STI 매립 산화막 손실에 따른 STI 측벽 살리사이드 생성을 방지함으로써 소오스／드레인 누설 전류를 억제할 수 있는 이점이 있다． In addition, there is an advantage in that the source / drain leakage current can be suppressed by preventing the formation of STI sidewall salicide due to STI buried oxide loss during subsequent wet etching.
또한， 액티브 탑 코너를 라운딩시킴으로써 액티브 탑 코너에서의 전기장 집중 현상을 방지함으로써 소자의 신뢰성을 향상시킬 수 있는 이점이 있다. In addition, by rounding the active top corner, there is an advantage that the reliability of the device can be improved by preventing electric field concentration at the active top corner.
도1은 종래 기술에 형성된 반도체 소자의 소자 분리막 형성 방법을 나타낸 도면이다．1 is a view showing a device isolation film forming method of a semiconductor device formed in the prior art.
도２a 내지 도２f는 본 발명에 의한 반도체 소자의 소자 분리막 형성 방법 제조 방법을 순차적으로 나타낸 공정 단면도이다． 2A to 2F are cross-sectional views sequentially showing a method of forming a device isolation film and manufacturing method of a semiconductor device according to the present invention.
- 도면의 주요부분에 대한 부호의 설명 - -Explanation of symbols for the main parts of the drawings-
200 ： 실리콘 기판 210 ： 패드 산화막200 ： Silicone Substrate 210 ： Pad Anodized film
220 ： 패드 질화막 230 ： 트렌치220 ： Pad nitride film 230 ： Trench
240 ： 매립 산화막 250 ： 매립 질화막 240 ： embedded oxidized film 250 ： embedded nitride film
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| US11257708B2 (en) | 2018-09-05 | 2022-02-22 | Samsung Electronics Co., Ltd. | Gap-fill layers, methods of forming the same, and semiconductor devices manufactured by the methods of forming the same |
| US11640922B2 (en) | 2018-09-05 | 2023-05-02 | Samsung Electronics Co., Ltd. | Gap-fill layers, methods of forming the same, and semiconductor devices manufactured by the methods of forming the same |
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