KR20030050680A - Method of fabricating semiconductor device with dual gate oxide - Google Patents
Method of fabricating semiconductor device with dual gate oxide Download PDFInfo
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- KR20030050680A KR20030050680A KR1020010081184A KR20010081184A KR20030050680A KR 20030050680 A KR20030050680 A KR 20030050680A KR 1020010081184 A KR1020010081184 A KR 1020010081184A KR 20010081184 A KR20010081184 A KR 20010081184A KR 20030050680 A KR20030050680 A KR 20030050680A
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28211—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer
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- H—ELECTRICITY
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
Abstract
Description
본 발명은 반도체장치의 제조 방법에 관한 것으로, 특히 듀얼 게이트산화막(Dual gate oxide)을 구비한 CMOS의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a CMOS having a dual gate oxide.
일반적으로 반도체장치의 게이트산화막으로 열(Thermally) 또는 급속열처리(Rapid thermally)에 의해 성장된 SiO2를 사용하고 있다. 최근에 반도체소자의 디자인룰이 감소함에 따라 게이트산화막의 두께는 SiO2의 터널링한계가 되는 25∼30Å이하로 줄어드는 추세에 있으며, 0.1㎛급 소자에서의 게이트산화막으로는 25∼30Å두께가 예상된다.In general, SiO 2 grown by thermally or rapid thermally is used as a gate oxide film of a semiconductor device. As the design rules of semiconductor devices decrease in recent years, the thickness of gate oxide films has tended to decrease below 25-30 kHz, which is the tunneling limit of SiO 2 , and a thickness of 25-30 kHz is expected as a gate oxide film in 0.1 占 퐉 devices. .
그러나, 셀트랜지스터(Cell transistor)의 경우 리프레쉬(refresh) 등의 문제로 인하여 주변회로영역(peri)의 트랜지스터보다 높은 문턱전압(threshold voltage; Vt)이 요구됨에 따라 높은 게이트 전압이 가해지고 결과적으로 주변회로영역의 트랜지스터보다는 전기적 특성이 열화되는 단점이 나타난다.However, in the case of a cell transistor, a higher gate voltage is applied as a higher threshold voltage (Vt) than a transistor in the peripheral circuit region (peri) due to a problem such as refreshing, resulting in a peripheral voltage. The disadvantage is that the electrical characteristics deteriorate rather than the transistors in the circuit area.
셀영역의 트랜지스터 특성을 향상시키기 위해서는 셀영역의 트랜지스터의 게이트산화막의 두께를 증가시킬 필요가 있는데 이를 위해 제안된 것이 CMOS 공정에 의한 듀얼 게이트산화막(Dual gate dielectric)의 제조 방법이다.In order to improve the transistor characteristics of the cell region, it is necessary to increase the thickness of the gate oxide layer of the transistor of the cell region. A proposed method for manufacturing the dual gate dielectric layer by a CMOS process is proposed.
이러한 듀얼 게이트산화막의 종래기술로는 여러 가지가 있는데 최근에 많이 연구되는 방법은 일정 부분만 게이트산화막을 제거하고 다시 산화시켜 듀얼 게이트산화막을 형성시키는 제1방법과 일정 부분만 질소(nitrogen)와 같은 원소를 이온주입(implant)하여 게이트산화막의 성장을 느리게 하여 듀얼 게이트산화막을 형성시키는 제2방법, Si 및 Ge와 같은 원소를 이온주입하여 게이트산화막의 성장을 증가시켜 듀얼 게이트산화막을 형성하는 제3방법 등이 있다.There are a number of conventional techniques for such a dual gate oxide film. Recently, many researches have been made on the first method of forming a dual gate oxide film by removing only a portion of the gate oxide film and oxidizing it, and only a portion of nitrogen, such as nitrogen. A second method of forming a dual gate oxide film by slowing the growth of the gate oxide film by implanting elements, and a third method of forming a dual gate oxide film by increasing the growth of the gate oxide film by ion implanting elements such as Si and Ge Method and the like.
그러나, 상술한 종래기술 중 제1방법은 듀얼 게이트산화막을 형성시키기 위해 두 번의 높은 열공정을 실시하기 때문에 반도체기판의 표면이 손상되는 문제점이 있고, 제2방법 및 제3방법은 질소, Si, Ge의 이온주입으로 인해 반도체기판이 손상되는 문제점이 있다.However, since the first method of the above-described conventional technique performs two high thermal processes to form a dual gate oxide film, the surface of the semiconductor substrate is damaged, and the second and third methods are nitrogen, Si, There is a problem that the semiconductor substrate is damaged by the ion implantation of Ge.
특히, 반도체기판이 손상될 경우 채널 이동도(channel mobility) 등의 열화를 가져올 수도 있다.In particular, when the semiconductor substrate is damaged, deterioration such as channel mobility may occur.
본 발명은 상기한 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 두 번의 열공정 및 이온주입에 따른 공정의 복잡성 및 반도체기판의 손상을 억제하도록 하는데 적합한 듀얼 게이트산화막을 구비한 반도체장치의 제조 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and has a dual gate oxide film suitable for suppressing the damage of the semiconductor substrate and the complexity of the process caused by two thermal processes and ion implantation. The purpose is to provide.
도 1a 내지 도 1c는 본 발명의 제1실시예에 따른 듀얼 게이트산화막의 형성 방법을 도시한 공정 단면도,1A to 1C are cross-sectional views illustrating a method of forming a dual gate oxide film according to a first embodiment of the present invention;
도 2a 내지 도 2d는 본 발명의 제2실시예에 따른 반도체장치의 제조 방법을 도시한 공정 단면도.2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
21: 반도체기판 22 : 필드산화막21: semiconductor substrate 22: field oxide film
23 : 희생산화막 24 : 마스크23: sacrificial oxide film 24: mask
25 : 질소 주입층 26a : 박막 게이트산화막25 nitrogen injection layer 26a thin film gate oxide film
26b : 후막 게이트산화막26b thick film gate oxide film
상기의 목적을 달성하기 위한 본 발명의 듀얼 게이트산화막의 형성 방법은 반도체기판상에 희생산화막을 형성하는 단계, 상기 희생산화막의 일측을 디커플드플라즈마질화처리하여 상기 희생산화막 일측 하부의 상기 반도체기판 표면을 질화시키는 단계, 상기 희생산화막을 제거하여 상기 반도체기판 표면을 노출시키는 단계, 및 상기 노출된 반도체기판 표면을 열산화시켜 서로 다른 두께를 갖는 게이트산화막을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.A method of forming a dual gate oxide film of the present invention for achieving the above object comprises the steps of forming a sacrificial oxide film on a semiconductor substrate, and decoupled plasma nitriding one side of the sacrificial oxide film to the lower side of the semiconductor substrate. Nitriding a surface, removing the sacrificial oxide film to expose the surface of the semiconductor substrate, and thermally oxidizing the exposed surface of the semiconductor substrate to form gate oxide films having different thicknesses. do.
그리고, 본 발명의 반도체장치의 제조 방법은 셀영역과 주변회로영역이 정의된 반도체기판상에 희생산화막을 형성하는 단계, 상기 주변회로영역측 상기 희생산화막을 노출시키는 마스크층을 형성하는 단계, 상기 노출된 상기 희생산화막을 디커플드플라즈마질화처리하여 상기 주변회로영역측 상기 반도체기판 표면을 질화시키는 단계, 상기 마스크층 및 상기 희생산화막을 제거하여 상기 반도체기판 표면을 노출시키는 단계, 상기 노출된 반도체기판 표면을 열산화시켜 듀얼 게이트산화막을 형성하는 단계, 상기 듀얼 게이트산화막상에 각각 게이트전극을 형성하는 단계, 및 상기 게이트전극 하측의 상기 반도체기판에 소스/드레인 영역을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.The method of manufacturing a semiconductor device of the present invention includes forming a sacrificial oxide film on a semiconductor substrate in which a cell region and a peripheral circuit region are defined, and forming a mask layer exposing the sacrificial oxide film on the peripheral circuit region side. Denitrifying the exposed sacrificial oxide film to nitride the surface of the semiconductor substrate on the peripheral circuit region side, and removing the mask layer and the sacrificial oxide film to expose the surface of the semiconductor substrate, the exposed semiconductor Thermally oxidizing a substrate surface to form a dual gate oxide film, forming a gate electrode on the dual gate oxide film, and forming a source / drain region on the semiconductor substrate under the gate electrode. It is characterized by.
바람직하게, 상기 희생산화막 일측의 디커플드플라즈마질화처리는, 5mtorr∼50mtorr의 진공도 및 0℃∼700℃을 유지한 상태에서 100W∼2000W의 RF 소스파워를 인가하면서 10초∼300초동안 이루어지고, 그리고, 상기 디커플드플라즈마질화처리는 N2, N2O, NO 및 NH3로 이루어진 그룹중에서 선택되는 하나의 분위기기체에서 이루어짐을 특징으로 한다.Preferably, the decoupled plasma nitriding treatment on one side of the sacrificial oxide film is performed for 10 seconds to 300 seconds while applying an RF source power of 100 W to 2000 W while maintaining a vacuum degree of 5 mtorr to 50 mtorr and 0 ° C to 700 ° C. And, the decoupled plasma nitriding treatment is characterized in that it is made in one atmosphere gas selected from the group consisting of N 2 , N 2 O, NO and NH 3 .
바람직하게, 상기 희생산화막은 3Å∼25Å 두께를 갖는 것을 특징으로 한다.Preferably, the sacrificial oxide film is characterized in that it has a thickness of 3 ~ 25Å.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 1a 내지 도 1c는 본 발명의 제1실시예에 따른 듀얼 게이트산화막의 형성 방법을 도시한 공정 단면도이다.1A to 1C are cross-sectional views illustrating a method of forming a dual gate oxide film according to a first embodiment of the present invention.
도 1a에 도시된 바와 같이, 반도체기판(11)상에 3Å∼25Å 두께의 희생산화막(12)을 형성한 후, 희생산화막(12)상에 감광막을 도포하고 노광 및 현상으로 패터닝하여 희생산화막(12)의 일부분을 노출시키는 마스크(13)를 형성한다.As shown in FIG. 1A, after the sacrificial oxide film 12 having a thickness of 3 to 25 GPa is formed on the semiconductor substrate 11, a sacrificial oxide film 12 is coated on the sacrificial oxide film 12 and patterned by exposure and development. A mask 13 is formed which exposes a portion of 12).
여기서, 희생산화막(12)의 두께를 3Å∼25Å으로 한정한 것은 두께가 3Å미만일 경우는 후속 디커플드플라즈마질화처리시 반도체기판 표면이 손상되는 문제가 있고, 두께가 25Å보다 두꺼우면 후속 디커플드플라즈마질화처리시 산화속도를 감소시키는 원소인 질소(nitrogen; N)를 실리콘기판으로 확산시킬 수 없다.In this case, the thickness of the sacrificial oxide film 12 is limited to 3 GPa to 25 GPa. If the thickness of the sacrificial oxide film 12 is less than 3 GPa, there is a problem in that the surface of the semiconductor substrate is damaged during the subsequent decoupled plasma nitriding treatment. Nitrogen (N), an element that reduces oxidation rate during deplasmitization, cannot diffuse to silicon substrates.
다음으로, 마스크(13)에 의해 노출된 희생산화막(12)의 일부분을 질소(N)가 함유된 분위기기체에서 디커플드플라즈마질화처리(Decoupled Plasma nitridation; DPN)한다.Next, a portion of the sacrificial oxide film 12 exposed by the mask 13 is decoupled plasma nitridation (DPN) in an atmosphere gas containing nitrogen (N).
이 때, 디커플드플라즈마질화처리에 적용되는 분위기기체는 N2, N2O, NO 및 NH3로 이루어진 그룹중에서 선택되는 하나를 이용한다.At this time, the atmosphere gas applied to the decoupled plasma nitriding treatment uses one selected from the group consisting of N 2 , N 2 O, NO and NH 3 .
예컨대 분위기기체로 N2를 이용하는 경우, N2를 10sccm∼1000sccm의 유량으로 주입시키고, 5mtorr∼50mtorr의 진공도를 유지한 상태에서 반도체기판(11)은 0℃∼700℃을 유지하며, 100W∼2000W의 RF 소스파워를 인가하면서 10초∼300초동안 디커플드플라즈마질화처리한다.For example, the case of using the N 2 gas to the atmosphere, and injecting the N 2 at a flow rate of 10sccm~1000sccm, the semiconductor substrate 11 while maintaining the vacuum degree of 5mtorr~50mtorr maintains the 0 ℃ ~700 ℃, 100W~2000W Decoupled plasma nitriding for 10 to 300 seconds while applying RF source power.
한편, 분위기기체는 주로 질소(N)를 함유하고 있는데, 질소(N)는 산화공정ㅇ시 산화속도를 감소시키는 것으로 알려져 있으며, 종래 이온주입법에 의한 질소이온 주입과 다른 점은 디커플드플라즈마질화처리(DPN)에 의한 질소주입은 이온주입방식에 비해 기판 손상을 적게 주고, 낮은 깊이분포를 갖는 고농도 이온의 주입(inject)이 가능하다.On the other hand, the atmosphere gas mainly contains nitrogen (N), nitrogen (N) is known to reduce the oxidation rate during the oxidation process, and the difference between the nitrogen ion implantation by conventional ion implantation method is decoupled plasma nitrification Nitrogen injection by treatment (DPN) is less substrate damage than the ion implantation method, it is possible to inject a high concentration of ions having a low depth distribution.
전술한 디커플드플라즈마질화처리(DPN)후, 희생산화막(12) 하측의 반도체기판(11) 표면에는 질소가 확산하여 반도체기판내 실리콘을 질화시켜 낮은 깊이분포를 갖는 질화실리콘층(Nitrided Si)(14)이 형성된다.After the aforementioned decoupled plasma nitriding treatment (DPN), nitrogen diffuses to the surface of the semiconductor substrate 11 under the sacrificial oxide film 12 to nitrate silicon in the semiconductor substrate, thereby having a low depth distribution (Nitrided Si). (14) is formed.
도 1b에 도시된 바와 같이, 디커플드플라즈마질화처리가 이루어진 희생산화막(12)을 제거하여 반도체기판(11) 표면을 노출시킨다. 여기서, 희생산화막(12)을 제거하는 방법은, 먼저 일부분만을 디커플드플라즈마질화처리하기 위해 이용된 마스크(13)를 제거한 후, 다음으로 습식세정(wet-cleaning)을 실시하여 스트립후 잔류하는 감광막잔류물과 희생산화막(12)을 제거한다.As shown in FIG. 1B, the sacrificial oxide film 12 subjected to the decoupled plasma nitriding treatment is removed to expose the surface of the semiconductor substrate 11. Here, in the method of removing the sacrificial oxide film 12, first, the mask 13 used for decoupling plasma nitriding only a part thereof is removed, and then wet-cleaning is performed to remain after stripping. The photoresist residue and the sacrificial oxide film 12 are removed.
한편, 감광막잔류물을 제거하기 위한 습식세정은 피라나(pirana, H2SO4+H2O2), SC1(NH4OH) 용액을 이용하고, 희생산화막(12)을 제거하기 위한 습식세정은 희석된 HF 및 SC1 용액을 이용한다.Meanwhile, wet cleaning for removing the photoresist residue is performed by using pirana (pirana, H 2 SO 4 + H 2 O 2 ), SC1 (NH 4 OH) solution, and wet cleaning for removing the sacrificial oxide film 12. Silver diluted HF and SC1 solution is used.
도 1c에 도시된 바와 같이, 노출된 반도체기판(11)을 열산화시켜 디커플드 플라즈마질화처리된 부분, 즉 질화실리콘층(14)이 형성된 반도체기판(11) 표면에는 박막 게이트산화막(15a)을 형성시키고, 디커플드플라즈마질화처리가 이루어지지 않은 부분에 박막 게이트산화막(15a)보다 상대적으로 두께가 두꺼운 후막 게이트산화막(15b)을 형성시킨다.As shown in FIG. 1C, a thin film gate oxide film 15a is formed on the surface of the semiconductor substrate 11 on which the exposed semiconductor substrate 11 is thermally oxidized to be decoupled plasma nitridation, that is, the silicon nitride layer 14 is formed. The thick film gate oxide film 15b having a relatively thicker thickness than the thin film gate oxide film 15a is formed in a portion where the decoupled plasma nitriding treatment is not performed.
이와 같이 한 번의 열산화공정시 박막 게이트산화막(15a)과 후막 게이트산화막(15b)의 두께가 차이가 나는 이유는, 전술한 디커플드플라즈마질화처리(DPN)를 통해 박막 게이트산화막(15a)이 형성될 부분에는 미리 질화실리콘층(14)이 형성되어 있어 열산화시 질화실리콘층(14)이 없는 후막 게이트산화막(15b) 형성 부분에 비해 산화속도가 느리기 때문이다.The reason why the thicknesses of the thin-film gate oxide film 15a and the thick-film gate oxide film 15b are different in one thermal oxidation process is that the thin-film gate oxide film 15a is subjected to the decoupled plasma nitriding treatment (DPN) described above. This is because the silicon nitride layer 14 is formed in the portion to be formed in advance so that the oxidation rate is slower than that of the thick gate oxide film 15b without the silicon nitride layer 14 during thermal oxidation.
상술한 제1실시예에 의하면, 높은 전압이 인가되더라도 충분한 게이트산화막의 두께를 확보할 수 있으며, 열공정 및 이온주입방식에 의해 서로 다른 두께를 갖는 듀얼 게이트산화막을 형성하지 않기 때문에 반도체기판 표면의 손상을 방지한다.According to the first embodiment described above, even if a high voltage is applied, a sufficient thickness of the gate oxide film can be ensured, and since the dual gate oxide films having different thicknesses are not formed by the thermal process and the ion implantation method, Prevent damage.
도 2a내지 도 2d는 본 발명의 제2실시예에 따른 CMOS의 제조 방법을 도시한 공정 단면도이다.2A to 2D are cross-sectional views illustrating a method of manufacturing a CMOS in accordance with a second embodiment of the present invention.
도 2a에 도시된 바와 같이, 셀영역(Ⅰ)과 주변회로영역(Ⅱ)이 정의된 반도체기판(21)의 소정 부분에 소자의 활성영역과 필드영역을 한정하는 필드산화막(22)을 형성한다. 이 때, 필드산화막(22)은 반도체기판(21)을 소정 깊이로 식각하여 트렌치를 형성하고, 이 트렌치에 절연막을 채우므로써 형성된다. 한편, 필드산화막(22)을 STI(Shallow Trench Isolation) 방법으로 형성하는 것을 보였으나, LOCOS(Local Oxidation of Silicon) 방법으로도 형성할 수 있다.As shown in FIG. 2A, a field oxide film 22 defining an active region and a field region of an element is formed in a predetermined portion of the semiconductor substrate 21 in which the cell region I and the peripheral circuit region II are defined. . At this time, the field oxide film 22 is formed by etching the semiconductor substrate 21 to a predetermined depth to form a trench, and filling the trench with an insulating film. On the other hand, although the field oxide film 22 has been shown to be formed by a shallow trench isolation (STI) method, it may also be formed by a local oxide of silicon (LOCOS) method.
그리고, 셀영역(Ⅰ)은 높은 동작전압이 인가되는 영역이고, 주변회로영역(Ⅱ)은 낮은 동작전압이 인가되는 영역이다.The cell region I is a region to which a high operating voltage is applied, and the peripheral circuit region II is a region to which a low operating voltage is applied.
계속해서, 반도체기판(21)의 활성영역상에 3Å∼25Å의 두께를 갖는 희생산화막(23)을 성장시킨 후, 희생산화막(23)을 포함한 반도체기판(21)상에 감광막을 도포하고 노광 및 현상으로 패터닝하여 주변회로영역(Ⅱ)을 노출시키는 마스크(24)를 형성한다.Subsequently, a sacrificial oxide film 23 having a thickness of 3 to 25 GPa is grown on the active region of the semiconductor substrate 21, and then a photosensitive film is coated on the semiconductor substrate 21 including the sacrificial oxide film 23, and then exposed and exposed. The mask 24 is patterned by developing to expose the peripheral circuit region II.
여기서, 희생산화막(23)의 두께를 3Å∼25Å으로 한정한 것은 두께가 3Å미만일 경우는 후속 디커플드플라즈마질화처리시 반도체기판 표면이 손상되는 문제가 있고, 두께가 25Å보다 두꺼우면 후속 디커플드플라즈마질화처리시 산화속도를 감소시키는 원소인 질소를 반도체기판으로 확산시킬 수 없다.Herein, the thickness of the sacrificial oxide film 23 is limited to 3 kV to 25 kV. If the thickness is less than 3 kV, the surface of the semiconductor substrate is damaged during the subsequent decoupled plasma nitriding treatment. Nitrogen, an element that reduces the oxidation rate, cannot be diffused into a semiconductor substrate during deplasmitization.
계속해서, 마스크(24)에 의해 노출된 희생산화막(23)의 일부분을 질소(N)가 함유된 분위기기체에서 디커플드플라즈마질화처리(DPN)한다.Subsequently, a portion of the sacrificial oxide film 23 exposed by the mask 24 is decoupled plasma nitriding (DPN) in an atmosphere gas containing nitrogen (N).
이 때, 디커플드플라즈마질화처리에 적용되는 분위기기체는 N2, N2O, NO 및 NH3로 이루어진 그룹중에서 선택되는 하나를 이용한다.At this time, the atmosphere gas applied to the decoupled plasma nitriding treatment uses one selected from the group consisting of N 2 , N 2 O, NO and NH 3 .
예컨대 분위기기체로 N2를 이용하는 경우, N2를 10sccm∼1000sccm의 유량으로 주입시키고, 5mtorr∼50mtorr의 진공도를 유지한 상태에서 반도체기판(21)은 0℃∼700℃을 유지하며, 100W∼2000W의 RF 소스파워를 인가하면서 10초∼300초동안 디커플드플라즈마질화처리한다.For example, the case of using the N 2 gas to the atmosphere, and injecting the N 2 at a flow rate of 10sccm~1000sccm, the semiconductor substrate 21 while maintaining the vacuum degree of 5mtorr~50mtorr maintains the 0 ℃ ~700 ℃, 100W~2000W Decoupled plasma nitriding for 10 to 300 seconds while applying RF source power.
한편, 분위기기체는 주로 질소(N)를 함유하고 있는데, 질소(N)는 산화공정ㅇ시 산화속도를 감소시키는 것으로 알려져 있으며, 종래 이온주입법에 의한 질소이온 주입과 다른 점은 디커플드플라즈마질화처리(DPN)에 의한 질소주입은 이온주입방식에 비해 기판 손상을 적게 주고, 낮은 깊이분포를 갖는 고농도 이온의 주입(inject)이 가능하다.On the other hand, the atmosphere gas mainly contains nitrogen (N), nitrogen (N) is known to reduce the oxidation rate during the oxidation process, and the difference between the nitrogen ion implantation by conventional ion implantation method is decoupled plasma nitrification Nitrogen injection by treatment (DPN) is less substrate damage than the ion implantation method, it is possible to inject a high concentration of ions having a low depth distribution.
전술한 디커플드플라즈마질화처리(DPN)후, 희생산화막(23) 하측의 반도체기판(21) 표면에는 낮은 깊이분포를 갖는 질화실리콘층(25)이 형성된다. 이 때, 질화실리콘층(25)의 농도 분포는 도 3을 참조하기로 한다.After the decoupled plasma nitriding treatment (DPN) described above, a silicon nitride layer 25 having a low depth distribution is formed on the surface of the semiconductor substrate 21 under the sacrificial oxide film 23. In this case, the concentration distribution of the silicon nitride layer 25 will be referred to FIG. 3.
도 3은 희생산화막이 있는 상태에서 디커플드플라즈마질화처리한 후 질소의 농도(concentration) 분포를 보여주는 그래프로서, 희생산화막을 15Å 두께의 SiO2로 형성하고, 디커플드플라즈마질화처리를 100sccm N2/20mTorr/500W/35초의 조건에서 실시한 경우를 도시하고 있다.3 is a graph showing the concentration distribution of nitrogen after decoupling plasma nitriding in the presence of a sacrificial oxide film, and the sacrificial oxide film is formed of SiO 2 having a thickness of 15 Å and the decoupled plasma nitriding is performed at 100 sccm N The case where it performed on the conditions of 2 / 20mTorr / 500W / 35 second is shown.
도 3을 참조하면, 디커플드플라즈마질화처리후 질화실리콘층(25)의 농도분포는 표면으로부터 그 깊이가 깊어질수록 낮음을 알 수 있다.Referring to FIG. 3, it can be seen that the concentration distribution of the silicon nitride layer 25 after the decoupled plasma nitriding treatment is lower as the depth thereof is deeper from the surface.
도 2b에 도시된 바와 같이, 디커플드플라즈마질화처리가 이루어진 희생산화막(23)을 제거하여 반도체기판(21) 표면을 노출시킨다. 여기서, 희생산화막(23)을 제거하는 방법은, 일부분만을 디커플드플라즈마질화처리하기 위해 이용된 마스크(24)를 제거한 후, 습식세정을 실시하여 스트립후 잔류하는 감광막잔류물과 희생산화막(23)을 제거한다.As shown in FIG. 2B, the sacrificial oxide film 23 subjected to the decoupled plasma nitriding treatment is removed to expose the surface of the semiconductor substrate 21. Here, in the method of removing the sacrificial oxide film 23, after removing the mask 24 used for the decoupled plasma nitriding only a part of the sacrificial oxide film, wet cleaning is performed to remove the photoresist residue and the sacrificial oxide film 23 remaining after stripping. ).
한편, 감광막잔류물을 제거하기 위한 습식세정은 피라나(pirana, H2SO4+H2O2), SC1(NH4OH) 용액을 이용하고, 희생산화막(23)을 제거하기 위한 습식세정은 희석된 HF 및 SC1 용액을 이용한다.Meanwhile, wet cleaning for removing the photoresist residue is performed using pirana (pirana, H 2 SO 4 + H 2 O 2 ), and SC1 (NH 4 OH) solution, and wet cleaning for removing the sacrificial oxide layer 23. Silver diluted HF and SC1 solution is used.
도 2c에 도시된 바와 같이, 노출된 반도체기판(21)을 열산화시켜 디커플드 플라즈마질화처리된 부분, 즉 질화실리콘층(25)이 형성된 반도체기판(21) 표면에는 박막 게이트산화막(26a)을 형성시키고, 디커플드플라즈마질화처리가 이루어지지 않은 부분에 박막 게이트산화막(26a)보다 상대적으로 두께가 두꺼운 후막 게이트산화막(26b)을 형성시킨다.As shown in FIG. 2C, a thin film gate oxide layer 26a is formed on a surface of the semiconductor substrate 21 on which the exposed semiconductor substrate 21 is thermally oxidized to be decoupled plasma nitridation, that is, the silicon nitride layer 25 is formed. The thick film gate oxide film 26b thicker than the thin film gate oxide film 26a is formed in a portion where the decoupled plasma nitriding treatment is not performed.
이와 같이 한 번의 열산화공정시 박막 게이트산화막(26a)과 후막 게이트산화막(26b)의 두께가 차이가 나는 이유는, 전술한 디커플드플라즈마질화처리(DPN)를 통해 박막 게이트산화막(26a)이 형성될 부분에는 미리 질화실리콘층(25)이 형성되어 있어 열산화시 질화실리콘층(25)이 없는 후막 게이트산화막(26b) 형성 부분에 비해 산화속도가 느리기 때문이다.The reason why the thicknesses of the thin film gate oxide film 26a and the thick film gate oxide film 26b are different in one thermal oxidation process is that the thin film gate oxide film 26a is formed through the decoupled plasma nitriding treatment (DPN) described above. This is because the silicon nitride layer 25 is formed in advance in the portion to be formed, and thus the oxidation rate is lower than that of the thick gate oxide layer 26b without the silicon nitride layer 25 during thermal oxidation.
도 2d에 도시된 바와 같이, 후막 및 박막 게이트산화막(26a,26b)상에 게이트전극을 형성하기 위한 폴리실리콘(27)과 질화금속막(28)을 차례로 증착한다.As shown in FIG. 2D, polysilicon 27 and metal nitride film 28 for forming a gate electrode are deposited sequentially on the thick and thin film gate oxide films 26a and 26b.
여기서, 폴리실리콘(27)은 셀영역의 nMOSFET 및 주변회로영역의 nMOSFET의 게이트로 이용되는 경우에는 4.1eV∼4.2eV 정도의 일함수(work function)를 갖는 n+-폴리실리콘을 사용하며, 주변회로영역의 pMOSFET의 게이트로 이용되는 경우에는 4.9eV∼5.1eV 정도의 일함수를 갖는 p+-폴리실리콘을 사용한다.Here, the polysilicon 27 uses n + -polysilicon having a work function of about 4.1 eV to 4.2 eV when used as the gate of the nMOSFET in the cell region and the nMOSFET in the peripheral circuit region. When used as the gate of the pMOSFET in the circuit area, p + -polysilicon having a work function of about 4.9 eV to 5.1 eV is used.
그리고, 질화금속막(28)은 TaN, TaSiN, TiN, TiAlN, TiSiN, RuTaN, WN, TiBN, ZrSiN, ZrAlN, MoSiN, MoAlN, RuTiN 및 IrTiN로 이루어진 그룹중에서 선택되는 하나를 이용한다.The metal nitride film 28 uses one selected from the group consisting of TaN, TaSiN, TiN, TiAlN, TiSiN, RuTaN, WN, TiBN, ZrSiN, ZrAlN, MoSiN, MoAlN, RuTiN and IrTiN.
그리고, 폴리실리콘(27) 및 질화금속막(28)의 두께는 10Å∼2000Å이다.The thicknesses of the polysilicon 27 and the metal nitride film 28 are 10 kPa to 2000 kPa.
한편, 게이트전극은 전술한 폴리실리콘/질화금속막의 적층구조외에 폴리실리콘 단독구조, 질화금속막의 단독구조, 폴리실리콘/질화금속/실리사이드의 적층구조, 폴리실리콘/질화금속/텅스텐의 적층구조도 가능하다.On the other hand, in addition to the above-described lamination structure of the polysilicon / metal nitride film, the gate electrode may be made of a polysilicon alone structure, a metal nitride film alone structure, a polysilicon / metal nitride / silicide lamination structure, and a polysilicon / metal nitride / tungsten lamination structure. Do.
이 때, 실리사이드 또는 텅스텐은 게이트전극의 저항을 낮추기 위해 적용된 물질로, 50Å∼2000Å 두께로 증착된다. 실리사이드로는 텅스텐실리사이드(W-silicide), 코발트실리사이드(Co-silicide), 티타늄실리사이드(Ti-silicide), 몰리브덴실리사이드(Mo-silicide), 탄탈륨실리사이드(Ta-silicide), 니오비윰실리사이드(Nb-silicide)를 이용한다.In this case, silicide or tungsten is a material applied to lower the resistance of the gate electrode, and is deposited to have a thickness of 50 kPa to 2000 kPa. The silicides include tungsten silicide (W-silicide), cobalt silicide (Co-silicide), titanium silicide (Ti-silicide), molybdenum silicide (Mo-silicide), tantalum silicide (Ta-silicide) and niobium silicide (Nb- silicide).
다음으로, 감광막에 의한 게이트마스크(도시 생략)로 질화금속막(28)과 폴리실리콘(27)을 식각하여 셀영역(Ⅰ) 및 주변회로영역(Ⅱ)에 각각 트랜지스터의 게이트전극을 형성한다.Next, the metal nitride film 28 and the polysilicon 27 are etched with a gate mask (not shown) by a photoresist film to form gate electrodes of transistors in the cell region I and the peripheral circuit region II, respectively.
계속해서, 게이트마스크를 제거한 후 트랜지스터의 소스/드레인을 형성하기 위한 불순물 이온주입 및 스페이서(30) 공정을 거쳐 LDD(29) 구조의 소스/드레인(31)을 형성한다. 후속 공정으로 각각의 트랜지스터들을 절연시켜주기 위한 층간절연막을 형성하고, 소스/드레인(31) 및 게이트전극을 외부단자와 연결시켜주기 위한 금속화(Metallization) 공정을 실시한다.Subsequently, after the gate mask is removed, the source / drain 31 having the LDD 29 structure is formed through the impurity ion implantation and spacer 30 processes for forming the source / drain of the transistor. In a subsequent process, an interlayer insulating film is formed to insulate each transistor, and a metallization process is performed to connect the source / drain 31 and the gate electrode with external terminals.
상술한 제2실시예에 의하면, 주변회로영역(Ⅱ)에만 디커플드플라즈마질화처리하여 반도체기판(21) 표면에 질화실리콘층(25)을 형성한 후 후속 열산화공정을 실시하면 셀영역(Ⅰ)과 주변회로영역(Ⅱ)에 서로 다른 두께를 갖는 듀얼 게이트산화막을 형성한다.According to the second embodiment described above, after the silicon nitride layer 25 is formed on the surface of the semiconductor substrate 21 by the decoupled plasma nitriding only in the peripheral circuit region II, a subsequent thermal oxidation process is performed. Dual gate oxide films having different thicknesses are formed in I) and the peripheral circuit region II.
이러한 결과, 주변회로영역(Ⅱ)에서의 산화속도를 감소시켜 셀영역(Ⅰ)의 게이트산화막의 두께를 주변회로영역(Ⅱ)의 게이트산화막보다 작게는 2Å 크게는 10Å 이상 두껍게 형성할 수 있다. 따라서, 셀영역(Ⅰ)의 트랜지스터에 높은 전압을 인가해도 충분한 게이트산화막의 두께를 확보할 수 있다.As a result, by reducing the oxidation rate in the peripheral circuit region II, the thickness of the gate oxide film in the cell region I can be formed to be 2 kV or more and 10 kPa or more thicker than the gate oxide film of the peripheral circuit region II. Therefore, even if a high voltage is applied to the transistor of the cell region I, a sufficient gate oxide film thickness can be ensured.
본 발명의 또 다른 실시예로서, 적층구조의 듀얼게이트 절연막을 적용하는 CMOS 뿐만 아니라 듀얼 다마신(Dual damascene) 구조의 CMOS에도 적용가능하며, 다양한 게이트산화막(질화 게이트산화막 및 고유전 금속산화막 등)에 적용할 수 있다.As another embodiment of the present invention, the present invention can be applied not only to a CMOS using a dual gate insulating film having a stacked structure but also to a CMOS having a dual damascene structure, and to various gate oxide films (such as a nitride gate oxide film and a high dielectric metal oxide film). Applicable to
또한 듀얼 게이트산화막뿐만 아니라, 트리플(triple) 게이트산화막을 구비하는 반도체장치에도 적용가능하다.In addition to the dual gate oxide film, the present invention can be applied to a semiconductor device having a triple gate oxide film.
그리고, 본 발명은 실리콘산화막(SiO2), 실리콘산화질화막(SiON), 고유전 금속산화막(Al2O3, Ta2O5, HfO2, ZrO2), 고유전 금속산화막의 실리케이트(Hf-silicate, Zr-silicate) 및 고유전 금속산화막의 혼합막, 고유전 금속산화막의 나노래미네이트(Nano-laminate) 구조를 갖는 고유전막중에서 선택되는 적어도 하나 또는 이들의 적층막으로 이루어진 게이트산화막을 구비하는 반도체장치에 적용 가능하다.In addition, the present invention provides a silicate (Hf-) of a silicon oxide film (SiO 2 ), a silicon oxynitride film (SiON), a high dielectric metal oxide film (Al 2 O 3 , Ta 2 O 5 , HfO 2 , ZrO 2 ), and a high dielectric metal oxide film. A gate oxide film comprising at least one selected from a mixture of silicate, Zr-silicate and high dielectric metal oxide films, and a high dielectric film having a nano-laminate structure of a high dielectric metal oxide film. Applicable to semiconductor devices.
또한, 본 발명은 임베디드형(embedded type)의 메모리소자(DRAM, SRAM, FLASH)와 로직소자를 결합한 시스템온칩(System On Chip;SOC)과 같은 소자에서 로직소자영역과 메모리소자의 주변회로영역에서는 얇은 게이트산화막을 형성하고, 메모리소자의 셀영역에서는 두꺼운 게이트산화막을 형성하는 방법에도 적용 가능하다.In addition, the present invention is in the logic device area and the peripheral circuit area of the memory device in a device such as a system on chip (SOC) combined with embedded memory devices (DRAM, SRAM, FLASH) and logic devices It is also applicable to the method of forming a thin gate oxide film and forming a thick gate oxide film in the cell region of the memory device.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같은 본 발명은 디커플드플라즈마질화처리에 의해 산화속도를 감소시키는 질소을 주입하고 한번의 열산화공정을 통해 듀얼 게이트산화막을 형성하므로 추가 열공정이 필요없고, 이온주입방식이 발생시키는 반도체기판의 손상을 발생시키지 않으므로 GOI 특성을 개선할 수 있는 효과가 있다.As described above, the present invention provides a semiconductor substrate which does not need an additional thermal process because the dual gate oxide film is formed through a single thermal oxidation process by injecting nitrogen which reduces the oxidation rate by the decoupled plasma nitriding treatment. There is an effect that can improve the GOI properties because it does not cause damage.
또한 디커플드플라즈마질화처리에 의해 질소주입층이 반도체기판 표면에만 국한되므로 게이트산화막 하부 채널이동도 특성을 확보할 수 있는 효과가 있다.In addition, since the nitrogen injection layer is limited only to the surface of the semiconductor substrate by the decoupled plasma nitriding treatment, it is possible to obtain the gate oxide channel channel mobility characteristics.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100609236B1 (en) * | 2003-12-31 | 2006-08-02 | 동부일렉트로닉스 주식회사 | Method of forming dual gate |
| KR100611784B1 (en) * | 2004-12-29 | 2006-08-10 | 주식회사 하이닉스반도체 | Semiconductor device with multi-gate dielectric and method for manufacturing the same |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100609236B1 (en) * | 2003-12-31 | 2006-08-02 | 동부일렉트로닉스 주식회사 | Method of forming dual gate |
| KR100611784B1 (en) * | 2004-12-29 | 2006-08-10 | 주식회사 하이닉스반도체 | Semiconductor device with multi-gate dielectric and method for manufacturing the same |
| US7563726B2 (en) | 2004-12-29 | 2009-07-21 | Hynix Semiconductor Inc. | Semiconductor device with multiple gate dielectric layers and method for fabricating the same |
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