KR20030047405A - Multi chip package and manufacturing method thereof - Google Patents

Multi chip package and manufacturing method thereof Download PDF

Info

Publication number
KR20030047405A
KR20030047405A KR1020010077885A KR20010077885A KR20030047405A KR 20030047405 A KR20030047405 A KR 20030047405A KR 1020010077885 A KR1020010077885 A KR 1020010077885A KR 20010077885 A KR20010077885 A KR 20010077885A KR 20030047405 A KR20030047405 A KR 20030047405A
Authority
KR
South Korea
Prior art keywords
semiconductor chip
die pad
lead
slot
bonding
Prior art date
Application number
KR1020010077885A
Other languages
Korean (ko)
Inventor
이장우
목승곤
Original Assignee
삼성전자주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자주식회사 filed Critical 삼성전자주식회사
Priority to KR1020010077885A priority Critical patent/KR20030047405A/en
Publication of KR20030047405A publication Critical patent/KR20030047405A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/074—Stacked arrangements of non-apertured devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE: A multi-chip package and a method for manufacturing the same are provided to be capable of preventing the damage of a semiconductor chip, the contact between wires and the limitation in chip selection by bonding the rear surfaces of semiconductor chips together. CONSTITUTION: A multi-chip package(300) is provided with a die pad(310) having a slot(315), the first and second semiconductor chips(301a,301b), and a lead(340) made of an inner and outer lead(340a,340b). The first and second semiconductor chips further include active surfaces having bonding pads(303a,303b) and rear surfaces. The rear surfaces of the first and second semiconductor chips are bonded with each other through an adhesive(350). At this time, the first semiconductor chip is located in the slot(315) of the die pad(310), wherein the die pad is attached to the rear surface of the second semiconductor chip. Preferably, the size of the slot is larger than that of the first semiconductor chip.

Description

멀티 칩 패키지와 그 제조 방법{Multi chip package and manufacturing method thereof}Multi chip package and manufacturing method

본 발명은 반도체 칩 패키지에 관한 것으로, 좀 더 상세하게는 멀티 칩 패키지와 그 제조 방법에 관한 것이다.The present invention relates to a semiconductor chip package, and more particularly to a multi-chip package and a method of manufacturing the same.

최근, 반도체 칩의 집적도가 증가함에 따라, 반도체 칩 패키지는 크기가 소형화되면서 용량은 증가되고 그 기능이 다양화되었다. 이와 같은 추세에 부합되기위한 반도체 칩 패키지에는 멀티 칩 패키지가 있다. 멀티 칩 패키지는 복수개의 반도체 칩을 하나의 패키지로 구성하는 기술로서, 이 기술이 적용된 멀티 칩 패키지를 이용하는 것이 하나의 반도체 칩을 포함하는 반도체 패키지 여러 개를 이용하는 것보다 소형화와 경량화 및 실장면적에서 유리하다.In recent years, as the degree of integration of semiconductor chips increases, the size of semiconductor chip packages has become smaller and the capacity has increased and the functions thereof have been diversified. There is a multi-chip package in the semiconductor chip package to meet this trend. Multi-chip package is a technology that configures a plurality of semiconductor chips into one package, and using the multi-chip package to which the technology is applied is smaller, lighter and more compact than using multiple semiconductor packages including a single semiconductor chip. It is advantageous.

종래 기술에 따른 멀티 칩 패키지를 도면을 참조하여 설명하면 다음과 같다.Referring to the drawings, a multi-chip package according to the prior art is as follows.

도 1a는 종래 기술에 따른 멀티 칩 패키지의 단면도이다.1A is a cross-sectional view of a multichip package according to the prior art.

종래 기술에 따른 멀티 칩 패키지(100)는, 다이 패드(110)와, 내부 리드(140a)와 외부 리드(140b)로 구성된 리드(140)와, 제 1반도체 칩(101a)과 제 2반도체 칩(101b)을 포함한다. 제 1반도체 칩(101a)은 본딩 패드(103a)가 형성된 활성면과 그와 반대되는 배면을 포함하며, 배면이 다이 패드(110) 상에 접착 수단(150)에 의해 부착된다. 제 2반도체 칩(101b)은 본딩 패드(103b)가 형성된 활성면과 그와 반대되는 배면을 포함하며, 그 배면은 제 1반도체 칩(101a)의 활성면에 접착 수단(150)에 의해 부착된다.The multichip package 100 according to the related art includes a die pad 110, a lead 140 formed of an internal lead 140a and an external lead 140b, a first semiconductor chip 101a, and a second semiconductor chip. 101b. The first semiconductor chip 101a includes an active surface on which the bonding pads 103a are formed and a rear surface opposite thereto, and the back surface is attached by the adhesive means 150 on the die pad 110. The second semiconductor chip 101b includes an active surface on which the bonding pads 103b are formed and a rear surface opposite thereto, and the rear surface is attached to the active surface of the first semiconductor chip 101a by an adhesive means 150. .

이와 같은 제 1, 2반도체 칩(101a, 101b)의 본딩 패드(103a, 103b)는 내부 리드(140a)와 복수개의 와이어(120)에 의해 전기적으로 연결된다. 제 1, 2반도체 칩(101a, 101b)과 복수개의 와이어(120), 다이 패드(110) 및 내부 리드(140a)는 에폭시 몰딩 수지(epoxy molding compound; EMC)와 같은 성형 수지에 의해 봉지되어 패키지 몸체(130)가 형성된다.The bonding pads 103a and 103b of the first and second semiconductor chips 101a and 101b are electrically connected to each other by an internal lead 140a and a plurality of wires 120. The first and second semiconductor chips 101a and 101b, the plurality of wires 120, the die pad 110 and the inner lead 140a are encapsulated by a molding resin such as an epoxy molding compound (EMC) and packaged. Body 130 is formed.

그러나 종래 기술의 멀티 칩 패키지(100)는 제 1반도체 칩(101a)의 활성면에 제 2반도체 칩(101b)이 부착되므로 제 1반도체 칩(101a)의 손상 가능성이 증대되며, 제 1반도체 칩(101b)의 본딩 패드(103a)와 내부 리드(140a) 및 제 2반도체 칩(101b)의 본딩 패드(103b)와 내부 리드(140a)간을 전기적으로 연결하는 와이어(120)간의 접촉으로 인한 불량이 발생될 수 있다. 더불어 제 1반도체 칩(101a)은 에지 본딩 패드형(edgy bonding pad type)으로만 구비되어야 하는 한계가 있다.However, since the second semiconductor chip 101b is attached to the active surface of the first semiconductor chip 101a in the conventional multi-chip package 100, the possibility of damage of the first semiconductor chip 101a is increased, and the first semiconductor chip is Defect due to contact between the bonding pad 103a of the 101b and the inner lead 140a and the wire 120 electrically connecting the bonding pad 103b of the second semiconductor chip 101b and the inner lead 140a. This may occur. In addition, there is a limit that the first semiconductor chip 101a should be provided only in an edge bonding pad type.

이와 같은 문제점을 극복하기 위한 종래 기술의 또 다른 멀티 칩 패키지를 설명하면 다음과 같다.Another multi-chip package according to the related art for overcoming such a problem is as follows.

도 1b는 종래 기술에 따른 또 다른 멀티 칩 패키지의 단면도이다.1B is a cross-sectional view of another multichip package according to the prior art.

도 1b에 따른 멀티 칩 패키지(200)는, 다이 패드(210)와, 본딩 패드(203a, 203b)가 형성된 활성면과 활성면의 반대면인 배면이 구비된 제 1반도체 칩(201a)과 제 2반도체 칩(201b), 다이 패드(210)를 중심으로 배열된 내부 리드(240a) 및 외부 리드(240b)로 구성된 리드(240)를 포함한다.The multi-chip package 200 according to FIG. 1B includes a first semiconductor chip 201a having a die pad 210, an active surface on which bonding pads 203a and 203b are formed, and a back surface opposite to the active surface. The lead 240 includes a second semiconductor chip 201b, an inner lead 240a and an outer lead 240b arranged around the die pad 210.

제 1, 2반도체 칩(201a, 201b)은 다이 패드(210)의 상하면에 배면이 접착 수단(250)에 의해 접착되고, 제 1, 2반도체 칩(201a, 201b)의 본딩 패드(203a, 203b)는 복수개의 와이어(220)에 의해 내부 리드(220)와 전기적으로 연결된다. 이와 같은 제 1, 2반도체 칩(201a, 201b), 다이 패드(210), 복수개의 와이어(220) 및 내부 리드(220)는 에폭시 몰딩 수지와 같은 플라스틱 성형 수지에 의해 봉지되어 패키지 몸체(230)를 형성한다.The first and second semiconductor chips 201a and 201b are bonded to the top and bottom surfaces of the die pad 210 by the bonding means 250, and the bonding pads 203a and 203b of the first and second semiconductor chips 201a and 201b. ) Is electrically connected to the inner lead 220 by a plurality of wires 220. The first and second semiconductor chips 201a and 201b, the die pad 210, the plurality of wires 220, and the inner lead 220 are encapsulated by a plastic molding resin such as an epoxy molding resin, and thus the package body 230. To form.

이와 같은 종래 기술에 따른 또 다른 멀티 칩 패키지는, 상술한 문제점, 예컨대 반도체 칩의 손상, 와이어간의 접촉, 반도체 칩 선택의 제한 발생과 같은 문제가 감소될 수 있다. 그러나 멀티 칩 패키지의 전체 두께가 증가되어 박형화가 어려워지는 문제가 발생된다.Another multi-chip package according to the related art can reduce the above-described problems, such as damage of semiconductor chips, contact between wires, and limitations in semiconductor chip selection. However, as the overall thickness of the multi-chip package is increased, it becomes difficult to thin.

본 발명의 목적은 반도체 칩의 손상, 와이어간의 접촉 및 반도체 칩의 선택 제한과 같은 문제가 발생되지 않는 멀티 칩 패키지와 그 제조 방법을 제공하는데 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a multi-chip package and a method of manufacturing the same, in which problems such as damage of semiconductor chips, contact between wires, and limitation of selection of semiconductor chips do not occur.

본 발명의 또 다른 목적은 박형화가 가능한 멀티 칩 패키지와 그 제조 방법을 제공하는데 있다.It is still another object of the present invention to provide a multi-chip package capable of thinning and a method of manufacturing the same.

도 1a는 종래 기술에 따른 멀티 칩 패키지의 단면도,1A is a cross-sectional view of a multi-chip package according to the prior art,

도 1b는 종래 기술에 따른 또 다른 멀티 칩 패키지의 단면도,1B is a cross-sectional view of another multi-chip package according to the prior art,

도 2a는 본 발명의 일 실시예에 따른 멀티 칩 패키지의 단면도,2A is a cross-sectional view of a multichip package according to an embodiment of the present invention;

도 2b는 본 발명의 일 실시예에 따른 멀티 칩 패키지의 부분 사시도,2B is a partial perspective view of a multichip package according to an embodiment of the present invention;

도 3a는 본 발명의 또 다른 실시예에 따른 멀티 칩 패키지의 단면도,3A is a cross-sectional view of a multichip package according to another embodiment of the present invention;

도 3b는 본 발명의 또 다른 실시예에 따른 멀티 칩 패키지의 부분 사시도,3B is a partial perspective view of a multichip package according to another embodiment of the present invention;

도 4a 내지 도 4c는 본 발명의 일 실시예에 따른 멀티 칩 패키지의 제조 공정 단면도,4A to 4C are cross-sectional views of a manufacturing process of a multi-chip package according to an embodiment of the present invention;

도 5a 내지 도 5c는 본 발명의 또 다른 실시예에 따른 멀티 칩 패키지의 제조 공정 단면도이다.5A to 5C are cross-sectional views illustrating a manufacturing process of a multichip package according to another exemplary embodiment of the present invention.

* 도면의 주요 부분에 대한 설명 *Description of the main parts of the drawing

100, 200, 300, 400 : 멀티 칩 패키지100, 200, 300, 400: Multichip Package

101a, 201a, 301a, 401a : 제 1반도체 칩101a, 201a, 301a, 401a: first semiconductor chip

101b, 201b, 301b, 401b : 제 2반도체 칩101b, 201b, 301b, 401b: second semiconductor chip

103a, 103b, 203a, 203b, 303a, 303b, 403a, 403b : 본딩 패드Bonding pads 103a, 103b, 203a, 203b, 303a, 303b, 403a, 403b

110, 210, 310, 410 : 다이 패드110, 210, 310, 410: die pad

120, 220, 320, 420 : 와이어120, 220, 320, 420: wire

130, 230, 330, 430 : 패키지 몸체130, 230, 330, 430: package body

140a, 240a, 340a, 440a : 내부 리드Internal lead: 140a, 240a, 340a, 440a

140b, 240b, 340b, 440b : 외부 리드140b, 240b, 340b, 440b: external lead

140, 240, 340, 440 : 리드140, 240, 340, 440: leads

150, 250, 350, 450 : 접착 수단150, 250, 350, 450: bonding means

315, 415 : 슬롯315, 415: slot

420a, 420b, 420c : 제 1, 2, 3와이어420a, 420b, 420c: 1st, 2nd, 3rd wire

460 : 테이프 배선 기판460: Tape Wiring Board

461 : 회로 패턴461: circuit pattern

463 : 절연층463: insulation layer

465 : 관통홀465: through hole

상기 목적을 달성하기 위하여, 본 발명에 따른 멀티 칩 패키지는, 소정의 크기를 갖는 슬롯이 형성된 다이 패드; 다이 패드의 상부면에 부착되는 배면과, 배면과 반대되며 본딩 패드가 형성된 활성면이 구비된 제 1반도체 칩; 슬롯 내부에 위치하고, 제 1반도체 칩의 배면과 부착되는 배면 및 배면과 반대되고 본딩 패드가 구비된 제 2반도체 칩; 다이 패드를 중심으로 나열된 내부 리드와 외부 리드를 포함하는 리드; 제 1, 2반도체 칩의 본딩 패드와 내부 리드를 전기적으로 연결하는 복수개의 와이어; 및 제 1, 2반도체 칩, 다이 패드, 내부 리드 및 와이어를 봉지하여 형성된 패키지 몸체;를 포함하는 것을 특징으로 한다.In order to achieve the above object, the multi-chip package according to the present invention, a die pad having a slot having a predetermined size; A first semiconductor chip having a back surface attached to an upper surface of the die pad and an active surface opposite to the back surface and having a bonding pad formed thereon; A second semiconductor chip disposed in the slot and opposite to the rear surface and the rear surface of the first semiconductor chip and provided with a bonding pad; A lead including an inner lead and an outer lead centered around the die pad; A plurality of wires electrically connecting the bonding pads of the first and second semiconductor chips and the internal leads; And a package body formed by encapsulating the first and second semiconductor chips, the die pad, the inner lead, and the wire.

본 발명에 따른 또 다른 멀티 칩 패키지는, 소정의 크기를 갖는 슬롯이 형성된 다이 패드; 적어도 슬롯의 크기로 구비되는 관통홀이 형성되고, 다이 패드의 하부면에 부착되는 회로 형성체; 다이 패드의 하부면과 반대되는 상부면에 부착되는배면과, 배면과 반대되며 본딩 패드가 형성된 활성면이 구비된 제 1반도체 칩; 슬롯 및 관통홀의 내부에 위치하고, 제 1반도체 칩의 배면과 부착되는 배면 및 배면과 반대되고 본딩 패드가 구비된 제 2반도체 칩; 다이 패드를 중심으로 나열된 내부 리드와 외부 리드를 포함하는 리드; 제 1반도체 칩의 본딩 패드와 회로 형성체를 전기적으로 연결하는 복수개의 제 1와이어, 회로 형성체와 내부 리드를 연결하는 복수개의 제 2와이어, 및 제 2반도체 칩의 본딩 패드와 내부 리드를 연결하는 제 3와이어를 포함하는 복수개의 와이어; 및 제 1, 2반도체 칩, 다이 패드, 내부 리드, 회로 형성체 및 제 1, 2, 3와이어를 봉지하여 형성된 패키지 몸체;를 포함하는 것을 특징으로 한다.Another multi-chip package according to the present invention, the die pad is formed slot having a predetermined size; A circuit body formed with at least a slot having a size and attached to a lower surface of the die pad; A first semiconductor chip having a back surface attached to an upper surface opposite to a lower surface of the die pad and an active surface opposite to the rear surface and having a bonding pad formed thereon; A second semiconductor chip disposed inside the slot and the through hole and opposite to the rear surface and the rear surface of the first semiconductor chip and provided with a bonding pad; A lead including an inner lead and an outer lead centered around the die pad; A plurality of first wires electrically connecting the bonding pads of the first semiconductor chip and the circuit forming body, a plurality of second wires connecting the circuit forming body and the internal leads, and connecting the bonding pads of the second semiconductor chip and the internal leads A plurality of wires comprising a third wire; And a package body formed by encapsulating the first and second semiconductor chips, the die pad, the inner lead, the circuit forming member, and the first, second and third wires.

여기서, 회로 형성체는 다이 패드의 하부면에 부착되는 절연층과, 절연층 상에 형성된 회로 패턴, 및 적어도 슬롯의 크기로 구비되는 관통홀이 형성된 테이프 회로 기판인 것이 바람직하다. 또한 회로 형성체는 다이 패드의 하부면에 절연 재질의 접착 수단에 의해 부착된 금속 회로 패턴인 것이 바람직하다.Here, the circuit former is preferably a tape circuit board having an insulating layer attached to the lower surface of the die pad, a circuit pattern formed on the insulating layer, and a through hole provided at least in the size of a slot. In addition, the circuit former is preferably a metal circuit pattern attached to the lower surface of the die pad by means of bonding means of insulating material.

본 발명에 따른 멀티 칩 패키지의 제조 방법은, (a) 본딩 패드가 형성된 활성면과 활성면과 반대되는 배면이 구비된 제 1, 2반도체 칩과 내부 리드와 외부 리드로 구성된 리드 및 슬롯이 형성된 다이 패드를 준비하는 단계; (b) 제 1반도체 칩의 배면과 제 2반도체 칩의 배면을 접착하는 단계; (c) 제 1반도체 칩을 슬롯 내부에 위치시키고, 제 2 반도체 칩의 배면을 다이 패드에 부착하는 단계; (d) 제 1, 2반도체 칩의 본딩 패드와 내부 리드를 와이어 본딩하는 단계; (e) 제 1, 2반도체 칩, 내부 리드, 와이어 및 다이 패드를 봉지하여 패키지 몸체를 형성하는 단계;를포함하는 것이 바람직하다.Method for manufacturing a multi-chip package according to the present invention, (a) the first and second semiconductor chip having an active surface with a bonding pad and the back surface opposite to the active surface and the lead and the slot consisting of an inner lead and an outer lead is formed Preparing a die pad; (b) bonding the back side of the first semiconductor chip to the back side of the second semiconductor chip; (c) placing the first semiconductor chip inside the slot and attaching the back surface of the second semiconductor chip to the die pad; (d) wire bonding the bonding pads and the inner leads of the first and second semiconductor chips; (e) encapsulating the first and second semiconductor chips, the inner leads, the wires, and the die pads to form a package body.

본 발명에 따른 또 다른 멀티 칩 패키지의 제조 방법은, 본딩 패드가 형성된 활성면과 활성면과 반대되는 배면이 구비된 제 1, 2반도체 칩과, 내부 리드와 외부 리드로 구성된 리드와, 슬롯이 형성되고 다이 패드, 및 다이 패드 상에 부착되며 슬롯과 대응되는 크기로 구비된 관통홀이 형성된 회로 형성체를 준비하는 단계; (b) 제 1반도체 칩의 배면과 제 2반도체 칩의 배면을 접착하는 단계; (c) 제 1반도체 칩을 슬롯 및 관통홀 내부에 위치시키고, 제 2 반도체 칩의 배면을 다이 패드에 부착하는 단계; (d) 제 1반도체 칩의 본딩 패드와 회로 형성체, 회로 형성체와 내부 리드, 및 제 2반도체 칩과 내부 리드를 와이어 본딩하는 단계; (e) 제 1, 2반도체 칩, 내부 리드, 와이어 및 다이 패드를 봉지하여 패키지 몸체를 형성하는 단계;를 포함하는 것을 특징으로 한다.According to another aspect of the present invention, there is provided a method of manufacturing a multi-chip package, wherein the first and second semiconductor chips having an active surface on which a bonding pad is formed and a back surface opposite to the active surface, a lead composed of an inner lead and an outer lead, Preparing a circuit formed body formed with a die pad and a through hole formed on the die pad and having a size corresponding to that of the slot; (b) bonding the back side of the first semiconductor chip to the back side of the second semiconductor chip; (c) placing the first semiconductor chip inside the slot and the through hole, and attaching the back surface of the second semiconductor chip to the die pad; (d) wire bonding the bonding pads and the circuit former of the first semiconductor chip, the circuit former and the internal lead, and the second semiconductor chip and the internal lead; (e) encapsulating the first and second semiconductor chips, the inner leads, the wires, and the die pads to form a package body.

이하, 첨부 도면을 참조하여 본 발명의 실시예를 보다 상세하게 설명하고자 한다.Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

도 2a는 본 발명의 일 실시예에 따른 멀티 칩 패키지의 단면도, 도 2b는 본 발명의 일 실시예에 따른 멀티 칩 패키지의 부분 사시도이다.2A is a cross-sectional view of a multichip package according to an embodiment of the present invention, and FIG. 2B is a partial perspective view of the multichip package according to an embodiment of the present invention.

도 2a 및 도 2b에 따른 멀티 칩 패키지(300)는, 소정의 크기의 슬롯(315)이 형성된 다이 패드(310)와, 제 1, 2반도체 칩(301a, 301b) 및 내부 리드(340a)와 외부 리드(340b)로 구성되는 리드(340)를 포함한다.The multi-chip package 300 according to FIGS. 2A and 2B may include a die pad 310 having a predetermined size slot 315, first and second semiconductor chips 301a and 301b, and an internal lead 340a. It includes a lead 340 composed of an external lead 340b.

제 1반도체 칩(301a)과 제 2반도체 칩(301b)은 본딩 패드(303a, 303b)가 형성된 활성면과, 활성면과 반대되는 배면을 갖는다. 제 1, 2반도체 칩(301a, 301b)은 그 배면이 서로 접착되고, 센터 본딩 패드형(center bonding pad type) 또는 에지 본딩 패드형 중 어느 하나의 형태로 구비될 수 있다. 제 1반도체 칩(301a)은 다이 패드(310)의 슬롯(315) 내부에 위치되고, 제 2반도체 칩(301b)의 배면은 다이 패드(310)에 접착 수단(350)이 개재되어 부착된다. 슬롯(315)은 최소한 제 1반도체 칩(301a)의 크기보다 크며, 제 1반도체 칩(301a)은 제 2반도체 칩(301b)보다 작은 크기를 갖도록 구비되는 것이 바람직하다.The first semiconductor chip 301a and the second semiconductor chip 301b have an active surface on which the bonding pads 303a and 303b are formed, and a back surface opposite to the active surface. The back surfaces of the first and second semiconductor chips 301a and 301b are bonded to each other and may be provided in one of a center bonding pad type and an edge bonding pad type. The first semiconductor chip 301a is positioned inside the slot 315 of the die pad 310, and a rear surface of the second semiconductor chip 301b is attached to the die pad 310 with an adhesive means 350 interposed therebetween. The slot 315 is at least larger than the size of the first semiconductor chip 301a, and the first semiconductor chip 301a is preferably provided to have a smaller size than the second semiconductor chip 301b.

다이 패드(310) 주변에는 이를 중심으로 내부 리드(340a)와 외부 리드(340b)를 포함하는 리드(340)가 배열되고, 다이 패드(310) 및 제 1, 2반도체 칩(301a, 301b)의 본딩 패드(303a, 303b)는 복수개의 와이어(320)에 의해 전기적으로 연결된다. 제 1, 2반도체 칩(301a, 301b), 다이 패드(310), 내부 리드(340a, 340b) 및 와이어(320)는 에폭시 몰딩 수지와 같은 성형 수지에 의해 봉지되어 패키지 몸체(330)가 형성된다.A lead 340 including an inner lead 340a and an outer lead 340b is arranged around the die pad 310, and the die pad 310 and the first and second semiconductor chips 301a and 301b are arranged around the die pad 310. The bonding pads 303a and 303b are electrically connected by the plurality of wires 320. The first and second semiconductor chips 301a and 301b, the die pad 310, the inner leads 340a and 340b and the wire 320 are encapsulated by a molding resin such as an epoxy molding resin to form a package body 330. .

이와 같은 멀티 칩 패키지의 제조 방법을 도면을 참조하여 설명하면 다음과 같다.The manufacturing method of such a multi-chip package will be described with reference to the drawings.

도 4a 내지 도 4c는 본 발명의 일 실시예에 따른 멀티 칩 패키지의 제조 공정 단면도이다.4A through 4C are cross-sectional views illustrating a manufacturing process of a multi-chip package according to an embodiment of the present invention.

(a) 먼저, 도 2b와 같이 본딩 패드(303b)가 형성된 활성면과 활성면과 반대되는 배면이 구비된 제 1, 2반도체 칩(301a, 301b)과 내부 리드(도시하지 않음)와 외부 리드(도시하지 않음)로 구성된 리드(도시하지 않음) 및 슬롯(315)이 형성된 다이 패드(310)를 준비하는 단계를 거친다. 상술한 바와 같이 슬롯(315)은 제 1반도체 칩(301a)의 크기 이상으로 구비되고, 리드 프레임 제조 공정 중 펀칭 공정에 의해 다이 패드(310)가 관통됨으로써 마련된다.(a) First, as shown in FIG. 2B, the first and second semiconductor chips 301a and 301b having the active surface on which the bonding pads 303b are formed and the back surface opposite to the active surface, the inner lead (not shown), and the outer lead are provided. A step (not shown) consisting of a lead (not shown) and a slot 315 are formed to prepare a die pad 310. As described above, the slot 315 is provided to be larger than or equal to the size of the first semiconductor chip 301a and is provided by the die pad 310 being penetrated by the punching process during the lead frame manufacturing process.

(b) 도 4a와 같이, 제 1반도체 칩(301a)의 배면과 제 2반도체 칩(301b)의 배면을 접착하는 단계를 거친다. 제 1반도체 칩(301a)과 제 2반도체 칩(301b)은 탄성중합체(elastomer) 또는 은 에폭시(Ag epoxy)와 같은 접착 수단(350)에 의해 접착된다.4B, the back surface of the first semiconductor chip 301a and the back surface of the second semiconductor chip 301b are bonded to each other. The first semiconductor chip 301a and the second semiconductor chip 301b are bonded by an adhesive means 350 such as an elastomer or silver epoxy.

(c) 도 4b와 같이, 제 1반도체 칩(301a)을 슬롯(315) 내부에 위치시키고, 제 2반도체 칩(301b)의 배면을 다이 패드(310)에 부착하는 단계를 거친다. 제 2반도체 칩(301b)과 다이 패드(310) 사이에는 접착 수단이 개재되고 탄성 중합체 또는 은 에폭시와 같은 재질로 마련될 수 있다.(C) As shown in FIG. 4B, the first semiconductor chip 301a is positioned inside the slot 315, and the back surface of the second semiconductor chip 301b is attached to the die pad 310. An adhesive means may be interposed between the second semiconductor chip 301b and the die pad 310, and may be formed of a material such as an elastomer or silver epoxy.

(d) 도 4c와 같이, 제 1, 2반도체 칩(301a, 301b)의 본딩 패드(303a, 303b)와 내부 리드(340a)를 와이어(320) 본딩하는 단계를 거친다.4D, the bonding pads 303a and 303b of the first and second semiconductor chips 301a and 301b and the internal lead 340a are bonded to the wire 320.

(e) 제 1, 2반도체 칩(301a, 301b), 내부 리드(340a), 와이어(320) 및 다이 패드(310)를 봉지하여 패키지 몸체(도 2a의 330)를 형성하는 단계를 거침으로써 본 발명에 따른 멀티 칩 패키지(도 2a의 300)의 제조 공정은 완료된다.(e) encapsulating the first and second semiconductor chips 301a and 301b, the inner lead 340a, the wire 320 and the die pad 310 to form a package body (330 in FIG. 2A). The manufacturing process of the multichip package 300 according to the invention (300 in FIG. 2A) is completed.

본 발명에 따른 멀티 칩 패키지는 또 다른 형태로 구비될 수 있으며, 이를 도면과 함께 설명하면 다음과 같다.The multi-chip package according to the present invention may be provided in another form, which will be described with reference to the accompanying drawings.

도 3a는 본 발명의 또 다른 실시예에 따른 멀티 칩 패키지의 단면도, 도 3b는 본 발명의 또 다른 실시예에 따른 멀티 칩 패키지의 부분 사시도이다.3A is a cross-sectional view of a multi-chip package according to another embodiment of the present invention, and FIG. 3B is a partial perspective view of the multi-chip package according to another embodiment of the present invention.

도 3a 및 도 3b에 따른 또 다른 멀티 칩 패키지(400)는, 소정의 크기를 갖는슬롯(415)이 형성된 다이 패드(410)와, 제 1, 2반도체 칩(401a, 401b), 내부 리드(440a)와 외부 리드(440b)로 구성되는 리드(440), 및 회로 형성체를 포함하며, 본 실시예에서는 회로 형성체로서 테이프 회로 기판(460)이 사용된다.Another multi-chip package 400 according to FIGS. 3A and 3B includes a die pad 410 having a slot 415 having a predetermined size, first and second semiconductor chips 401a and 401b, and an internal lead. A lead 440 composed of a 440a and an external lead 440b, and a circuit forming body. In this embodiment, a tape circuit board 460 is used as the circuit forming body.

테이프 회로 기판(460)은 절연층(463)과 절연층(463) 상에 형성된 회로 패턴(461) 및 다이 패드(410)에 형성된 슬롯(415) 크기 이상으로 구비된 관통홀(465)이 형성된다. 이 때, 슬롯(415)은 최소한 제 1반도체 칩(401a)의 크기보다 크게 형성되고, 제 1반도체 칩(401a)은 제 2반도체 칩(401b)보다 작은 크기를 갖도록 구비되는 것이 바람직하다. 이와 같은 테이프 회로 기판(460) 관통홀(465)이 슬롯(415)에 대응되도록 다이 패드(410) 상에 접착된다.The tape circuit board 460 is formed with an insulating layer 463, a circuit pattern 461 formed on the insulating layer 463, and a through hole 465 having a size larger than a slot 415 formed in the die pad 410. do. At this time, the slot 415 is formed to be at least larger than the size of the first semiconductor chip 401a, the first semiconductor chip 401a is preferably provided to have a smaller size than the second semiconductor chip 401b. The tape circuit board 460 through hole 465 is adhered to the die pad 410 so as to correspond to the slot 415.

제 1반도체 칩(401a)과 제 2반도체 칩(401b)은 본딩 패드(403a, 403b)가 형성된 활성면과, 활성면과 반대되는 배면을 갖는다. 제 1, 2반도체 칩(401a, 401b)은 배면이 서로 접착되며, 센터 본딩 패드형 또는 에지 본딩 패드형 중 어느 하나의 형태로 구비될 수 있다. 제 2반도체 칩(401b)은 슬롯(415) 및 테이프 회로 기판(460)의 관통홀(465) 내부에 위치되고, 제 1반도체 칩(401a)의 배면은 다이 패드(410)에서 테이프 회로 기판이 접착된 면과 반대인 면에 접착 수단(450)에 의해 부착된다.The first semiconductor chip 401a and the second semiconductor chip 401b have an active surface on which the bonding pads 403a and 403b are formed, and a back surface opposite to the active surface. The first and second semiconductor chips 401a and 401b may be bonded to each other on a rear surface thereof and may be provided in one of a center bonding pad type or an edge bonding pad type. The second semiconductor chip 401b is located in the slot 415 and the through hole 465 of the tape circuit board 460, and the back surface of the first semiconductor chip 401a is formed at the die pad 410. It is attached by the bonding means 450 to the surface opposite to the bonded surface.

다이 패드(410) 주변에는 이를 중심으로 내부 리드(440a)와 외부 리드(440b)를 포함하는 리드(440)가 나열된다. 또한 제 1반도체 칩(401a)의 본딩 패드(403a)는 복수개의 제 1와이어(420a)에 의해 테이프 회로 기판(460)의 회로 패턴(463)과 전기적으로 연결되며, 회로 패턴(463)은 제 2와이어(420b)에 의해 내부 리드(440a)와 연결된다. 더불어 제 2반도체 칩(401b)의 본딩 패드(403b)는 내부 리드(440a)와 제 3와이어(420c)에 의해 연결된다. 이와 같은 제 1, 2반도체 칩(401a, 401b), 다이 패드(410), 내부 리드(440a), 테이프 회로 기판(460) 및 제 1, 2, 3와이어(420a, 420b, 420c)는 에폭시 몰딩 수지와 같은 성형 수지에 의해 봉지되어 패키지 몸체(430)가 형성된다.The lead 440 including the inner lead 440a and the outer lead 440b is arranged around the die pad 410. In addition, the bonding pads 403a of the first semiconductor chip 401a are electrically connected to the circuit patterns 463 of the tape circuit board 460 by the plurality of first wires 420a. It is connected to the inner lead 440a by two wires 420b. In addition, the bonding pad 403b of the second semiconductor chip 401b is connected by the internal lead 440a and the third wire 420c. The first and second semiconductor chips 401a and 401b, the die pad 410, the inner lead 440a, the tape circuit board 460, and the first, second and third wires 420a, 420b and 420c are epoxy molded. The package body 430 is formed by being sealed by a molding resin such as a resin.

이하 도면을 참조하여 본 발명의 또 다른 실시예에 따른 제조 공정을 설명하면 다음과 같다. 도 5a 내지 도 5c는 본 발명의 또 다른 실시예에 따른 멀티 칩 패키지의 제조 공정 단면도이다.Hereinafter, a manufacturing process according to another embodiment of the present invention will be described with reference to the accompanying drawings. 5A to 5C are cross-sectional views illustrating a manufacturing process of a multichip package according to another exemplary embodiment of the present invention.

(a) 도 3b를 참조하여 설명하면, 먼저 본딩 패드(403a)가 형성된 활성면과 활성면과 반대되는 배면이 구비된 제 1, 2반도체 칩(401a, 401b)과, 내부 리드(440a)와 외부 리드(도시하지 않음)로 구성된 리드(도시하지 않음)와, 슬롯(415)이 형성된 다이 패드(410), 및 슬롯(415)과 대응되는 관통홀(465)이 형성된 다이 패드(410) 상에 부착되는 테이프 회로 기판(460)을 준비하는 단계를 거친다. 슬롯(415)은 제 1반도체 칩(401a)의 크기 이상으로 형성되고, 리드 프레임 제조 공정 중 펀칭 공정에 의해 다이 패드(410)를 관통하여 마련된다.Referring to FIG. 3B, first and second semiconductor chips 401a and 401b having an active surface on which a bonding pad 403a is formed and a back surface opposite to the active surface, an internal lead 440a and On a lead (not shown) composed of an external lead (not shown), a die pad 410 having a slot 415, and a die pad 410 having a through hole 465 corresponding to the slot 415. Preparing a tape circuit board 460 attached to the. The slot 415 is formed to be larger than or equal to the size of the first semiconductor chip 401a and is provided through the die pad 410 by a punching process during the lead frame manufacturing process.

(b) 도 5a와 같이, 제 1반도체 칩(401a)의 배면과 제 2반도체 칩(401b)의 배면을 접착하는 단계를 거친다. 제 1반도체 칩(401a)과 제 2반도체 칩(401b)은 탄성중합체 또는 은 에폭시 등과 같은 접착 수단(450)에 의해 접착된다.5B, the back surface of the first semiconductor chip 401a and the back surface of the second semiconductor chip 401b are bonded to each other. The first semiconductor chip 401a and the second semiconductor chip 401b are bonded by an adhesive means 450 such as an elastomer or silver epoxy.

(c) 도 5b와 같이, 제 1반도체 칩(401a)을 슬롯(415) 및 테이프 회로 기판(460)에 형성된 관통홀(465) 내부에 위치시키고, 제 2반도체 칩(401b)의 배면을 다이 패드(410)에 부착하는 단계를 거친다. 제 2반도체 칩(401b)과 다이 패드(410) 사이에는 접착 수단이 개재되며 탄성중합체 또는 은 에폭시 등의 재질로 마련될 수 있다.5C, the first semiconductor chip 401a is positioned inside the through hole 465 formed in the slot 415 and the tape circuit board 460, and the back surface of the second semiconductor chip 401b is die-casted. The pad 410 is attached. An adhesive means may be interposed between the second semiconductor chip 401b and the die pad 410 and may be made of a material such as an elastomer or silver epoxy.

(d) 도 5c와 같이, 제 1반도체 칩(401a)의 본딩 패드(403a)와 테이프 회로 기판(460)의 회로 패턴(461)과 내부 리드(440a), 및 제 2반도체 칩(401b)과 내부 리드(440a)를 제 1, 2, 3와이어(420a, 420b, 420c)를 이용하여 전기적으로 연결하는 단계를 거친다. 회로 패턴(461)은 제 1와이어(420a)에 의해 제 1반도체 칩(401a)의 본딩 패드(403a)와 연결되고, 회로 패턴(461)은 제 2와이어(420b)에 의해 내부 리드(440a)와 연결되며, 제 2반도체 칩(401b)의 본딩 패드(403b)는 제 3와이어(420c)에 의해 내부 리드(440a)와 연결된다.As shown in FIG. 5C, the bonding pad 403a of the first semiconductor chip 401a and the circuit pattern 461 and the internal lead 440a of the tape circuit board 460, and the second semiconductor chip 401b, The inner lead 440a is electrically connected using the first, second, and third wires 420a, 420b, and 420c. The circuit pattern 461 is connected to the bonding pad 403a of the first semiconductor chip 401a by the first wire 420a, and the circuit pattern 461 is connected to the internal lead 440a by the second wire 420b. The bonding pad 403b of the second semiconductor chip 401b is connected to the internal lead 440a by the third wire 420c.

(e) 제 1, 2반도체 칩(401a, 401b), 내부 리드(440a), 제 1, 2, 3와이어(420a, 420b, 420c) 및 다이 패드(410)를 봉지하여 패키지 몸체(도 3a의 430)를 형성하는 단계를 거침으로써 본 발명에 따른 또 다른 멀티 칩 패키지(도 3a의 400)의 제조 공정은 완료된다.(e) The package body (see FIG. 3A) by encapsulating the first and second semiconductor chips 401a and 401b, the inner lead 440a, the first and second wires 420a, 420b and 420c and the die pad 410. The step of forming 430 completes the manufacturing process of another multi-chip package 400 of FIG. 3A according to the present invention.

상술한 실시예에서는 회로 형성체로서 테이프 회로 기판을 예로 들었으나, 금속 회로 패턴 등으로 구비될 수 있다. 금속 회로 패턴은 구리와 같은 금속층이 소정의 회로로 형성된 것으로 다이 패드에 형성된 슬롯 크기 이상으로 구비된 관통홀이 형성되고, 전도성 재질의 접착 수단에 의해 다이 패드 상에 접착된다.In the above-described embodiment, although the tape circuit board is taken as the circuit forming body, it may be provided as a metal circuit pattern or the like. In the metal circuit pattern, a metal layer such as copper is formed of a predetermined circuit, and a through hole provided with a slot size formed in the die pad or more is formed, and is adhered onto the die pad by an adhesive means of conductive material.

상술한 바와 같이 제 1반도체 칩과 내부 리드의 전기적 연결 시 회로 형성체를 매개로 하는 경우, 제 1반도체 칩과 내부 리드를 직접 연결하는 경우보다 각각의 와이어의 길이가 감소되므로 와이어 뒤틀림(tilt), 스위핑(sweeping) 등의 불량이 감소될 수 있으며, 와이어 루프 높이(loop height)가 감소되어 패키지 몸체의 두께가 감소될 수 있다.As described above, when the first semiconductor chip and the internal lead are connected to each other through a circuit forming body, the wires are twisted since the length of each wire is reduced than when the first semiconductor chip and the internal lead are directly connected. Defects, such as sweeping, can be reduced, and the wire loop height can be reduced to reduce the thickness of the package body.

한편, 본 명세서와 도면에 개시된 본 발명의 실시예들은 이해를 돕기 위해 특정 예를 제시한 것에 지나지 않으며, 본 발명의 범위를 한정하고자 하는 것은 아니다. 예를 들어, 회로 형성체는 테이프 회로 기판 이외에도 다층 기판을 사용할 수 있다. 더불어 여기에 개시된 실시예들 이외에도 본 발명의 기술적 사상에 바탕을 둔 다른 변형예들이 실시 가능하다는 것은, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 자명한 것이다.On the other hand, the embodiments of the present invention disclosed in the specification and drawings are merely presented specific examples to aid understanding and are not intended to limit the scope of the present invention. For example, the circuit forming body can use a multilayer board other than a tape circuit board. In addition, it is apparent to those skilled in the art that other modifications based on the technical idea of the present invention can be carried out in addition to the embodiments disclosed herein.

따라서, 본 발명의 구조 및 방법을 따른 멀티 칩 패키지는 반도체 칩의 배면끼리 부착되므로 반도체 칩의 손상, 와이어간의 접촉 및 반도체 칩의 선택 제한과 같은 문제가 발생되지 않는다. 또한 다이 패드 상에 형성된 슬릿 내부에 반도체 칩이 위치되도록 하므로, 다이 패드의 두께만큼 패키지의 두께가 감소될 수 있다. 더불어 반도체 칩과 내부 리드의 전기적 연결 시, 미세 회로와 미세 회로 폭을 갖는 회로 형성체를 매개수단으로 이용하므로, 반도체 칩과 내부 리드를 직접 연결하는 경우보다 각각의 와이어의 길이가 감소되므로 와이어 뒤틀림, 스위핑 등의 불량이 감소될 수 있으며, 와이어 루프 높이가 감소되어 패키지 몸체의 두께가 감소될 수 있다.Therefore, since the multi-chip package according to the structure and method of the present invention is attached to the back of the semiconductor chip, problems such as damage of the semiconductor chip, contact between wires, and limitation of selection of the semiconductor chip do not occur. In addition, since the semiconductor chip is positioned inside the slit formed on the die pad, the thickness of the package can be reduced by the thickness of the die pad. In addition, when the semiconductor chip and the internal lead are electrically connected, the circuit forming body having a fine circuit and a fine circuit width is used as an intermediary means, and thus the wire warpage is reduced because the length of each wire is reduced than when the semiconductor chip and the internal lead are directly connected. Defects, such as sweeping, can be reduced, and the wire loop height can be reduced to reduce the thickness of the package body.

Claims (6)

소정의 크기를 갖는 슬롯이 형성된 다이 패드;A slotted die pad having a predetermined size; 상기 다이 패드의 상부면에 부착되는 배면과, 상기 배면과 반대되며 본딩 패드가 형성된 활성면이 구비된 제 1반도체 칩;A first semiconductor chip having a back surface attached to an upper surface of the die pad and an active surface opposite to the back surface and having a bonding pad formed thereon; 상기 슬롯 내부에 위치하고, 상기 제 1반도체 칩의 배면과 부착되는 배면 및 상기 배면과 반대되고 본딩 패드가 구비된 제 2반도체 칩;A second semiconductor chip disposed inside the slot and attached to a rear surface of the first semiconductor chip and opposite to the rear surface and having a bonding pad; 상기 다이 패드를 중심으로 나열된 내부 리드와 외부 리드를 포함하는 리드;A lead including an inner lead and an outer lead arranged about the die pad; 상기 제 1, 2반도체 칩의 본딩 패드와 상기 내부 리드를 전기적으로 연결하는 복수개의 와이어; 및A plurality of wires electrically connecting the bonding pads of the first and second semiconductor chips and the internal leads; And 상기 제 1, 2반도체 칩, 다이 패드, 내부 리드 및 와이어를 봉지하여 형성된 패키지 몸체;를 포함하는 것을 특징으로 하는 멀티 칩 패키지.And a package body formed by encapsulating the first and second semiconductor chips, the die pad, the inner lead, and the wire. 소정의 크기를 갖는 슬롯이 형성된 다이 패드;A slotted die pad having a predetermined size; 적어도 상기 슬롯의 크기로 구비되는 관통홀이 형성되고, 상기 다이 패드의 하부면에 부착되는 회로 형성체;A circuit body formed with a through hole provided at least in the size of the slot and attached to a lower surface of the die pad; 상기 다이 패드의 하부면과 반대되는 상부면에 부착되는 배면과, 상기 배면과 반대되며 본딩 패드가 형성된 활성면이 구비된 제 1반도체 칩;A first semiconductor chip having a rear surface attached to an upper surface opposite to a lower surface of the die pad and an active surface opposite to the rear surface and having a bonding pad formed thereon; 상기 슬롯 및 상기 관통홀의 내부에 위치하고, 상기 제 1반도체 칩의 배면과 부착되는 배면 및 상기 배면과 반대되고 본딩 패드가 구비된 제 2반도체 칩;A second semiconductor chip disposed inside the slot and the through hole and attached to a rear surface of the first semiconductor chip and opposite to the rear surface and having a bonding pad; 상기 다이 패드를 중심으로 나열된 내부 리드와 외부 리드를 포함하는 리드;A lead including an inner lead and an outer lead arranged about the die pad; 상기 제 1반도체 칩의 본딩 패드와 상기 회로 형성체를 전기적으로 연결하는 복수개의 제 1와이어, 상기 회로 형성체와 상기 내부 리드를 연결하는 복수개의 제 2와이어, 및 상기 제 2반도체 칩의 본딩 패드와 상기 내부 리드를 연결하는 제 3와이어를 포함하는 복수개의 와이어; 및A plurality of first wires electrically connecting the bonding pads of the first semiconductor chip and the circuit former, a plurality of second wires connecting the circuit former and the internal leads, and a bonding pad of the second semiconductor chip A plurality of wires including a third wire connecting the inner lead to the inner lead; And 상기 제 1, 2반도체 칩, 다이 패드, 내부 리드, 회로 형성체 및 제 1, 2, 3와이어를 봉지하여 형성된 패키지 몸체;를 포함하는 것을 특징으로 하는 멀티 칩 패키지.And a package body formed by encapsulating the first and second semiconductor chips, the die pad, the inner lead, the circuit forming member, and the first, second and third wires. 제 2항에 있어서, 상기 회로 형성체는 상기 다이 패드의 하부면에 부착되는 절연층과, 상기 절연층 상에 형성된 회로 패턴, 및 적어도 상기 슬롯의 크기로 구비되는 관통홀을 포함하는 테이프 회로 기판인 것을 특징으로 하는 멀티 칩 패키지.The tape circuit board of claim 2, wherein the circuit former includes an insulating layer attached to a lower surface of the die pad, a circuit pattern formed on the insulating layer, and a through hole provided at least in the size of the slot. Multi-chip package characterized in that the. 제 2항에 있어서, 상기 회로 형성체는 상기 다이 패드의 하부면에 절연 재질의 접착 수단에 의해 부착된 금속 회로 패턴인 것을 특징으로 하는 멀티 칩 패키지.The multi-chip package according to claim 2, wherein the circuit former is a metal circuit pattern attached to a lower surface of the die pad by an adhesive means of insulating material. (a) 본딩 패드가 형성된 활성면과 상기 활성면과 반대되는 배면이 구비된 제 1, 2반도체 칩과 내부 리드와 외부 리드로 구성된 리드 및 슬롯이 형성된 다이 패드를 준비하는 단계;(a) preparing a die pad including first and second semiconductor chips having an active surface having a bonding pad formed thereon and a rear surface opposite to the active surface, and a lead and a slot formed of an inner lead and an outer lead; (b) 상기 제 1반도체 칩의 배면과 상기 제 2반도체 칩의 배면을 접착하는 단계;(b) adhering a back surface of the first semiconductor chip and a back surface of the second semiconductor chip; (c) 상기 제 1반도체 칩을 상기 슬롯 내부에 위치시키고, 상기 제 2 반도체 칩의 배면을 상기 다이 패드에 부착하는 단계;(c) placing the first semiconductor chip inside the slot and attaching a back surface of the second semiconductor chip to the die pad; (d) 상기 제 1, 2반도체 칩의 본딩 패드와 상기 내부 리드를 와이어 본딩하는 단계;(d) wire bonding the bonding pads of the first and second semiconductor chips and the internal leads; (e) 상기 제 1, 2반도체 칩, 내부 리드, 와이어 및 다이 패드를 봉지하여 패키지 몸체를 형성하는 단계;를 포함하는 것을 특징으로 하는 멀티 칩 패키지의 제조 방법.(e) encapsulating the first and second semiconductor chips, internal leads, wires, and die pads to form a package body. (a) 본딩 패드가 형성된 활성면과 상기 활성면과 반대되는 배면이 구비된 제 1, 2반도체 칩과, 내부 리드와 외부 리드로 구성된 리드와, 슬롯이 형성되고 다이 패드, 및 상기 다이 패드 상에 부착되며 상기 슬롯과 대응되는 크기로 구비된 관통홀이 형성된 회로 형성체를 준비하는 단계;(a) a first semiconductor chip having an active surface having a bonding pad formed thereon and a back surface opposite to the active surface, a lead composed of an inner lead and an outer lead, a slot formed thereon, and a die pad formed on the die pad; Preparing a circuit body having a through hole attached to the slot and having a size corresponding to that of the slot; (b) 상기 제 1반도체 칩의 배면과 상기 제 2반도체 칩의 배면을 접착하는 단계;(b) adhering a back surface of the first semiconductor chip and a back surface of the second semiconductor chip; (c) 상기 제 1반도체 칩을 슬롯 및 관통홀 내부에 위치시키고, 상기 제 2 반도체 칩의 배면을 상기 다이 패드에 부착하는 단계;(c) placing the first semiconductor chip inside a slot and a through hole, and attaching a rear surface of the second semiconductor chip to the die pad; (d) 상기 제 1반도체 칩의 본딩 패드와 상기 회로 형성체, 상기 회로 형성체와 상기 내부 리드, 및 상기 제 2반도체 칩과 상기 내부 리드를 와이어 본딩하는 단계;(d) wire bonding a bonding pad and the circuit former of the first semiconductor chip, the circuit former and the internal lead, and the second semiconductor chip and the internal lead; (e) 상기 제 1, 2반도체 칩, 내부 리드, 와이어 및 다이 패드를 봉지하여 패키지 몸체를 형성하는 단계;를 포함하는 것을 특징으로 하는 멀티 칩 패키지의 제조 방법.(e) encapsulating the first and second semiconductor chips, internal leads, wires, and die pads to form a package body.
KR1020010077885A 2001-12-10 2001-12-10 Multi chip package and manufacturing method thereof KR20030047405A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020010077885A KR20030047405A (en) 2001-12-10 2001-12-10 Multi chip package and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020010077885A KR20030047405A (en) 2001-12-10 2001-12-10 Multi chip package and manufacturing method thereof

Publications (1)

Publication Number Publication Date
KR20030047405A true KR20030047405A (en) 2003-06-18

Family

ID=29574024

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020010077885A KR20030047405A (en) 2001-12-10 2001-12-10 Multi chip package and manufacturing method thereof

Country Status (1)

Country Link
KR (1) KR20030047405A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100733251B1 (en) * 2005-09-29 2007-06-27 삼성전기주식회사 Double electronic components embedded PCB and manufacturing method thereof
WO2007145433A1 (en) * 2006-06-13 2007-12-21 Atlab Inc. Semiconductor device and touch sensor device
US7723831B2 (en) 2007-05-17 2010-05-25 Micron Technology, Inc. Semiconductor package having die with recess and discrete component embedded within the recess
KR20120015592A (en) * 2010-08-12 2012-02-22 삼성전자주식회사 Lead frame, and semiconductor package having the same
CN111540725A (en) * 2020-07-10 2020-08-14 甬矽电子(宁波)股份有限公司 Lead frame, square flat pin-free packaging structure and packaging method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990080278A (en) * 1998-04-15 1999-11-05 최완균 Multi-chip package
KR20010002214A (en) * 1999-06-12 2001-01-05 마이클 디. 오브라이언 A semiconductor packages and manufacturing method for it
KR20020061444A (en) * 2001-01-18 2002-07-24 주식회사 바른전자 Ultra Thin Stacked Semiconductor Chip Package and Lead Frame Used in the Package

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990080278A (en) * 1998-04-15 1999-11-05 최완균 Multi-chip package
KR20010002214A (en) * 1999-06-12 2001-01-05 마이클 디. 오브라이언 A semiconductor packages and manufacturing method for it
KR20020061444A (en) * 2001-01-18 2002-07-24 주식회사 바른전자 Ultra Thin Stacked Semiconductor Chip Package and Lead Frame Used in the Package

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100733251B1 (en) * 2005-09-29 2007-06-27 삼성전기주식회사 Double electronic components embedded PCB and manufacturing method thereof
WO2007145433A1 (en) * 2006-06-13 2007-12-21 Atlab Inc. Semiconductor device and touch sensor device
KR100792670B1 (en) * 2006-06-13 2008-01-09 주식회사 애트랩 Electrical touch sensor and touch sensor Device
US8053687B2 (en) 2006-06-13 2011-11-08 Atlab Inc. Semiconductor device and touch sensor device
US7723831B2 (en) 2007-05-17 2010-05-25 Micron Technology, Inc. Semiconductor package having die with recess and discrete component embedded within the recess
US7807502B2 (en) 2007-05-17 2010-10-05 Micron Technology, Inc. Method for fabricating semiconductor packages with discrete components
US7964946B2 (en) 2007-05-17 2011-06-21 Micron Technology, Inc. Semiconductor package having discrete components and system containing the package
US8174105B2 (en) 2007-05-17 2012-05-08 Micron Technology, Inc. Stacked semiconductor package having discrete components
KR20120015592A (en) * 2010-08-12 2012-02-22 삼성전자주식회사 Lead frame, and semiconductor package having the same
CN111540725A (en) * 2020-07-10 2020-08-14 甬矽电子(宁波)股份有限公司 Lead frame, square flat pin-free packaging structure and packaging method

Similar Documents

Publication Publication Date Title
US8866280B2 (en) Chip package
KR100477020B1 (en) Multi chip package
US6798049B1 (en) Semiconductor package and method for fabricating the same
US6982485B1 (en) Stacking structure for semiconductor chips and a semiconductor package using it
KR20030018204A (en) Multi chip package having spacer
US6429043B1 (en) Semiconductor circuitry device and method for manufacturing the same
KR100444228B1 (en) Chip package and method of fabricating the same
US7307352B2 (en) Semiconductor package having changed substrate design using special wire bonding
KR20010049663A (en) Semiconductor device
US20040036154A1 (en) High performance thermally enhanced package and method of fabricating the same
KR100401975B1 (en) Chip package and the method of fabricating the same
KR20030047405A (en) Multi chip package and manufacturing method thereof
TWM615149U (en) Quad flat no-lead package structure
KR100610917B1 (en) Wire bonding structure between semiconductor chip and substrate, and semiconductor package using it, and manufacturing method of the same
KR200169583Y1 (en) Ball grid array package
KR100437821B1 (en) semiconductor package and metod for fabricating the same
KR100390453B1 (en) semiconductor package with such circuit board and method for fabricating the same
KR100762871B1 (en) method for fabricating chip scale package
KR20030040922A (en) Chip scale package, manufacturing method thereof and stack chip scale package using the same
KR100481927B1 (en) Semiconductor Package and Manufacturing Method
KR100267220B1 (en) Semiconductor package and method for fabricating the same
KR20000076859A (en) Semiconductor device
KR20010068504A (en) Multichip module and assembly-stacked package using the same
KR100337456B1 (en) Frame for semiconductor package and manufacturing method of semiconductor package using same
KR20030025481A (en) flip-chip semiconductor package and method of manufacturing thereof

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E601 Decision to refuse application