KR100390453B1 - semiconductor package with such circuit board and method for fabricating the same - Google Patents
semiconductor package with such circuit board and method for fabricating the same Download PDFInfo
- Publication number
- KR100390453B1 KR100390453B1 KR10-1999-0067455A KR19990067455A KR100390453B1 KR 100390453 B1 KR100390453 B1 KR 100390453B1 KR 19990067455 A KR19990067455 A KR 19990067455A KR 100390453 B1 KR100390453 B1 KR 100390453B1
- Authority
- KR
- South Korea
- Prior art keywords
- base layer
- layer
- chip
- circuit board
- semiconductor chip
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/2901—Shape
- H01L2224/29011—Shape comprising apertures or cavities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
본 발명은 열방출 성능이 향상되고 경박단소화된 새로운 구조의 반도체 패키지 및 그의 제조시에 적용되는 회로기판에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package having a new structure with improved heat dissipation performance and to a light and short structure, and a circuit board applied in manufacturing thereof.
이를 위해, 본 발명은 상기 회로기판의 하부기층(1)에 구비된 칩-캐비티인 제2개방홀(9) 내에 위치하는 반도체 칩(3)과, 상기 반도체 칩(3)의 본딩패드와 상부기층(2)의 핑거부를 제1개방홀(8)을 통해 전기적으로 연결하는 전도성연결부재(5)인 골드와이어와, 상기 전도성연결부재(5)와 본딩패드 및 핑거부가 외부로 노출되지 않도록 봉지하는 몰드바디(6)와, 상기 상부기층(2)의 핑거부에 부착되는 솔더볼(7)을 포함하여서 되는 반도체 패키지가 제공된다.To this end, the present invention provides a semiconductor chip 3 located in the second opening hole 9, which is a chip-cavity provided in the lower substrate 1 of the circuit board, a bonding pad and an upper portion of the semiconductor chip 3. A gold wire, which is a conductive connecting member 5 that electrically connects the finger portion of the base layer 2 through the first opening hole 8, and the conductive connecting member 5, the bonding pad and the finger portion are sealed so as not to be exposed to the outside. There is provided a semiconductor package comprising a mold body 6 and a solder ball 7 attached to a finger portion of the upper base layer 2.
Description
본 발명은 반도체 패키지 및 그 제조방법에 관한 것으로서, 더욱 상세하게는 경박단소화된 새로운 구조의 BGA 패키지(BGA package ; Ball Grid Array package)에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package and a method of manufacturing the same, and more particularly, to a BGA package (BGA package) having a light and simple structure.
일반적으로, 반도체 산업에서 집적회로에 대한 패키징 기술은 소형화에 대한요구 및 실장 신뢰성을 만족시키기 위해 지금까지 계속 발전해오고 있다.In general, the packaging technology for integrated circuits in the semiconductor industry has been continuously developed to meet the demand for miniaturization and mounting reliability.
즉, 소형화에 대한 요구는 칩 스케일에 근접한 패키지에 대한 개발을 가속화시키고 있으며, 실장 신뢰성에 대한 요구는 실장작업의 효율성 및 실장후의 기계적·전기적 신뢰성을 향상시킬 수 있는 패키지 제조 기술에 대한 중요성을 부각시키고 있다.In other words, the demand for miniaturization is accelerating the development of packages close to the chip scale, and the demand for mounting reliability emphasizes the importance of package manufacturing technology that can improve the efficiency of mounting work and the mechanical and electrical reliability after mounting. I'm making it.
한편, 일반적으로 반도체소자는 집적회로가 형성된 웨이퍼 상태에서 낱개의 칩으로 각각 분리된 후, 이것을 플라스틱 패키지나 세라믹 패키지에 탑재하여 기판에의 실장이 용이하도록 조립하는 패키징 공정을 거치게 된다.On the other hand, in general, semiconductor devices are separated into individual chips in a wafer in which integrated circuits are formed, and then mounted in a plastic package or a ceramic package, and then subjected to a packaging process for assembling the substrate to facilitate mounting on the substrate.
이와 같이 행해지는 반도체소자에 대한 패키징 공정의 주목적은 기판이나 소켓에 실장하기 위한 형상의 확보와 기능보호에 있다고 할 수 있다.The main purpose of the packaging step for the semiconductor element thus performed is to secure the shape and protect the function for mounting on the substrate or the socket.
또한, 최근에는 집적회로의 고집적화에 따라 다핀화, 미세조립기술, 또 실장형태의 다양화에 따른 패키지의 다종류화 등, 조립공정과 관련된 기술도 각각 세분된 분야에 따라 크게 변화하고 있다.In addition, in recent years, technologies related to the assembly process, such as multi-pinning, micro-assembly technology, and package variety due to the diversification of the mounting type according to the high integration of integrated circuits, are also greatly changed according to the subdivided fields.
한편, 반도체 패키지는 실장형태 및 리드형태에 따라 여러 가지 유형으로 나뉘는데, 패키지의 대표적인 예로서는 DIP(Dual Inline Package)외에 QFP(Quad Flat Package), TSOP(Thin Small Outline Package), BGA 패키지( Ball Grid Array package), BLP(Bottom Leaded Package) 등이 있으며, 계속 다핀(多-pin)화 또는 경박단소(輕薄短小)화 되고 있다.On the other hand, semiconductor packages are divided into various types according to the mounting type and lead type. Examples of packages include quad flat packages (QFP), thin small outline packages (TSOP), and BGA packages (ball grid array) in addition to dual inline packages (DIP). packages, BLP (Bottom Leaded Package), and the like, and continue to be multi-pin or light and thin.
상기한 패키지 타입중, BGA 패키지(Ball Grid Array package)는 반도체 칩이 부착된 기판의 이면에 구형의 솔더볼을 소정의 상태로 배열(Array)하여아웃터리드(outer lead) 대신으로 사용하게 되며, 상기 BGA 패키지는 패키지 몸체(Package Body) 면적을 QFP(Quad Flat Package) 타입보다 작게 하는데 유리하며, QFP와는 달리 리드의 변형이 없는 장점이 있다.Among the above package types, the BGA package (Ball Grid Array package) is used to replace the outer lead by arranging the spherical solder balls in a predetermined state on the back surface of the substrate on which the semiconductor chip is attached. The BGA package is advantageous in making the package body area smaller than the Quad Flat Package (QFP) type, and unlike QFP, there is an advantage of no deformation of the lead.
도 1을 참조하여 종래 BGA 패키지 제작을 위한 공정을 개략적으로 설명하면 다음과 같다.Referring to Figure 1 schematically illustrating a process for manufacturing a conventional BGA package as follows.
먼저, 웨이퍼 상면에 집적회로를 형성하는 FAB(Fabrication)공정이 끝난 상태에서 웨이퍼에 형성된 반도체 칩을 개별적으로 분리하기 위한 소잉(sawing)을 실시한다.First, sawing is performed to individually separate semiconductor chips formed on a wafer in a state in which an FAB (fabrication) process for forming an integrated circuit on the upper surface of the wafer is completed.
그 다음, 내부에 회로패턴(18)이 형성된 회로기판(10)이 공정에 투입됨에 따라 회로기판(10) 상면에 접착제(11)를 도포하여 절단된 반도체 칩(12)을 본딩시키게 되며, 칩 본딩이 끝난 후에는 반도체 칩(12)에 형성된 본딩패드(13)와 회로기판(10)에 형성된 소정의 회로패턴(18) 사이를 골드와이어(14)를 이용하여 서로 전기적으로 연결시키는 와이어 본딩을 실시하게 된다.Then, as the circuit board 10 having the circuit pattern 18 formed therein is introduced into the process, the adhesive 11 is applied to the upper surface of the circuit board 10 to bond the cut semiconductor chip 12. After the bonding is finished, the wire bonding is electrically connected between the bonding pad 13 formed on the semiconductor chip 12 and the predetermined circuit pattern 18 formed on the circuit board 10 using gold wires 14. Will be implemented.
그리고, 와이어 본딩이 완료된 후에는 반도체 칩(12) 및 금속세선(14)을 봉지수지인 EMC(15)(Epoxy Molding Compound)로 몰딩하는 몰딩 공정을 수행하게 되며, 몰딩이 완료된 다음에는 스크린 프린팅(Screen Printing)을 통해 회로기판(10) 저면에 일정 패턴(2)의 솔더 페이스트(Solder paste)를 전사하여 플럭스(Flux)를 코팅시키는 플럭스 코팅(Flux Coating) 공정을 수행하게 된다.After the wire bonding is completed, a molding process of molding the semiconductor chip 12 and the fine metal wires 14 into an epoxy molding compound (EMC) 15, which is an encapsulation resin, is performed. After the molding is completed, screen printing ( Through Screen Printing, a flux coating process is performed in which a solder paste of a predetermined pattern 2 is transferred to a bottom surface of the circuit board 10 to coat flux.
또한, 플럭스(16) 코팅 공정이 끝난 다음에는 회로기판(10) 저면에 일정 패턴으로 코팅된 플럭스에 솔더볼(17)을 부착시킨 다음, 열처리 공정인리플로우(Reflow)를 수행하여 솔더볼(17)을 회로기판(10)에 견고히 고정시키게 된다.In addition, after the flux 16 coating process is completed, the solder ball 17 is attached to the flux coated with a predetermined pattern on the bottom surface of the circuit board 10, and then the solder ball 17 is performed by performing a reflow process. To be firmly fixed to the circuit board 10.
그 후, 클리닝 및 마킹 공정을 거쳐 완제품인 BGA 패키지를 출하하게 된다.After that, the BGA package, which is a finished product, is shipped through a cleaning and marking process.
그러나, 이와 같은 종래의 BGA 패키지는 회로기판 상부면에 반도체 칩이 부착되고, 상기 회로기판 상부면상에 부착된 반도체 칩 및 상기 반도체 칩의 본딩패드와 회로기판의 회로패턴 사이를 전기적으로 연결하는 금속세선을 봉지하게 되므로 인해, 패키지의 전체적인 높이(h)가 높아지는 되는 단점이 있었다.However, such a conventional BGA package has a semiconductor chip attached to an upper surface of a circuit board, and a metal that electrically connects a semiconductor chip attached on the upper surface of the circuit board and a bonding pad of the semiconductor chip and a circuit pattern of the circuit board. Since the thin wire is encapsulated, the overall height (h) of the package is increased.
또한, 종래에는 회로기판 상에 솔더볼 부착시, 반도체 칩 영역을 벗어난 위치에 솔더볼이 부착되므로 인해 솔더볼 부착 위치 확보를 위해 반도체 패키지의 전체적인 사이즈가 커지게 되는 단점이 있었다.In addition, in the related art, when solder balls are attached on a circuit board, solder balls are attached to positions outside the semiconductor chip area, and thus, the overall size of the semiconductor package is increased to secure the solder ball attachment positions.
본 발명은 상기한 제반 문제점을 해결하기 위한 것으로서, 회로기판의 두께 내에 반도체 칩이 위치하도록 함과 더불어 회로기판의 반도체 칩 영역 상부에 솔더볼이 부착될 수 있도록 구조를 개선하여 경박단소화된 BGA 패키지(BGA package ; Ball Grid Array package)를 제공함과 더불어 소자 동작시의 열방출 성능을 향상시킬 수 있도록 하는데 그 목적이 있다.The present invention is to solve the above-mentioned problems, the thin and short BGA package by improving the structure so that the solder ball is attached to the upper portion of the semiconductor chip area of the circuit board and the semiconductor chip is located within the thickness of the circuit board In addition to providing a (BGA package; Ball Grid Array package), the aim is to improve heat dissipation performance during device operation.
한편, 본 발명의 또 다른 목적은 대면적에서 많은 수의 BGA 패키지를 한번에 제조하므로써 하므로써, 패키지 제조시 생산성을 향상시킬 수 있도록 하는데 그 목적이 있다.On the other hand, another object of the present invention is to produce a large number of BGA packages in a large area at one time, to improve the productivity in the package manufacturing.
도 1은 종래의 일반적인 BGA 패키지를 나타낸 종단면도1 is a longitudinal cross-sectional view showing a conventional BGA package of the prior art
도 2는 본 발명에 적용되는 회로기판의 일실시예를 나타낸 종단면도Figure 2 is a longitudinal cross-sectional view showing an embodiment of a circuit board applied to the present invention
도 3a 내지 도 3c는 도 2의 회로기판에 대한 제조 과정을 나타낸 종단면도로서,3A to 3C are longitudinal cross-sectional views illustrating a manufacturing process of the circuit board of FIG. 2.
도 3a는 상부기층이과 하부기층이 접합되기 전의 상태도3A is a state diagram before the upper base layer and the lower base layer are joined.
도 3b는 도 3a의 접합후 상태도Figure 3b is a state diagram after the bonding of Figure 3a
도 3c는 상부기층에 솔더마스크를 형성한 후의 상태도3c is a state diagram after forming a solder mask on the upper base layer
도 4a 내지 도 4e는 도 2의 회로기판을 이용한 본 발명 반도체 패키지 제조 과정을 나타낸 종단면도로서,4A through 4E are longitudinal cross-sectional views illustrating a process of manufacturing a semiconductor package of the present invention using the circuit board of FIG. 2.
도 4a는 회로기판의 저면의 칩-캐비티에 칩을 부착시킨 후의 상태도4A is a state diagram after attaching the chip to the chip-cavity of the bottom surface of the circuit board.
도 4b는 반도체 칩의 본딩패드와 기판의 핑거부를 와이어 본딩한 후의 상태도4B is a state diagram after wire bonding a bonding pad of a semiconductor chip and a finger portion of a substrate.
도 4c는 와이어 봉지후의 상태도4C is a state diagram after the wire encapsulation
도 4d는 단위 패키지 별로 소잉후의 상태도4D is a state diagram after sawing for each unit package
도 4e는 솔더볼 부착후의 반도체 패키지 단품을 나타낸 종단면도4E is a longitudinal cross-sectional view of a semiconductor package unit after solder ball is attached.
도 5는 본 발명의 제2실시예에 따른 반도체 패키지를 나타낸 종단면도5 is a longitudinal sectional view showing a semiconductor package according to a second embodiment of the present invention;
도 6은 본 발명의 제3실시예에 따른 반도체 패키지를 나타낸 종단면도6 is a longitudinal sectional view showing a semiconductor package according to a third embodiment of the present invention;
도 7은 본 발명의 제4실시예에 따른 반도체 패키지를 나타낸 종단면도7 is a longitudinal sectional view showing a semiconductor package according to a fourth embodiment of the present invention;
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
1:하부기층 100:수지층1: lower base layer 100: resin layer
101:금속층 2:상부기층101: metal layer 2: upper base layer
200:수지층 201:회로패턴200: resin layer 201: circuit pattern
202:솔더마스크 3:반도체 칩202: solder mask 3: semiconductor chip
4:접착부재 5:전도성연결부재4: adhesive member 5: conductive connecting member
6:몰드바디 7:솔더볼6: Molded body 7: Solder ball
8:제1개방홀 9:제2개방홀8: first opening hall 9: second opening hall
상기한 목적을 달성하기 위한 본 발명은 회로패턴 및 제1개방홀이 형성된 상부기층과 상기 제1개방홀에 연통하며 상하부기층의 접합시 칩-캐비티를 이루는 제2개방홀이 구비된 하부기층으로 이루어진 회로기판과, 상기 회로기판의 칩-캐비티 내에 부착되는 반도체 칩과, 상기 반도체 칩의 본딩패드와 상기 회로기판의 상부기층에 구비된 핑거부를 전기적으로 연결하는 전도성연결부재와, 상기 반도체 칩의 본딩패드와 전도성연결부재 및 핑거부가 외부로부터 보호되도록 감싸는 몰드바디와, 상기 회로기판의 상부기층에 부착되는 솔더볼을 포함하여서 되는 반도체 패키지가 제공된다.The present invention for achieving the above object is a lower base layer having a circuit pattern and a first opening is formed in the upper base layer and the second opening hole communicating with the first opening and forming a chip-cavity when the upper and lower base layers are bonded. A circuit board, a semiconductor chip attached to a chip cavity of the circuit board, a conductive connection member electrically connecting a bonding pad of the semiconductor chip to a finger part provided on an upper layer of the circuit board, Provided is a semiconductor package including a bonding pad, a conductive connection member, a mold body surrounding a finger portion to be protected from the outside, and a solder ball attached to an upper layer of the circuit board.
한편, 상기한 목적을 달성하기 위한 본 발명의 또 다른 형태는, 회로패턴 및 제1개방홀이 구비된 상부기층과 상기 제1개방홀에 연통하며 하부기층과의 접합시 칩-캐비티를 이루는 제2개방홀이 구비된 하부기층으로 이루어진 회로기판의 칩-캐비티 내에 반도체 칩을 부착하는 단계와, 상기 상부기층의 핑거부와 반도체 칩의 본딩패드를 전도성연결부재를 이용하여 연결하는 단계와, 상기 반도체 칩의 본딩패드와 핑거부 및 전도성연결부재가 외부로부터 보호되도록 봉지수지를 이용하여 봉지하는 단계와, 상기 상부기층에 형성된 회로패턴의 볼부착부에 솔더볼을 부착하는 단계를 포함하여서 됨을 특징으로 하는 반도체 패키지 제조방법이 제공된다.On the other hand, another aspect of the present invention for achieving the above object, the circuit pattern and the first base is provided with a chip-cavity in communication with the upper base layer and the first opening and the lower base layer is provided; Attaching a semiconductor chip to a chip-cavity of a circuit board having a lower base layer having two openings, connecting a finger portion of the upper base layer and a bonding pad of the semiconductor chip using a conductive connection member; Sealing the bonding pad, the finger portion, and the conductive connection member of the semiconductor chip using an encapsulation resin; and attaching solder balls to the ball attachment portion of the circuit pattern formed on the upper base layer. A semiconductor package manufacturing method is provided.
이하, 본 발명의 각 실시예를 첨부도면 도 2 내지 도 7을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, each embodiment of the present invention will be described in detail with reference to FIGS. 2 to 7.
우선, 도 2 내지 도 4e를 참조하여 본 발명의 제1실시예에 적용되는 회로기판 및 이를 이용한 반도체 패키지에 대해 설명하고자 한다.First, a circuit board applied to a first embodiment of the present invention and a semiconductor package using the same will be described with reference to FIGS. 2 to 4E.
도 2는 본 발명의 제1실시예에 따른 회로기판을 나타낸 종단면도로서, 비어홀(via hole) 및 제1개방홀(8)이 구비되며 회로패턴(201)이 형성된 상부기층(2)과, 비어홀과 제2개방홀(9)이 형성되며 상기 상부기층(2) 하부면상에 부착되는 하부기층(1)으로 구성되며, 상기 상부기층(2)과 하부기층(1)과의 접합시 상기 제2개방홀(9)이 칩-캐비티(chip-cavity)를 이루게 된다.FIG. 2 is a longitudinal cross-sectional view of a circuit board according to a first embodiment of the present invention, including an upper base layer 2 having a via hole and a first opening hole 8 and a circuit pattern 201 formed therein; A via hole and a second opening hole 9 are formed, and the lower base layer 1 is attached to the lower surface of the upper base layer 2, and the bonding of the upper base layer 2 and the lower base layer 1 is performed. Two open holes 9 form a chip-cavity.
이 때, 상기 상부기층(2)은 비어홀 및 제1개방홀(8)이 구비된 BT수지등으로 된 수지층(200)과, 상기 수지층(200) 상면에 형성되는 회로패턴(201)과, 상기 회로패턴(201) 상면의 핑거부 및 볼부착부를 제외한 영역에 도포되는 솔더마스크(202)로 이루어진다.In this case, the upper base layer 2 may include a resin layer 200 made of a BT resin having a via hole and a first opening hole 8, and a circuit pattern 201 formed on an upper surface of the resin layer 200. The solder mask 202 is applied to an area excluding the finger part and the ball attaching part of the upper surface of the circuit pattern 201.
그리고, 상기 하부기층(1)은 제2개방홀(9)이 형성되며 비어홀이 구비된 수지층(100)과 상기 수지층(100) 상하부에 형성되는 Cu등의 금속층(101)으로 이루어진다.In addition, the lower base layer 1 includes a resin layer 100 having a second opening hole 9 and a via hole, and a metal layer 101 such as Cu formed above and below the resin layer 100.
이와 같이 구성된 본 발명의 제1실시예에 따른 회로기판의 제조과정을 도 3a 내지 도 3c를 참조하여 설명하면 다음과 같다.The manufacturing process of the circuit board according to the first embodiment of the present invention configured as described above will be described with reference to FIGS. 3A to 3C.
먼저, 도 3a에 나타낸 바와 같이, 비어홀 및 제1개방홀(8)이 구비된 수지층(200)과 상기 수지층(200) 상면에 형성되는 회로패턴(201)으로 이루어진 상부기층(2)(上部基層)과, 제2개방홀(9)이 형성되며 비어홀이 구비된 수지층(100)과 상기 수지층(100) 상하부면에 형성되는 금속층(101)으로 구성된 하부기층(1)(下部基層)을 각각 준비한다.First, as shown in FIG. 3A, the upper base layer 2 (which includes the resin layer 200 having the via hole and the first opening hole 8) and the circuit pattern 201 formed on the upper surface of the resin layer 200 ( The lower base layer 1 (upper base), the lower base layer 1 formed of a resin layer 100 having a via hole and a metal layer 101 formed on upper and lower surfaces of the resin layer 100 having a second opening hole 9 formed therein. Prepare each).
이와 같이 상부기층(2) 및 하부기층(1)이 준비된 상태에서, 도 3b에 나타낸 바와 같이, 상부기층(2) 하부에 하부기층(1)을 접합하게 된다.In the state where the upper base layer 2 and the lower base layer 1 are prepared as described above, as shown in FIG. 3B, the lower base layer 1 is bonded to the lower portion of the upper base layer 2.
이 때, 상기 상부기층(2)과 하부기층(1)은 상부기층(2)의 제1개방홀(8)과 하부기층(1)의 제2개방홀(9)이 연통되도록 접합하며, 이에 따라 상기 제2개방홀(9)은 반도체 칩(3)이 안착되는 칩-캐비티를 이루게 된다.In this case, the upper base layer 2 and the lower base layer 1 are bonded to each other so that the first opening hole 8 of the upper base layer 2 and the second opening hole 9 of the lower base layer 1 communicate with each other. Accordingly, the second opening hole 9 forms a chip cavity in which the semiconductor chip 3 is seated.
한편, 상부기층(2)과 하부기층(1)간의 접합이 완료된 후에는, 도 3c에 나타낸 바와 같이, 상기 상부기층(2)의 회로패턴(201)의 핑거부 및 볼부착부를 제외한 전 영역이 커버되도록 상부기층(2) 상부면에 솔더마스크(202)를 형성하므로써, 회로기판의 제조를 완료하게 된다.On the other hand, after the bonding between the upper base layer 2 and the lower base layer 1 is completed, as shown in FIG. 3C, all areas except the finger part and the ball attaching part of the circuit pattern 201 of the upper base layer 2 are formed. By forming the solder mask 202 on the upper surface of the upper substrate layer 2 so as to cover, the manufacture of the circuit board is completed.
이하, 상기와 같이 제조된 회로기판을 이용한 반도체 패키지의 구성 및 제조과정은 다음과 같다.Hereinafter, the configuration and manufacturing process of the semiconductor package using the circuit board manufactured as described above are as follows.
도 4e는 도 2의 회로기판을 이용하여 제조된 반도체 패키지를 나타낸 종단면도로서, 본 발명의 제1실시예에 따른 회로기판을 이용하여 제조된 반도체 패키지는, 회로패턴(201) 및 제1개방홀(8)이 형성된 상부기층(2)과 상기 제1개방홀(8)에 연통하며 상하부기층(1)의 접합시 칩-캐비티를 이루는 제2개방홀(9)이 구비된 하부기층(1)으로 이루어진 회로기판과, 상기 하부기층(1)에 구비된 칩-캐비티인 제2개방홀(9) 내에 위치하며 센터에 본딩패드가 형성된 센터패드(Center pad) 타입의 반도체 칩(3)과, 상기 반도체 칩의 센터에 형성된 본딩패드와 상부기층(2)의 핑거부를 제1개방홀(8)을 통해 전기적으로 연결하는 전도성연결부재(5)인 골드와이어와, 상기 전도성연결부재(5)와 본딩패드 및 핑거부가 외부로 노출되지 않도록 봉지하는 몰드바디(6)와, 상기 상부기층(2)의 핑거부에 부착되는 솔더볼(7)을 포함하여 구성된다.4E is a longitudinal cross-sectional view illustrating a semiconductor package manufactured using the circuit board of FIG. 2. The semiconductor package manufactured using the circuit board according to the first exemplary embodiment of the present invention includes a circuit pattern 201 and a first opening. The lower base layer 1 having a second opening hole 9 which communicates with the upper base layer 2 on which the holes 8 are formed and the first opening hole 8 and forms a chip-cavity when the upper and lower base layers 1 are bonded. A center pad type semiconductor chip 3 located in a second opening hole 9, which is a chip-cavity provided in the lower base layer 1, and having a bonding pad formed at a center thereof; And a gold wire, which is a conductive connecting member 5 that electrically connects the bonding pad formed at the center of the semiconductor chip and the finger portion of the upper base layer 2 through the first opening hole 8, and the conductive connecting member 5. And a mold body 6 encapsulating the bonding pad and the finger portion so as not to be exposed to the outside, and the upper base layer 2. Is configured to include a solder ball (7) attached to the refuse.
이 때, 상기 회로기판의 칩-캐비티 내에 위치하는 반도체 칩(3)은, 칩-캐비티를 이루는 제2개방홀(9) 내측면으로부터 일정간격 이격되도록 부착된다.At this time, the semiconductor chip 3 located in the chip cavity of the circuit board is attached to be spaced apart from the inner surface of the second opening hole 9 constituting the chip cavity.
한편, 상기 칩-캐비티 내에 위치하는 반도체 칩(3)과 상부기층(2) 사이에는 반도체 칩(3)을 부착시키기 위한 접착부재(4)가 개재(介在)된다.Meanwhile, an adhesive member 4 for attaching the semiconductor chip 3 is interposed between the semiconductor chip 3 and the upper base layer 2 positioned in the chip cavity.
이 때, 상기 접착부재(4)는 사각고리 형상을 이루게 되며, 사각고리 형상처럼 전체적으로 이어져 있지 않더라도 무방하다.At this time, the adhesive member 4 may have a square ring shape, and may not be connected as a whole as a square ring shape.
이와 같이 구성된 본 발명 반도체 패키지의 제조 과정은 다음과 같다.The manufacturing process of the semiconductor package of the present invention configured as described above is as follows.
먼저, 도 4a에 나타낸 바와 같이, 회로패턴(201) 및 제1개방홀(8)이 구비된 상부기층(2)과 상기 제1개방홀(8)에 연통하며 하부기층(1)과의 접합시 칩-캐비티를 이루는 제2개방홀(9)이 구비된 하부기층(1)으로 이루어진 회로기판의 칩-캐비티 내에 반도체 칩(3)을 부착하게 된다.First, as shown in FIG. 4A, the upper base layer 2 provided with the circuit pattern 201 and the first opening hole 8 communicates with the first opening hole 8 and is bonded to the lower base layer 1. The semiconductor chip 3 is attached to the chip cavity of the circuit board including the lower base layer 1 having the second opening hole 9 forming the sea chip cavity.
이 때, 상기 상부기층(2) 저면의 제1개방홀(8) 주변에는 접착부재(4)가 구비된다.At this time, the adhesive member 4 is provided around the first opening hole 8 at the bottom of the upper base layer 2.
그 후, 도 4b에 나타낸 바와 같이, 상기 상부기층(2)의 핑거부와 반도체 칩(3)의 본딩패드를 전도성연결부재(5)인 골드와이어를 이용하여 연결하는 와이어 본딩 공정을 수행하게 된다.Thereafter, as illustrated in FIG. 4B, a wire bonding process of connecting the finger portion of the upper base layer 2 and the bonding pad of the semiconductor chip 3 using the gold wire, which is the conductive connecting member 5, is performed. .
그리고, 와이어 본딩후에는 반도체 칩(3)의 본딩패드와 핑거부 및 전도성연결부재(5)가 외부로부터 보호되도록 봉지수지를 이용하여 봉지하여 도 4c에 나타낸 바와 같이 몰드바디(6)를 형성하게 되며, 몰드바디(6) 형성 후에는 회로기판을 소잉하여 도 4d에서와 같이 개별 패키지 별로 분리시키게 된다.After the wire bonding, the bonding pad, the finger portion, and the conductive connecting member 5 of the semiconductor chip 3 are encapsulated using an encapsulation resin so as to be protected from the outside to form the mold body 6 as shown in FIG. 4C. After the mold body 6 is formed, the circuit board is sawed and separated into individual packages as shown in FIG. 4D.
이어, 상기 회로기판의 상부기층(2)에 형성된 회로패턴(201)의 볼부착부에 솔더볼(7)을 부착하면 도 4e에서와 같은 형태를 갖는 반도체 패키지가 완성된다.Subsequently, when the solder ball 7 is attached to the ball attachment portion of the circuit pattern 201 formed on the upper substrate layer 2 of the circuit board, a semiconductor package having a shape as shown in FIG. 4E is completed.
한편, 상기에서 솔더볼(7)의 부착이 완료된 상태에서 개별 패키지 별로 소잉을 하지 않고 몰드바디(6) 형성후에 소잉을 먼저 행하는 이유는 회로기판의 소잉시 기판에 가해지는 충격에 의해 솔더볼(7)이 기판에서 탈락하는 현상을 방지하기 위함이다.On the other hand, in the state where the solder ball (7) is attached in the complete state, the first sawing after forming the mold body (6) without sawing for each individual package is the reason for first sawing the solder ball 7 due to the impact applied to the substrate when sawing the circuit board This is to prevent the phenomenon of falling off from the substrate.
따라서, 솔더볼(7)과 회로기판과의 접합 신뢰성만 충분히 보장된다면, 솔더볼(7) 부착까지 완료한 상태에서 회로기판을 단위 패키지 별로 분리하여도 무방함은 물론이다.Therefore, if only the soldering reliability of the solder ball 7 and the circuit board is sufficiently secured, the circuit board may be separated for each unit package in a state where the solder ball 7 is completed.
상기한 바와 같이 완성된 본 발명의 반도체 패키지는, 우선 본 발명의 반도체 패키지는 회로기판의 칩-캐비티 내측에 반도체 패키지가 부착되어 회로기판 외부로 노출되지 않는 구조여서 반도체 칩(3)의 두께만큼 패키지의 전체적인 두께를 줄이므로써, 패키지의 경박화가 가능하게 된다.In the semiconductor package of the present invention completed as described above, the semiconductor package of the present invention has a structure in which the semiconductor package is attached to the inside of the chip-cavity of the circuit board so that the semiconductor package is not exposed to the outside of the circuit board. By reducing the overall thickness of the package, the package can be made thinner.
또한, 본 발명의 반도체 패키지는 회로기판의 칩-캐비티 내측에 반도체 패키지가 부착되고, 회로기판의 제1개방홀(8)을 통해 칩 영역 내에서 와이어본딩이 이루어지고 와이어 본딩된 좁은 영역만이 봉지되어, 솔더볼(7)이 봉지후 형성된 몰드바디(6) 외측 영역에 부착가능하므로 인해, 종래 BGA 패키지와 같이 몰드바디(6) 형성면 반대편에 솔더볼(7)이 부착될 때에 비해 몰드바디(6)의 높이 만큼 패키지의 전체적인 두께를 줄일 수 있게 된다. ,In addition, in the semiconductor package of the present invention, the semiconductor package is attached to the inside of the chip-cavity of the circuit board, and wire bonding is performed in the chip area through the first opening hole 8 of the circuit board. Since the solder ball 7 can be attached to an outer region of the mold body 6 formed after encapsulation, the mold body (i.e., when the solder ball 7 is attached to the opposite side of the mold body 6 forming surface as in the conventional BGA package) By 6), the overall thickness of the package can be reduced. ,
한편, 본 발명의 반도체 패키지는 회로기판의 상부기층(2) 상에 부착되는 솔더볼(7)이 종래의 BGA와는 달리 반도체 칩 사이즈 내부 영역에도 부착되므로 인해, 입출력단자 수를 늘릴 수 있으며, 패키지 사이즈의 단소화가 가능하게 된다.Meanwhile, in the semiconductor package of the present invention, since the solder balls 7 attached on the upper substrate 2 of the circuit board are also attached to the internal area of the semiconductor chip size unlike the conventional BGA, the number of input / output terminals can be increased, and the package size can be increased. Can be reduced.
뿐만 아니라, 본 발명의 반도체 패키지는 종래 BGA 패키지에 비해 봉지 영역이 좁아 봉지수지의 양이 줄어들게 되며, 이에 따라 제조 비용을 절감할 수 있게 된다.In addition, the semiconductor package of the present invention has a narrower encapsulation area than the conventional BGA package, thereby reducing the amount of encapsulating resin, thereby reducing manufacturing costs.
즉, 본 발명에서는 회로기판의 칩-캐비티 내측에 반도체 칩이 부착되고, 회로기판의 제1개방홀(8)을 통해 반도체 칩(3) 사이즈 영역 내에서 와이어본딩이 이루어지므로 와이어의 길이가 짧고 봉지영역 또한 매우 좁아, 봉지수지양이 종래에 비해 현저히 줄어들게 된다.That is, in the present invention, the semiconductor chip is attached to the inside of the chip-cavity of the circuit board, and wire bonding is performed in the size area of the semiconductor chip 3 through the first opening hole 8 of the circuit board. The encapsulation area is also very narrow, so that the amount of encapsulated resin is significantly reduced compared with the conventional one.
또한, 본 발명의 반도체 패키지는 회로기판의 구조적인 특징상 하부기층(1)의 전면적에 걸쳐 Cu층이 형성되므로 인해 반도체소자의 작동시 열방출 성능이 기존의 BGA 구조에 비해 증대되며, 이에 따라 패키지의 신뢰성을 향상시킬 수 있게 된다.In addition, in the semiconductor package of the present invention, since the Cu layer is formed over the entire area of the lower substrate layer 1 due to the structural characteristics of the circuit board, the heat dissipation performance of the semiconductor device is increased compared to the conventional BGA structure. The reliability of the package can be improved.
한편, 도 5는 본 발명의 제2실시예에 따른 BGA 패키지를 나타낸 종단면도로서, 본 발명의 제2실시예에 따른 반도체 패키지는 회로기판의 하부기층(1)의 구조가 제1실시예에서와 다르며, 나머지 구성은 동일하다.5 is a longitudinal cross-sectional view illustrating a BGA package according to a second embodiment of the present invention. In the semiconductor package according to the second embodiment of the present invention, the structure of the lower base layer 1 of the circuit board is shown in FIG. And the rest of the configuration is the same.
즉, 본 발명의 제2실시예의 경우에는, 하부기층(1) 전체가 Cu층 또는 그 밖의 열전도성이 뛰어난 금속재질로 구성되어, 방열성능이 극대화되도록 한 점에 특징이 있다.That is, in the case of the second embodiment of the present invention, the entire lower base layer 1 is composed of a Cu layer or other metal material having excellent thermal conductivity, so that the heat dissipation performance is maximized.
그리고, 도 6은 본 발명의 제3실시예에 따른 반도체 패키지를 나타낸 종단면도로서, 본 발명의 제3실시예에서는 하부기층(1)이 전술한 제1 및 제2 실시예에서와 달라지게 된다.6 is a longitudinal cross-sectional view illustrating a semiconductor package according to a third embodiment of the present invention, in which a lower base layer 1 is different from the first and second embodiments described above. .
즉, 본 발명의 제3실시예에 따른 반도체 패키지는 회로기판을 구성하는 하부기층(1)의 구조가, BT수지등으로 된 수지층(100)과 상기 수지층(100) 상면에 형성되는 금속층(101)으로 이루어지며, 이와 같이 할 경우에는 전술한 실시예에 비해 반도체 패키지의 무게를 줄일 수 있게 된다.That is, in the semiconductor package according to the third embodiment of the present invention, the structure of the lower base layer 1 constituting the circuit board is a resin layer 100 made of BT resin or the like and a metal layer formed on the upper surface of the resin layer 100. 101, the weight of the semiconductor package can be reduced compared to the above-described embodiment.
또한, 도 7은 본 발명의 제4실시예에 따른 반도체 패키지를 나타낸 종단면도로서, 이 경우는 제3실시예에 따른 반도체 패키지와 나머지 구성은 동일하며, 칩-캐비티 내에 부착되는 반도체 칩(3)이 칩-캐비티 내주면에 완전히 밀착되는 점이 다르다.7 is a longitudinal cross-sectional view illustrating a semiconductor package according to a fourth embodiment of the present invention, in which case the semiconductor package 3 according to the third embodiment has the same configuration as the semiconductor package 3 and is attached to the chip cavity. ) Is completely in contact with the inner circumferential surface of the chip-cavity.
한편, 전술한 제1실시예 및 제2실시예에 따른 반도체 패키지에서도 제4실시예에서와 같이 칩-캐비티 내측면에 반도체 칩(3)의 외측면이 완전히 밀착되도록 삽입되어도 무방함은 물론이다.Meanwhile, in the semiconductor packages according to the first and second embodiments described above, the outer surface of the semiconductor chip 3 may be inserted in close contact with the inner surface of the chip cavity, as in the fourth embodiment. .
그리고, 전술한 실시예에서는 도 4a에 나타낸 바와 같이, 상부기층(2)과 하부기층(1)이 접합된 상태에서 상부기층(1)의 제1개방홀(8) 주변에 접착부재(4)가 구비되지만, 상부기층과 하부기층과의 접합 공정 진행시에 상부기층 저면의 칩-캐비티 영역 내에 접착제가 도포되도록 하여, 반도체 패키지 제조시 상부기층 저면에직접 반도체 칩(3)을 부착하도록 하여 공정을 단순화함이 가능함은 물론이다.In the above-described embodiment, as shown in FIG. 4A, the adhesive member 4 is disposed around the first opening hole 8 of the upper base layer 1 while the upper base layer 2 and the lower base layer 1 are bonded to each other. Although the adhesive is applied to the chip-cavity region of the bottom of the upper base layer during the bonding process between the upper base layer and the lower base layer, the semiconductor chip 3 is attached directly to the bottom of the upper base layer during the manufacture of the semiconductor package. Of course, it is possible to simplify.
이상에서와 같이, 본 발명은 회로기판의 두께 내에 반도체 칩이 위치하도록 함과 더불어 회로기판의 반도체 칩 영역 상부에 솔더볼이 부착될 수 있도록 회로기판의 구조를 개선함에 따라, 경박단소화된 BGA(BGA ; Ball Grid Array) 타입의 반도체 패키지를 제공할 수 있으며, 웨이퍼 스케일 패키지와 마찬가지로 대면적의 기판상에서 한꺼번에 많은 수의 BGA 패키지를 제조하므로써, 패키지 제조시 생산성을 향상시킬 수 있게 된다.As described above, the present invention improves the structure of the circuit board such that the semiconductor chip is positioned within the thickness of the circuit board and the solder balls can be attached to the semiconductor chip region of the circuit board. It is possible to provide a ball grid array (BGA) type semiconductor package, and as in a wafer scale package, by manufacturing a large number of BGA packages at once on a large-area substrate, productivity in package manufacturing can be improved.
Claims (7)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-1999-0067455A KR100390453B1 (en) | 1999-12-30 | 1999-12-30 | semiconductor package with such circuit board and method for fabricating the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-1999-0067455A KR100390453B1 (en) | 1999-12-30 | 1999-12-30 | semiconductor package with such circuit board and method for fabricating the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20010059917A KR20010059917A (en) | 2001-07-06 |
| KR100390453B1 true KR100390453B1 (en) | 2003-07-04 |
Family
ID=19634564
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR10-1999-0067455A KR100390453B1 (en) | 1999-12-30 | 1999-12-30 | semiconductor package with such circuit board and method for fabricating the same |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100390453B1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100800148B1 (en) * | 2006-06-30 | 2008-02-01 | 주식회사 하이닉스반도체 | FBGA package |
| KR100871794B1 (en) * | 2007-07-19 | 2008-12-02 | 주식회사 동부하이텍 | Semiconductor device package and method for fabricating the same |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5191511A (en) * | 1991-02-08 | 1993-03-02 | Kabushiki Kaisha Toshiba | Semiconductor device including a package having a plurality of bumps arranged in a grid form as external terminals |
| US5519936A (en) * | 1994-01-28 | 1996-05-28 | International Business Machines Corporation | Method of making an electronic package with a thermally conductive support member having a thin circuitized substrate and semiconductor device bonded thereto |
| JPH1074783A (en) * | 1996-07-09 | 1998-03-17 | Internatl Business Mach Corp <Ibm> | Integrated circuit chip package and encapsulation process |
| JPH1197568A (en) * | 1997-09-22 | 1999-04-09 | Sumitomo Metal Smi Electron Devices Inc | Cavity-down type bga package |
| JPH11163038A (en) * | 1997-11-28 | 1999-06-18 | Nec Corp | Semiconductor device |
-
1999
- 1999-12-30 KR KR10-1999-0067455A patent/KR100390453B1/en active IP Right Grant
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5191511A (en) * | 1991-02-08 | 1993-03-02 | Kabushiki Kaisha Toshiba | Semiconductor device including a package having a plurality of bumps arranged in a grid form as external terminals |
| US5519936A (en) * | 1994-01-28 | 1996-05-28 | International Business Machines Corporation | Method of making an electronic package with a thermally conductive support member having a thin circuitized substrate and semiconductor device bonded thereto |
| JPH1074783A (en) * | 1996-07-09 | 1998-03-17 | Internatl Business Mach Corp <Ibm> | Integrated circuit chip package and encapsulation process |
| JPH1197568A (en) * | 1997-09-22 | 1999-04-09 | Sumitomo Metal Smi Electron Devices Inc | Cavity-down type bga package |
| JPH11163038A (en) * | 1997-11-28 | 1999-06-18 | Nec Corp | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20010059917A (en) | 2001-07-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5241133A (en) | Leadless pad array chip carrier | |
| US6060778A (en) | Ball grid array package | |
| US6781242B1 (en) | Thin ball grid array package | |
| AU647864B2 (en) | Leadless pad array chip carrier | |
| US6819565B2 (en) | Cavity-down ball grid array semiconductor package with heat spreader | |
| US20020187591A1 (en) | Packaging process for semiconductor package | |
| KR100390453B1 (en) | semiconductor package with such circuit board and method for fabricating the same | |
| JPH11297917A (en) | Semiconductor device and its manufacture | |
| KR100437821B1 (en) | semiconductor package and metod for fabricating the same | |
| KR100247641B1 (en) | Package and method of manufacturing the same | |
| KR100462373B1 (en) | Chip scale package and method for fabricating the same | |
| KR100216845B1 (en) | Structure of csp ( chip scale package ) and manufacture method | |
| KR100444175B1 (en) | ball grid array of stack chip package | |
| KR100356808B1 (en) | chip scale semiconductor package | |
| KR20020049821A (en) | chip scale semiconductor package in wafer level and method for fabricating the same | |
| KR20020065740A (en) | Thermal enhanced pbga package and method for fabricating the same | |
| KR200313831Y1 (en) | Bottom Lead Package | |
| EP1283547A1 (en) | Packaging process for semiconductor package | |
| KR20010066268A (en) | stack-type semiconductor package and method for fabricating the same | |
| KR20010001774A (en) | chip scale package and method for fabricating the same | |
| KR20020049823A (en) | semiconductor package and method for fabricating the same | |
| KR20040045696A (en) | method for fabricating semiconductor package | |
| KR20010054002A (en) | stack type semiconductor package and method for manucture of the same | |
| KR20020065729A (en) | Semicoductor package | |
| KR20020065735A (en) | Semiconductor package and method for fabricating the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| N231 | Notification of change of applicant | ||
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20130607 Year of fee payment: 11 |
|
| FPAY | Annual fee payment |
Payment date: 20140603 Year of fee payment: 12 |
|
| FPAY | Annual fee payment |
Payment date: 20150603 Year of fee payment: 13 |
|
| FPAY | Annual fee payment |
Payment date: 20160602 Year of fee payment: 14 |
|
| FPAY | Annual fee payment |
Payment date: 20170612 Year of fee payment: 15 |
|
| FPAY | Annual fee payment |
Payment date: 20180612 Year of fee payment: 16 |