KR20030002665A - Method for forming fine pattern of semiconductor device - Google Patents
Method for forming fine pattern of semiconductor device Download PDFInfo
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- KR20030002665A KR20030002665A KR1020010038349A KR20010038349A KR20030002665A KR 20030002665 A KR20030002665 A KR 20030002665A KR 1020010038349 A KR1020010038349 A KR 1020010038349A KR 20010038349 A KR20010038349 A KR 20010038349A KR 20030002665 A KR20030002665 A KR 20030002665A
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- photoresist
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- 238000000034 method Methods 0.000 title claims abstract description 57
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 105
- 238000005530 etching Methods 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 claims description 2
- 150000004767 nitrides Chemical class 0.000 claims description 2
- 239000010408 film Substances 0.000 claims 12
- 239000010409 thin film Substances 0.000 claims 2
- ISQINHMJILFLAQ-UHFFFAOYSA-N argon hydrofluoride Chemical compound F.[Ar] ISQINHMJILFLAQ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000001227 electron beam curing Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004132 cross linking Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
- H01L21/0276—Photolithographic processes using an anti-reflective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
본 발명은 반도체소자의 미세패턴 형성방법에 관한 것으로, 서로 다른 파장의 광원에서 반응하는 2중구조의 감광막을 사용하여 감광막패턴에 의한 피식각층의 패턴 변형을 방지하는 반도체소자의 미세패턴 형성방법에 관한 것이다.The present invention relates to a method of forming a micropattern of a semiconductor device, and to a method of forming a micropattern of a semiconductor device for preventing pattern deformation of an etched layer by a photosensitive film pattern by using a photosensitive film having a double structure reacting with light sources having different wavelengths. will be.
현재의 반도체소자 제조공정에서 사용되는 콘택플러그의 형성공정은 유기반사방지막을 이용하여 감광막의 패터닝을 돕고, 감광막을 식각방지막 및 탄소의 공급처로 사용하여 자기 정렬 식각공정을 거쳐 형성하고 있다. 또한, 워드라인이나 비트라인 등의 도전배선에서는 식각공정 시 감광막의 공정 마진을 확보하기 위하여 하드마스크를 사용하는 방법이 사용되고 있다.The process of forming a contact plug used in the current semiconductor device manufacturing process helps to pattern the photoresist using an organic antireflection film, and is formed through a self-aligned etching process using the photoresist as an etch stopper and a carbon source. In addition, in conductive wiring such as word lines or bit lines, a method of using a hard mask is used to secure a process margin of the photoresist layer during the etching process.
또한, 종래에는 아르곤 폴로라이드용 감광제를 사용하여 식각하면 감광제가 휘고, 산화막의 식각이 되질 않았다. 이러한 문제를 해결하기 위하여 이-빔(e-beam) 큐어링(curing) 공정을 사용하고 있으나 공정이 복잡하고 마스크 작업 시 이-빔 큐어링 시 발생하는 CD 바이어스까지 생각해야 된다.In addition, conventionally, when etching using a photosensitive agent for argon fluoride, the photosensitive agent is bent, the oxide film was not etched. In order to solve this problem, an e-beam curing process is used, but the process is complicated and the CD bias generated during the e-beam curing during masking must be considered.
이하, 첨부된 도면을 참고로 하여 종래기술에 따른 반도체소자의 미세패턴형성방법에 대하여 설명한다.Hereinafter, a method for forming a fine pattern of a semiconductor device according to the prior art will be described with reference to the accompanying drawings.
도 1a 내지 도 1c 는 종래기술에 따른 반도체소자의 미세패턴 형성방법에 의한 공정을 나타내는 사진으로서, 상기 도 1a 는 감광막패턴의 형성한 후를 나타내고, 도 1b 는 상기 감광막패턴을 식각마스크로 피식각층을 식각하는 과정 중 감광막패턴의 변형을 나타내고, 도 1c 는 식각공정을 실시하고 감광막패턴을 제거한 후 피식각층 패턴의 변형을 나타낸다.1A to 1C are photographs illustrating a process by a method of forming a micropattern of a semiconductor device according to the prior art, in which FIG. 1A shows a formation of a photoresist pattern, and FIG. 1B shows an etching layer using the photoresist pattern as an etch mask. 1C shows the deformation of the photoresist pattern during the etching process, and FIG. 1C shows the deformation of the etched layer pattern after performing the etching process and removing the photoresist pattern.
도 2a 내지 도 2e 는 종래기술에 따른 반도체소자의 미세패턴 형성방법에 의한 공정 단면도이다.2A to 2E are cross-sectional views illustrating a method of forming a fine pattern of a semiconductor device according to the prior art.
먼저, 반도체기판(21) 상부에 피식각층(22)을 형성한다. 상기 피식각층(22)은 절연막 또는 도전층일 수 있다. (도 2a 참조)First, an etching target layer 22 is formed on the semiconductor substrate 21. The etched layer 22 may be an insulating film or a conductive layer. (See Figure 2A)
다음, 상기 피식각층(22) 상부에 반사방지막(24)을 형성한다.Next, an anti-reflection film 24 is formed on the etched layer 22.
그 다음, 상기 반사방지막(24) 상부에 감광막(26)을 도포한다. (도 2b 참조)Next, a photosensitive film 26 is coated on the anti-reflection film 24. (See Figure 2b)
다음, 노광마스크를 이용하여 상기 감광막(26)을 노광시킨 후 현상하여 감광막패턴(27)을 형성한다. (도 2c 참조)Next, the photosensitive film 26 is exposed and developed using an exposure mask to form the photosensitive film pattern 27. (See Figure 2c)
그 다음, 상기 감광막패턴(27)을 식각마스크로 상기 반사방지막(24)을 식각하여 반사방지막패턴(25)을 형성한다. 이때, 과도식각공정에 의해 상기 피식각층(22)의 일부가 식각된다. (도 2d 참조)Next, the anti-reflection film 24 is etched using the photoresist pattern 27 as an etch mask to form the anti-reflection film pattern 25. At this time, a portion of the etching target layer 22 is etched by the transient etching process. (See FIG. 2D)
다음, 상기 감광막패턴(27)을 식각마스크로 상기 피식각층(22)을 식각하여 피식각층패턴(23)을 형성한다. 상기 식각공정 후 상기 감광막패턴(27)의 대부분이 제거되고, 상기 피식각층패턴(23) 상부에 반사방지막패턴(25)과 소정 두께의 감광막패턴(27)이 남게 된다. (도 2e 참조)Next, the etched layer 22 is etched using the photoresist pattern 27 as an etch mask to form the etched layer pattern 23. After the etching process, most of the photoresist pattern 27 is removed, and the anti-reflection film pattern 25 and the photoresist pattern 27 having a predetermined thickness remain on the etched layer pattern 23. (See Figure 2E)
그 후, 상기 감광막패턴(27) 및 반사방지막패턴(25)을 제거한다.Thereafter, the photoresist pattern 27 and the antireflection film pattern 25 are removed.
상기한 바와 같이 종래기술에 따른 반도체소자의 미세패턴 형성방법은, 감광막패턴을 식각마스크로 사용한 식각공정에서 감광막은 뭉침과 변형을 일으키게 된다. 이 과정에서 뭉쳐진 부분과 그렇지 않은 부분의 식각 시 저항력(resistivity) 차이가 발생하여 뭉쳐지지 않은 부위는 식각방지막의 역할을 상실하게 되어 식각 시 하부층이 식각된다. 이로 인하여 패턴은 원래 모양을 유지하지 못하고, 도 2e 의 ⓧ부분과 같이 변형된 프로파일을 갖게 된다. 상기와 같은 피식각층패턴의 변형 현상은 미세한 감광막패턴을 만들기 위해 사용되는 ArF, KrF 등의 짧은 파장을 사용하게 되면서 나타난 현상으로, 짧은 파장의 광원에 사용되는 감광막의 식각에 대한 내성이 기존의 감광막에 비해 떨어지며 하부 막질과의 접착성이 약하기 때문에 발생하고 있다.As described above, in the method of forming a fine pattern of a semiconductor device according to the prior art, the photoresist film is agglomerated and deformed in an etching process using the photoresist pattern as an etching mask. In this process, there is a difference in resistivity during the etching of the agglomerated portion and the non-aggregated portion, and the non-lumped portion loses the role of the etch barrier, and the lower layer is etched during the etching. As a result, the pattern does not maintain its original shape and has a deformed profile as shown in FIG. 2E. The above-mentioned deformation of the etched layer pattern is caused by using short wavelengths such as ArF and KrF used to make a fine photoresist pattern. The photoresist used in the light source having a short wavelength is etch resistant. This is because it is inferior to, and weak in adhesion to the underlying film.
본 발명은 상기한 바와 같은 종래기술의 문제점을 해결하기 위하여, 피식각층 상부에 서로 다른 파장의 광원에 반응하는 하부감광막과 상부감광막을 형성한 다음, 노광 및 현상공정에 의해 상기 상부감광막을 패터닝한 후 상기 상부감광막패턴을 식각마스크로 상기 하부감광막을 패터닝한 다음, 상기 하부감광막패턴을 식각마스크로 상기 피식각층을 식각하여 감광막패턴의 변형에 의한 피식각층 패턴의 변형을 방지하는 반도체소자의 미세패턴 형성방법을 제공하는데 그 목적이 있다.The present invention is to solve the problems of the prior art as described above, by forming a lower photosensitive film and an upper photosensitive film in response to light sources of different wavelengths on the etched layer, and then patterning the upper photosensitive film by an exposure and development process Afterwards, the lower photoresist layer is patterned using the upper photoresist pattern as an etch mask, and the lower photoresist pattern is etched using the lower photoresist pattern as an etch mask to prevent deformation of the etched layer pattern by deformation of the photoresist pattern. The purpose is to provide a formation method.
도 1a 내지 도 1c 는 종래기술에 따른 반도체소자의 미세패턴 형성방법에 의한 공정을 나타내는 사진.1A to 1C are photographs showing a process by a method for forming a fine pattern of a semiconductor device according to the prior art.
도 2a 내지 도 2e 는 종래기술에 따른 반도체소자의 미세패턴 형성방법에 의한 공정 단면도.2A through 2E are cross-sectional views illustrating a method of forming a fine pattern of a semiconductor device according to the prior art.
도 3a 내지 도 3f 는 본 발명의 제1실시예에 따른 반도체소자의 미세패턴 형성방법에 의한 공정 단면도.3A to 3F are cross-sectional views illustrating a method for forming a fine pattern of a semiconductor device in accordance with a first embodiment of the present invention.
도 4a 내지 도 4g 는 본 발명의 제2실시예에 따른 반도체소자의 미세패턴 형성방법에 의한 공정 단면도.4A to 4G are cross-sectional views illustrating a method for forming a micropattern of a semiconductor device in accordance with a second embodiment of the present invention.
도 5a 는 본 발명에 따른 반도체소자의 미세패턴 형성방법에 의해 형성된 감광막패턴의 사진.Figure 5a is a photograph of the photosensitive film pattern formed by the method for forming a fine pattern of a semiconductor device according to the present invention.
도 5b 는 본 발명에 따른 반도체소자의 미세패턴 형성방법에 의해 형성된 피식각층패턴의 사진.5b is a photograph of an etched layer pattern formed by a method for forming a micropattern of a semiconductor device according to the present invention;
< 도면의 주요 부분에 대한 간단한 설명 ><Brief description of the main parts of the drawing>
21, 31, 41 : 반도체기판 22, 32, 42 : 피식각층21, 31, 41: semiconductor substrates 22, 32, 42: etched layer
23, 33, 43 : 피식각층패턴 24, 46 : 반사방지막23, 33, 43: etched layer pattern 24, 46: antireflection film
25, 47 : 반사방지막패턴 26 : 감광막25, 47: antireflection film pattern 26: photosensitive film
27 : 감광막패턴 34, 44 : 하부감광막27: photosensitive film pattern 34, 44: lower photosensitive film
35, 45 : 하부감광막패턴 36, 48 : 상부감광막35, 45: lower photoresist pattern 36, 48: upper photoresist
37, 49 : 상부감광막패턴 50 : 노광마스크37, 49: upper photoresist pattern 50: exposure mask
상기 목적을 달성하기 위하여 본 발명에 따른 반도체소자의 미세패턴 형성방법은,In order to achieve the above object, the method of forming a fine pattern of a semiconductor device according to the present invention,
반도체기판 상부에 피식각층을 형성하는 공정과,Forming an etched layer on the semiconductor substrate;
상기 피식각층 상부에 서로 다른 파장의 광원에 반응하는 하부감광막과 상부감광막을 순차적으로 도포하는 공정과,Sequentially applying a lower photoresist film and an upper photoresist film reacting to light sources having different wavelengths on the etched layer;
상기 상부감광막을 노광 및 현상공정에 의해 상부감광막패턴을 형성하는 공정과,Forming an upper photoresist pattern by exposing and developing the upper photoresist;
상기 상부감광막패턴을 식각마스크로 상기 하부감광막을 식각하여 하부감광막패턴을 형성하되, 상기 식각공정 시 상기 상부감광막패턴의 대부분이 제거되도록 하는 공정과,Forming a lower photoresist pattern by etching the lower photoresist layer using the upper photoresist pattern as an etch mask, and removing most of the upper photoresist pattern during the etching process;
상기 하부감광막패턴을 식각마스크로 상기 피식각층을 식각하여 피식각층패턴을 형성하는 공정과,Etching the etched layer using the lower photoresist pattern as an etch mask to form an etched layer pattern;
상기 하부감광막패턴을 제거하는 공정을 포함하는 것을 특징으로 한다.And removing the lower photoresist pattern.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 3a 내지 도 3f 는 본 발명의 제1실시예에 따른 반도체소자의 미세패턴 형성방법에 의한 공정 단면도이다.3A to 3F are cross-sectional views illustrating a method for forming a fine pattern of a semiconductor device in accordance with a first embodiment of the present invention.
먼저, 반도체기판(31) 상부에 피식각층(32)을 형성한다. 이때, 상기 피식각층(32)은 산화막계열의 절연막이거나, 도전배선에서는 하드마스크로 사용되는 질화막계열의 절연막일 수 있다. (도 3a 참조)First, an etching target layer 32 is formed on the semiconductor substrate 31. In this case, the etched layer 32 may be an insulating film of an oxide film series or a nitride film insulating film used as a hard mask in a conductive wiring. (See Figure 3A)
다음, 상기 피식각층(32) 상부에 하부감광막(34)과 상부감광막(36)을 순차적으로 도포한다. 이때, 상기 하부감광막(34)은 ArF나 KrF와 같이 짧은 파장의 광원에 화학적인 반응을 일으키지 않는 DUV용 감광막 또는 I-라인용 감광막을 사용하고, 상기 상부감광막(36)은 ArF용 또는 KrF용 감광막을 사용한다. 여기서, 감광막이 2중 구조로 형성되어 있으므로 반사방지막은 형성하지 않아도 좋다.Next, the lower photoresist film 34 and the upper photoresist film 36 are sequentially applied to the etched layer 32. In this case, the lower photosensitive film 34 uses a photosensitive film for DUV or an I-line photosensitive film that does not cause a chemical reaction to a light source having a short wavelength such as ArF or KrF, and the upper photosensitive film 36 is used for ArF or KrF. Use a photoresist film. Here, since the photosensitive film is formed in a double structure, it is not necessary to form the antireflection film.
상기 하부감광막(34)을 I-라인용 감광막을 사용하고, 상부감광막을 ArF 감광막을 사용하는 경우 서로 혼합되는 것을 방지하기 위하여 상기 하부감광막(34) 형성 후 열처리공정을 실시하여 가교시킨다. (도 3b 참조)When the lower photoresist film 34 is used for the I-line photoresist film and the upper photoresist film is used for the ArF photoresist film, crosslinking is performed by forming the lower photoresist film 34 and then performing a heat treatment process. (See Figure 3b)
그 다음, 노광 및 현상공정을 실시하여 상부감광막패턴(37)을 형성한다. 이때, 상기 상부감광막(36)과 하부감광막(34)은 서로 반응하는 광원의 파장이 다르기 때문에 상기 상부감광막(36)의 노광공정 시 상기 하부감광막(34)은 그대로 남아 있게 된다. (도 3c 참조)Then, the exposure and development processes are performed to form the upper photoresist pattern 37. In this case, since the wavelengths of the light sources reacting with each other are different between the upper photoresist layer 36 and the lower photoresist layer 34, the lower photoresist layer 34 remains intact during the exposure process of the upper photoresist layer 36. (See Figure 3c)
다음, 상기 상부감광막패턴(37)을 식각마스크로 상기 하부감광막(34)을 건식식각하여 하부감광막패턴(35)을 형성한다. 이때, 상기 건식식각공정 중 상기 상부감광막패턴(37)의 대부분이 제거된다. (도 3d 참조)Next, the lower photoresist pattern 35 is dry-etched using the upper photoresist pattern 37 as an etch mask to form a lower photoresist pattern 35. At this time, most of the upper photoresist pattern 37 is removed during the dry etching process. (See FIG. 3D)
그 다음, 상기 하부감광막패턴(35)을 식각마스크로 상기 피식각층(32)을 건식식각하여 피식각층패턴(33)을 형성한다. 상기 감광막패턴의 변형은 상부감광막패턴937)에서만 발생하고, 식각내성이 강한 하부감광막패턴(35)이 식각마스크 역할을 하여 피식각층패턴(33)의 변형은 발생하지 않는다. (도 3e 및 도 3f 참조)Thereafter, the etched layer 32 is dry-etched using the lower photoresist pattern 35 as an etch mask to form an etched layer pattern 33. Deformation of the photoresist pattern occurs only in the upper photoresist pattern 937, and the lower photoresist pattern 35, which has strong etch resistance, serves as an etching mask, and thus the deformation of the etched layer pattern 33 does not occur. (See Figures 3E and 3F)
도 4a 내지 도 4g 는 본 발명의 제2실시예에 따른 반도체소자의 미세패턴 형성방법에 의한 공정 단면도이다.4A to 4G are cross-sectional views illustrating a method for forming a fine pattern of a semiconductor device in accordance with a second embodiment of the present invention.
먼저, 반도체기판(41) 상부에 피식각층(42)을 형성한다. (도 4a 참조)First, an etching target layer 42 is formed on the semiconductor substrate 41. (See Figure 4A)
다음, 상기 피식각층(42) 상부에 하부감광막(44)을 도포한다. 이때, 상기 하부감광막(44)은 I-라인용 감광막으로 네가티브형(negative type)이 사용된다. 상기 I-라인용 감광막은 고온으로 가열하면 경화되어 그 상부에 감광막을 도포할 수 있게 된다. 한편, 상기 I-라인용 감광막 이외에 KrF 감광막을 사용할 수도 있다. (도 4b 참조)Next, a lower photosensitive film 44 is coated on the etched layer 42. At this time, the lower photosensitive film 44 is a negative type (negative type) is used as the I-line photosensitive film. The I-line photoresist film is cured when heated to a high temperature, so that the photoresist film can be applied thereon. Meanwhile, in addition to the I-line photosensitive film, a KrF photosensitive film may be used. (See Figure 4b)
그 다음, 상기 하부감광막(44) 상부에 반사방지막(46)을 형성한다. 이때, 상기 I-라인용 감광막은 아르곤 폴로라이드 광을 흡수하기 때문에 상기 반사방지막(46)은 형성하지 않아도 좋다.Next, an anti-reflection film 46 is formed on the lower photoresist 44. In this case, the anti-reflection film 46 may not be formed because the I-line photoresist absorbs argon fluoride light.
다음, 상기 반사방지막(46) 상부에 상부감광막(48)을 도포한다. 상기 상부감광막(48)은 폴로라이드 감광막 또는 KrF용 또는 VUV용 감광막이 사용된다. (도 4c 참조)Next, an upper photoresist film 48 is coated on the anti-reflection film 46. The upper photoresist film 48 is a fluoride photoresist film or a photoresist film for KrF or VUV. (See Figure 4c)
그 다음, 노광마스크(50)를 이용한 노광공정 및 현상공정으로 상부감광막패턴(49)을 형성한다. 상기 노광공정은 ArF, KrF, F2또는 EUV가 광원으로 사용될 수 있다. (도 4d 참조)Next, the upper photosensitive film pattern 49 is formed by an exposure process and a development process using the exposure mask 50. In the exposure process, ArF, KrF, F 2 or EUV may be used as the light source. (See FIG. 4D)
다음, 상기 상부감광막패턴(49)을 식각마스크로 상기 반사방지막(46) 및 하부감광막(44)을 식각하여 반사방지막패턴(47) 및 하부감광막패턴(45)을 형성한다. 이때, 상기 식각공정 시 상기 상부감광막패턴(49)의 대부분이 제거된다. (도 4e 참조)Next, the anti-reflection film 46 and the lower photoresist layer 44 are etched using the upper photoresist pattern 49 as an etch mask to form the anti-reflection pattern 47 and the lower photoresist pattern 45. At this time, most of the upper photoresist pattern 49 is removed during the etching process. (See Figure 4E)
그 다음, 상기 하부감광막패턴(45)을 식각마스크로 사용하여 상기 피식각층(42)을 식각하여 피식각층패턴(43)을 형성한다. 이때, 상기 반사방지막패턴(47)은 상술한 바와 같이 형성하지 않을 수도 있기 때문에 예외로 둔다. (도 4f 참조)Next, the etching target layer 42 is etched using the lower photoresist pattern 45 as an etching mask to form the etching target layer pattern 43. At this time, the anti-reflection film pattern 47 is an exception because it may not be formed as described above. (See Figure 4f)
다음, 상기 하부감광막패턴(45)을 제거한다. (도 4g 참조)Next, the lower photoresist pattern 45 is removed. (See Figure 4g)
도 5a 는 본 발명에 따른 반도체소자의 미세패턴 형성방법에 의해 형성된 감광막패턴의 사진이고, 도 5b 는 본 발명에 따른 반도체소자의 미세패턴 형성방법에 의해 형성된 피식각층패턴의 사진으로서, 패턴의 변형을 발견할 수 없다.5A is a photograph of a photoresist pattern formed by a method of forming a micropattern of a semiconductor device according to the present invention, and FIG. 5B is a photograph of an etched layer pattern formed by a method of forming a micropattern of a semiconductor device according to the present invention. Can not be found.
이상에서 살펴본 바와 같이, 본 발명에 따른 반도체소자의 미세패턴 형성방법은, 피식각층 상부에 서로 다른 파장을 갖는 광원에 반응하는 하부감광막과 상부감광막을 형성하고, 상기 상부감광막을 노광 및 현상하여 상부감광막패턴을 형성한 다음, 상기 상부감광막패턴을 식각마스크로 상기 하부감광막을 식각하여 하부감광막패턴을 형성한 후 상기 하부감광막패턴을 식각마스크로 상기 피식각층을 식각하여 감광막패턴의 변형에 의한 피식각층의 패턴 변형을 방지함으로써 소자의 공정 수율 및 신뢰성을 향상시킬 수 있는 이점이 있다.As described above, in the method of forming a micropattern of a semiconductor device according to the present invention, a lower photoresist film and an upper photoresist film are formed on an etched layer and reacted with light sources having different wavelengths, and the upper photoresist film is exposed and developed. After the photoresist pattern is formed, the lower photoresist pattern is etched using the upper photoresist pattern as an etch mask to form a lower photoresist pattern, and the etched layer is then etched by the lower photoresist pattern using an etch mask. There is an advantage that can improve the process yield and reliability of the device by preventing the pattern deformation.
Claims (6)
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| KR101044820B1 (en) * | 2009-07-31 | 2011-06-30 | 주식회사 포스코 | Apparatus for cushioning tension of belt conveyor |
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