KR20030001063A - Method for forming metal-gate in semiconductor device - Google Patents
Method for forming metal-gate in semiconductor device Download PDFInfo
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- KR20030001063A KR20030001063A KR1020010037393A KR20010037393A KR20030001063A KR 20030001063 A KR20030001063 A KR 20030001063A KR 1020010037393 A KR1020010037393 A KR 1020010037393A KR 20010037393 A KR20010037393 A KR 20010037393A KR 20030001063 A KR20030001063 A KR 20030001063A
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- 238000000034 method Methods 0.000 title claims abstract description 44
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 229910052751 metal Inorganic materials 0.000 claims abstract description 29
- 239000002184 metal Substances 0.000 claims abstract description 29
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 29
- 229920005591 polysilicon Polymers 0.000 claims abstract description 29
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 26
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 26
- 230000004888 barrier function Effects 0.000 claims abstract description 22
- 238000009792 diffusion process Methods 0.000 claims abstract description 22
- 239000011229 interlayer Substances 0.000 claims abstract description 21
- 239000010410 layer Substances 0.000 claims abstract description 12
- 239000000126 substance Substances 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000005498 polishing Methods 0.000 claims abstract description 7
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 13
- 238000000151 deposition Methods 0.000 claims description 12
- 230000008021 deposition Effects 0.000 claims description 7
- 238000010438 heat treatment Methods 0.000 claims description 5
- 239000002243 precursor Substances 0.000 claims description 5
- 238000009832 plasma treatment Methods 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 229910052721 tungsten Inorganic materials 0.000 description 14
- 239000010937 tungsten Substances 0.000 description 14
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 13
- 238000005530 etching Methods 0.000 description 9
- 239000000463 material Substances 0.000 description 5
- 125000006850 spacer group Chemical group 0.000 description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 description 2
- 229910021341 titanium silicide Inorganic materials 0.000 description 2
- 235000017166 Bambusa arundinacea Nutrition 0.000 description 1
- 235000017491 Bambusa tulda Nutrition 0.000 description 1
- 241001330002 Bambuseae Species 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 235000015334 Phyllostachys viridis Nutrition 0.000 description 1
- 229910004200 TaSiN Inorganic materials 0.000 description 1
- 229910008482 TiSiN Inorganic materials 0.000 description 1
- 239000011425 bamboo Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- TUTOKIOKAWTABR-UHFFFAOYSA-N dimethylalumane Chemical compound C[AlH]C TUTOKIOKAWTABR-UHFFFAOYSA-N 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- -1 tungsten nitride Chemical class 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823456—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
본 발명은 반도체소자의 제조 방법에 관한 것으로, 특히 금속 게이트의 형성 방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a metal gate.
최근에, 반도체소자의 게이트 선폭이 0.1㎛까지 감소함에 따라 높은 면저항(Sheet resistance)을 가지는 폴리실리콘, 텅스텐실리사이드, 티타늄실리사이드에 의해서는 소자에서 요구하는 저항을 만족시키지 못하기 때문에 RC 지연시간이 증가하게 된다.Recently, as the gate line width of a semiconductor device decreases to 0.1 µm, the RC delay time increases because polysilicon, tungsten silicide, and titanium silicide having high sheet resistance do not satisfy the resistance required by the device. Done.
따라서, 이와 같은 면저항 문제점을 개선시키기 위하여 텅스텐/폴리실리콘의 적층막으로 이루어진 금속게이트(metal gate)를 적용하고 있는 추세이다.Accordingly, in order to improve the sheet resistance problem, a metal gate made of a tungsten / polysilicon laminated film is being applied.
일반적으로 텅스텐(W)은 벌크저항(Bulk resistance)이 6μΩㆍcm으로 텅스텐실리사이드(WSi)의 80μΩㆍcm과 티타늄실리사이드(TSi2)의 18μΩㆍcm에 비해 아주 낮은 저항을 가지므로 고집적 소자의 게이트 물질로 적합하다.In general, tungsten (W) has a bulk resistance of 6 μΩ · cm, which is much lower than 80 μΩ · cm of tungsten silicide (WSi) and 18 μΩ · cm of titanium silicide (TSi 2 ), so that the gate of the highly integrated device It is suitable as a material.
그러나, 텅스텐/폴리실리콘(W/Polysilicon) 게이트 구조에서는 후속 500℃이상의 열공정에 의해서 텅스텐과 폴리실리콘의 반응에 의한 텅스텐실리사이드(WSi)가 형성되므로써, 텅스텐 게이트의 낮은 저항을 유지할 수 없는 문제점이 있다.However, in the tungsten / polysilicon gate structure, since tungsten silicide (WSi) is formed by the reaction of tungsten and polysilicon by a subsequent thermal process of 500 ° C. or higher, there is a problem that the low resistance of the tungsten gate cannot be maintained. have.
따라서, 텅스텐과 폴리실리콘 사이에 확산배리어막으로 텅스텐나이트라이드막을 증착하여 텅스텐과 폴리실리콘의 반응으로 인한 저항 증가를 방지한다.Thus, a tungsten nitride film is deposited as a diffusion barrier film between tungsten and polysilicon to prevent an increase in resistance due to the reaction of tungsten and polysilicon.
그러나, 식각 공정, 특히, 반응성이온식각(Reactive Ion Etching; RIE)에 의한 게이트 형성은, 금속/확산방지막/폴리실리콘/게이트절연막의 순차적 패터닝의 어려움, 프로파일 확보의 어려움, 식각시 게이트절연막의 특성 열화 및 식각 손상을 회복시켜주기 위한 열부담(thermal budget) 등의 여러 문제점이 발생된다.However, etching process, in particular, gate formation by Reactive Ion Etching (RIE), has difficulty in sequential patterning of metal / diffusion barrier film / polysilicon / gate insulation film, difficulty in securing profile, characteristics of gate insulation film during etching. Several problems arise, such as thermal budgets for recovering deterioration and etching damage.
이를 해결하기 위해 다마신 구조(damascene structure)에서의 금속게이트 공정이 연구되고 있다.In order to solve this problem, a metal gate process in a damascene structure has been studied.
다마신 공정이라 함은 절연막(Dielectric layer)을 사진 및 식각으로 식각하여 트렌치(Trench)를 형성하고, 이 트렌치에 텅스텐(W), 알루미늄(Al), 구리(Cu) 등의 도전 물질을 채워 넣고 필요한 배선 이외의 도전 물질은 에치백(Etchback)이나 화학적기계적연마(Chemical Mechanical Polishing; CMP) 등의 기술을 이용하여 제거하므로써 처음에 형성한 트렌치 모양으로 배선을 형성하는 기술이다.In the damascene process, a dielectric layer is etched by photo and etching to form a trench, and the trench is filled with a conductive material such as tungsten (W), aluminum (Al), and copper (Cu). The conductive material other than the necessary wiring is a technique for forming the wiring in the trench shape first formed by removing it using a technique such as etching back or chemical mechanical polishing (CMP).
상기한 다마신 공정은, 특히 듀얼 다마신 공정은 주로 DRAM 등의 비트 라인(bit line) 또는 워드라인(Wordline), 금속배선 형성에 이용되며, 특히 다층 금속배선에서 상층 금속배선과 하층 금속배선을 접속시키기 위한 비아홀을 동시에 형성할 수 있을뿐만 아니라, 금속배선에 의해 발생하는 단차를 제거할 수 있으므로 후속 공정을 용이하게 하는 장점이 있다.In the damascene process, in particular, the dual damascene process is mainly used for forming bit lines, word lines, and metal wirings such as DRAM, and in particular, the upper metal wiring and the lower metal wiring in the multilayer metal wiring. Not only can the via holes for connection be formed at the same time, but also the step caused by the metal wiring can be eliminated, thereby facilitating subsequent processes.
상기한 다마신공정을 이용한 종래 금속게이트의 형성 방법을 첨부도면 도 1a 내지 도 1d를 참조하여 설명하면 다음과 같다.A method of forming a conventional metal gate using the damascene process described above will be described with reference to FIGS. 1A to 1D.
도 1a에 도시된 바와 같이, 반도체기판(11)상에 더미 게이트산화막(12), 더미 폴리실리콘(13)으로 이루어진 더미게이트(dummy gate)를 형성한 후, 더미게이트의 양측벽에 접하는 스페이서(14)를 형성한다.As shown in FIG. 1A, after a dummy gate including a dummy gate oxide film 12 and a dummy polysilicon 13 is formed on a semiconductor substrate 11, spacers contacting both sidewalls of the dummy gate ( 14).
그리고, 스페이서(14) 및 더미 폴리실리콘(13)을 포함한 전면에 층간절연막(Inter Layer Dielectric; ILD)(15)을 증착한 후, 더미 폴리실리콘(13)의 표면이 노출될때까지 층간절연막(15)을 화학적기계적연마한다.Then, an interlayer dielectric (ILD) 15 is deposited on the entire surface including the spacer 14 and the dummy polysilicon 13, and then the interlayer dielectric layer 15 is exposed until the surface of the dummy polysilicon 13 is exposed. Chemical mechanical polishing).
도 1b에 도시된 바와 같이, 노출된 더미 폴리실리콘(13) 및 더미 게이트산화막(12)을 딥아웃(dip-out)으로 제거하여 다마신 패턴(16)을 형성한다.As shown in FIG. 1B, the exposed dummy polysilicon 13 and the dummy gate oxide layer 12 are removed by dip-out to form a damascene pattern 16.
도 1c에 도시된 바와 같이, 다마신 패턴(16)의 전면에 게이트산화막(17), 확산방지막(18) 및 금속막(19)을 차례로 증착한다. 여기서, 금속막(19)은 텅스텐을 이용한다.As illustrated in FIG. 1C, the gate oxide layer 17, the diffusion barrier layer 18, and the metal layer 19 are sequentially deposited on the entire surface of the damascene pattern 16. Here, tungsten is used for the metal film 19.
도 1d에 도시된 바와 같이, 층간절연막(15)의 표면이 노출될때까지 금속막(19)을 화학적기계적연마하여 다마신 패턴(16) 내에 매립되는 금속게이트를 형성한다.As shown in FIG. 1D, the metal film 19 is chemically mechanically polished until the surface of the interlayer insulating film 15 is exposed to form a metal gate embedded in the damascene pattern 16.
그러나, 상술한 종래기술에서는 더미게이트산화막 형성, 금속게이트 형성을 위한 화학적기계적연마 등 금속게이트를 형성하기 위한 공정이 매우 복잡하고, 금속게이트 물질로 텅스텐을 이용하므로 게이트의 전기적 비저항이 높은 문제점이 있다.However, in the above-described prior art, a process for forming a metal gate, such as a dummy gate oxide film formation and chemical mechanical polishing for forming a metal gate, is very complicated, and since tungsten is used as the metal gate material, there is a problem in that the electrical resistivity of the gate is high. .
본 발명은 상기한 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 공정을 단순화시키고 게이트의 전기적 특성을 향상시키도록 한 금속게이트의 형성 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems of the prior art, and an object thereof is to provide a method of forming a metal gate to simplify the process and improve the electrical characteristics of the gate.
도 1a 내지 도 1d는 종래기술에 따른 텅스텐 게이트의 형성 방법을 도시한 공정 단면도,1A to 1D are cross-sectional views illustrating a method of forming a tungsten gate according to the prior art;
도 2a 내지 도 2d는 본 발명의 실시예에 따른 알루미늄 게이트의 형성 방법을 도시한 공정 단면도.2A to 2D are cross-sectional views illustrating a method of forming an aluminum gate according to an embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
21 : 반도체기판 22 : 게이트산화막21 semiconductor substrate 22 gate oxide film
23 : 확산방지막 24 : 더미 폴리실리콘23 diffusion barrier 24 dummy polysilicon
25 : 스페이서 26 : 제 1 층간절연막25 spacer 26 first interlayer insulating film
27 : 다마신 패턴 28 : 알루미늄막27: damascene pattern 28: aluminum film
29 : 산화알루미늄막 30 : 제 2 층간절연막29 aluminum oxide film 30 second interlayer insulating film
상기의 목적을 달성하기 위한 본 발명의 금속게이트의 형성 방법은 반도체기판상에 게이트산화막, 확산방지막, 더미 폴리실리콘이 순차적으로 적층된 더미 게이트패턴을 형성하는 단계, 상기 더미 게이트패턴을 포함한 전면에 층간절연막을 형성하는 단계, 상기 더미 폴리실리콘의 표면이 드러날때까지 상기 층간절연막을 화학적기계적연마하는 단계, 상기 드러난 더미 폴리실리콘을 선택적으로 제거하여 상기 확산방지막의 표면을 노출시키는 다마신 구조를 형성하는 단계, 상기 노출된 확산방지막상에만 선택적으로 알루미늄막을 증착하는 단계, 및 상기 알루미늄막상에 산화알루미늄막을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.The method of forming a metal gate of the present invention for achieving the above object comprises the steps of forming a dummy gate pattern in which a gate oxide film, a diffusion barrier film, and a dummy polysilicon are sequentially stacked on a semiconductor substrate, the front surface including the dummy gate pattern Forming an interlayer insulating film, chemically mechanically polishing the interlayer insulating film until the surface of the dummy polysilicon is exposed, and selectively removing the exposed dummy polysilicon to form a damascene structure exposing the surface of the diffusion barrier layer And depositing an aluminum film selectively only on the exposed diffusion barrier film, and forming an aluminum oxide film on the aluminum film.
바람직하게, 상기 알루미늄막을 증착하는 단계는, 선택적 화학기상증착법으로 이루어지되, DMAH 또는 DMEAA 중에서 선택된 어느 하나의 전구체를 이용함을 특징으로 하고, 상기 더미 폴리실리콘을 제거하는 단계는, 상기 확산방지막에 대한 큰 선택비를 갖는 식각제를 이용한 습식 또는 건식 딥아웃으로 이루어짐을 특징으로 한다.Preferably, the step of depositing the aluminum film is made by selective chemical vapor deposition, characterized in that using any one of the precursor selected from DMAH or DMEAA, the step of removing the dummy polysilicon, for the diffusion barrier It is characterized by consisting of a wet or dry deep-out using an etchant having a large selectivity.
그리고, 상기 산화알루미늄막을 형성하는 단계는, 열처리 또는 플라즈마처리 중 어느 하나를 실시하여 이루어짐을 특징으로 한다.In addition, the forming of the aluminum oxide film may be performed by performing any one of heat treatment and plasma treatment.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 2a 내지 도 2c는 본 발명의 실시예에 따른 금속게이트의 형성 방법을 도시한 공정 단면도로서, 알루미늄게이트의 형성 방법을 도시하고 있다.2A to 2C are cross-sectional views illustrating a method of forming a metal gate according to an exemplary embodiment of the present invention, and illustrate a method of forming an aluminum gate.
도 2a에 도시된 바와 같이, 반도체기판(21)상에 게이트산화막(22), 확산방지막(23), 더미 폴리실리콘(24)의 순서로 적층된 후 패터닝된 더미게이트를 형성한 후, 더미게이트의 양측벽에 접하는 스페이서(25)를 형성한다.As shown in FIG. 2A, after the gate oxide layer 22, the diffusion barrier 23, and the dummy polysilicon 24 are stacked in the order of forming the patterned dummy gate on the semiconductor substrate 21, a dummy gate is formed. Spacers 25 are formed in contact with both side walls of the substrate.
여기서, 확산방지막(23)은 TiN, Ti/TiN, Ta, TaN, Ta/TaN, WN, TiSiN, TaSiN등의 이원계 또는 삼원계 확산방지막을 이용한다.Here, the diffusion barrier 23 uses a binary or ternary diffusion barrier such as TiN, Ti / TiN, Ta, TaN, Ta / TaN, WN, TiSiN, TaSiN.
계속해서, 스페이서(25) 및 더미 폴리실리콘(24)을 포함한 전면에 제 1 층간절연막(26)을 증착한 후, 더미 폴리실리콘(24)의 표면이 노출될때까지 제 1 층간절연막(26)을 화학적기계적연마한다.Subsequently, after depositing the first interlayer insulating film 26 on the entire surface including the spacers 25 and the dummy polysilicon 24, the first interlayer insulating film 26 is deposited until the surface of the dummy polysilicon 24 is exposed. Chemical mechanical polishing
도 2b에 도시된 바와 같이, 노출된 더미 폴리실리콘(24)을 습식 케미컬이나 건식 케미컬을 사용하는 딥아웃 공정으로 제거하되, 더미 폴리실리콘(24)이 확산방지막(23)에 대해 큰 선택비를 갖는 식각제를 사용하여 폴리실리콘만 선택적으로 제거하여 확산방지막(23)의 표면을 노출시키므로써 다마신 패턴(27)을 형성한다.As shown in FIG. 2B, the exposed dummy polysilicon 24 is removed by a dip-out process using wet chemical or dry chemical, but the dummy polysilicon 24 has a large selectivity with respect to the diffusion barrier 23. Only the polysilicon is selectively removed using an etchant having the same, thereby exposing the surface of the diffusion barrier 23 to form a damascene pattern 27.
도 2c에 도시된 바와 같이, 다마신 페탄(27) 내의 확산방지막(23)상에 알루미늄막(28)을 증착하되, 다마신 패턴(27)내에 완전 증착후 과증착되지 않도록 다마신 패턴(27)의 깊이에 맞게 증착 두께 및 증착 시간을 조절한다.As shown in FIG. 2C, the aluminum film 28 is deposited on the diffusion barrier 23 in the damascene petane 27, but the damascene pattern 27 is not deposited after the complete deposition in the damascene pattern 27. Adjust the deposition thickness and deposition time to the depth of).
여기서, 알루미늄막(28)은 선택적 화학기상증착법(selective-CVD)으로 증착하되, 전구체(precursor)로 DMAH(Di-Methyl-Aluminum-Hydride) 또는 DMEAA(Di-Methyl-Ethyl-Amine-Alan) 중에서 선택된 어느 하나의 전구체를 이용한다.Here, the aluminum film 28 is deposited by selective chemical vapor deposition (selective-CVD), but as a precursor (precursor) in Di-Methyl-Aluminum-Hydride (DMAH) or Di-Methyl-Ethyl-Amine-Alan (DMEAA) Use either precursor selected.
도 2d에 도시된 바와 같이, 다마신 패턴(27) 내에 알루미늄막(28)을 완전히 채운 후, 200℃∼450℃의 온도에서 열공정을 실시하여 다마신 패턴을 뱀부(bamboo)구조를 갖도록 하여 알루미늄막(28)의 배향성을 향상시킨다.As shown in FIG. 2D, after the aluminum film 28 is completely filled in the damascene pattern 27, a thermal process is performed at a temperature of 200 ° C. to 450 ° C. so that the damascene pattern has a bamboo structure. The orientation of the aluminum film 28 is improved.
이러한 열공정은 노(Furnace)나 급속열처리(RTP) 등으로 진행하며, 또한 산소(O2)가 함유된 분위기에서 실시하여 알루미늄막(28) 표면에 치밀한 산화알루미늄막(AlOx)(29)을 형성시킨다. 이 때, 산화알루미늄막(29)을 형성시키므로써 이후 콘택식각시, 특히 자기정렬콘택식각시 제 1 층간절연막(26)과 충분한 선택비를 갖도록 한다.This thermal process is carried out in a furnace or rapid heat treatment (RTP), and is carried out in an atmosphere containing oxygen (O 2 ) to form a dense aluminum oxide film (AlO x ) 29 on the surface of the aluminum film 28. To form. At this time, the aluminum oxide film 29 is formed to have a sufficient selectivity with the first interlayer insulating film 26 during subsequent contact etching, particularly during self-aligned contact etching.
산화알루미늄막(29)을 형성하는 다른 방법은, 다마신 패턴(27) 내에 알루미늄막(28)을 완전히 채운 후, 산소(O2) 또는 N2O 분위기에서 플라즈마로 알루미늄막(28) 표면을 산화시킨다.Another method of forming the aluminum oxide film 29 is to completely fill the aluminum film 28 in the damascene pattern 27, and then to surface the aluminum film 28 with plasma in oxygen (O 2 ) or N 2 O atmosphere. Oxidize.
여기서, 플라즈마를 발생시키기 위한 파워, 가스 비율 등의 공정 조건을 조절하므로써 알루미늄막(28) 표면에 형성한 산화알루미늄막(29)의 두께를 변화시킨다. 결국, 산화알루미늄막(29)의 두께를 50Å∼200Å 정도로 형성하여 이후 콘택식각시 제 1 층간절연막(26)과 충분한 선택비를 갖도록 한다.Here, the thickness of the aluminum oxide film 29 formed on the surface of the aluminum film 28 is changed by adjusting process conditions such as power for generating plasma and gas ratio. As a result, the thickness of the aluminum oxide film 29 is formed to be about 50 to 200 Å so as to have a sufficient selectivity with the first interlayer insulating film 26 for subsequent contact etching.
상기한 플라즈마를 이용하여 알루미늄막(28)의 표면을 산화시킬 때, 독립된 플라즈마 장치에서 진행하거나, 또는 후속 층간절연막 증착시 플라즈마인핸스드 산화막(PE-Oxide) 증착 장치내에서 산화알루미늄막(29)과 제 2 층간절연막(30)을 연속적으로 증착할 수 있다.When the surface of the aluminum film 28 is oxidized using the plasma, the aluminum oxide film 29 is carried out in an independent plasma apparatus, or in a plasma enhanced oxide (PE-Oxide) deposition apparatus during subsequent interlayer dielectric film deposition. And the second interlayer insulating film 30 can be deposited successively.
계속해서, 알루미늄막(28)이 완전히 매립된 다마신 구조를 포함한 전면에 제 2 층간절연막(30)을 증착한다.Subsequently, a second interlayer insulating film 30 is deposited on the entire surface including the damascene structure in which the aluminum film 28 is completely embedded.
후속 공정으로 도면에 도시되지 않았지만, 제 2 층간절연막(30) 및 제 1 층간절연막(26)을 선택적으로 식각하여 반도체기판(21)의 표면이 노출되는 배선용 콘택홀을 형성한다. 이 때, 알루미늄막(28)의 표면에 산화알루미늄막(29)이 형성되어 있으므로, 콘택식각시 충분한 선택비를 가져 공정마진을 확보할 수 있다.Although not shown in the drawing in a subsequent process, the second interlayer insulating film 30 and the first interlayer insulating film 26 are selectively etched to form a contact hole for wiring in which the surface of the semiconductor substrate 21 is exposed. At this time, since the aluminum oxide film 29 is formed on the surface of the aluminum film 28, it is possible to secure a process margin with a sufficient selection ratio during contact etching.
상술한 본 발명에서는 게이트물질로 텅스텐에 비해 비저항이 1/3 정도인 알루미늄막을 이용하므로써 비교적 낮은 두께에서도 충분한 게이트의 전류공급 특성을 확보할 수 있다. 또한, 알루미늄막의 게이트물질로의 적용은, 최근 후속 층간절연막이나 금속배선 공정이 대부분 450℃ 이하에서 이루어지므로 열공정에 의한 열화없이 진행 가능하다.In the present invention described above, by using an aluminum film having a specific resistance of about 1/3 of tungsten as the gate material, sufficient current supply characteristics of the gate can be ensured even at a relatively low thickness. In addition, the application of the aluminum film to the gate material can be performed without deterioration due to the thermal process since most of the subsequent interlayer insulating films and metal wiring processes are performed at 450 ° C or lower.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같은 본 발명은 다마신 구조 형성후, 게이트산화막과 확산방지막을 추가로 증착할 필요가 없고, 또는 알루미늄증착후 화학적기계적연마 공정을 생략할 수 있으므로 공정 단순화에 따른 제조 단가를 낮출 수 있는 효과가 있다.As described above, the present invention does not need to further deposit a gate oxide film and a diffusion barrier after the damascene structure is formed, or the chemical mechanical polishing process can be omitted after aluminum deposition, thereby reducing the manufacturing cost according to the process simplification. It works.
또한, 텅스텐에 비해 비저항이 낮은 알루미늄막을 게이트물질로 이용하므로써 금속게이트의 전기적 특성을 향상시킬 수 있는 효과가 있다.In addition, by using an aluminum film having a lower specific resistance than tungsten as a gate material, there is an effect that can improve the electrical characteristics of the metal gate.
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