KR20020096748A - Method of forming a metal wiring in a semiconductor device - Google Patents
Method of forming a metal wiring in a semiconductor device Download PDFInfo
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- KR20020096748A KR20020096748A KR1020010035572A KR20010035572A KR20020096748A KR 20020096748 A KR20020096748 A KR 20020096748A KR 1020010035572 A KR1020010035572 A KR 1020010035572A KR 20010035572 A KR20010035572 A KR 20010035572A KR 20020096748 A KR20020096748 A KR 20020096748A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Abstract
Description
본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 특히 금속 배선 증착 후 화학적 기계적 연마를 실시하는 과정에서 디싱이나, 침식 또는 스크래치 현상이 발생되는 것을 방지할 수 있는 반도체 소자의 커패시터 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings of a semiconductor device, and more particularly, to a method of manufacturing a capacitor of a semiconductor device capable of preventing dishing, erosion or scratching in the process of performing chemical mechanical polishing after deposition of metal wires. will be.
반도체 소자가 고집적화되어 감에 따라, 소정의 공정을 진행한 후 반도체 기판 표면을 평탄화하는 것은 매우 중요하다. 현재까지는 반도체 기판의 평탄화 기술로 화학적 기계적 연마(Chemical Mechanical Polishing; CMP)가 개발된 기술 중 가장 효과적인 평탄화 방법이다. CMP는 반도체 기판의 표면에 연마액인 슬러리와 기계적 압력을 가하면서 반도체 기판과 패드를 마찰시켜 반도체 기판의 표면에 형성된 수 천Å의 단차를 제거하거나 금속 배선을 형성하는 기술이다.As semiconductor devices become highly integrated, it is very important to planarize the semiconductor substrate surface after a predetermined process. Until now, chemical mechanical polishing (CMP) has been the most effective planarization method for the semiconductor substrate planarization technology. CMP is a technique of removing the thousands of steps formed on the surface of a semiconductor substrate or forming metal wiring by rubbing the semiconductor substrate and the pad while applying a slurry, which is a polishing liquid, to the surface of the semiconductor substrate.
도 1a 내지 도 1c는 종래 기술에 따른 CMP 공정을 통한 금속 배선 형성 방법을 설명하기 위한 소자의 단면도이다.1A to 1C are cross-sectional views of devices for describing a metal wiring forming method through a CMP process according to the prior art.
도 1a를 참조하면, 소정의 공정을 통해 반도체 소자를 형성하기 위한 여러 요소가 형성된 반도체 기판(11) 상에 제 1 절연막(12), 식각 정지층(13), 제 2 절연(14)을 순차적으로 형성한 후 듀얼 다마신(Dual damascene) 공정으로 제 2 절연막(14)에는 트랜치(14a)를 형성하고, 제 1 절연막(12)에는 콘택홀(12a)을 형성한다. 이후, 금속 이온의 확산 방지와 접착 특성(Adhesion)을 향상시키기 위하여 트랜치(14a)와 콘택홀(12a)로 이루어진 듀얼 다마신 패턴을 포함한 전체 상부에 확산 장벽층(15)을 형성한 후 순차적으로 전체 상부에 금속 시드층(16)을 형성한다.Referring to FIG. 1A, a first insulating film 12, an etch stop layer 13, and a second insulating 14 are sequentially formed on a semiconductor substrate 11 on which various elements for forming a semiconductor device are formed through a predetermined process. After forming, the trench 14a is formed in the second insulating film 14 and the contact hole 12a is formed in the first insulating film 12 by a dual damascene process. Subsequently, in order to prevent diffusion of metal ions and to improve adhesion properties, the diffusion barrier layer 15 is formed on the whole including the dual damascene pattern formed of the trench 14a and the contact hole 12a. The metal seed layer 16 is formed on the whole.
금속 시드층(16)은 전기 도금법을 적용하기 위하여 형성하며, CVD법으로 증착한다.The metal seed layer 16 is formed to apply the electroplating method and is deposited by CVD method.
도 1b를 참조하면, 금속 전기 도금을 통해 듀얼 다마신 패턴(12a 및 14a)을 포함한 금속 시드층(16) 상에 금속 도금층(17)을 형성한다. 이로써, 듀얼 다마신 패턴(12a 및 14a)은 금속 도금층(17)으로 매립한다.Referring to FIG. 1B, the metal plating layer 17 is formed on the metal seed layer 16 including the dual damascene patterns 12a and 14a through metal electroplating. As a result, the dual damascene patterns 12a and 14a are embedded in the metal plating layer 17.
도 1c를 참조하면, 화학적 기계적 연마를 실시하여 제 2 절연막(14) 상의 금속 도금층(17) 및 확산 방지막(15)을 제거하여 전체 상부를 평탄화한다. 이로써, 듀얼 다마신 패턴(12a 및 14a) 내부에만 금속 도금층(17)이 잔류되어 금속 배선(18)이 형성된다.Referring to FIG. 1C, the entire upper part of the metal plating layer 17 and the diffusion barrier layer 15 on the second insulating layer 14 is removed by chemical mechanical polishing. As a result, the metal plating layer 17 remains inside the dual damascene patterns 12a and 14a to form the metal wiring 18.
도 2를 참조하면, 도 1a 및 도 1b에 도시된 공정 순서로 금속 배선을 형성할 경우 금속 도금층(17)의 화학적 기계적 연마를 실시하는 과정에서 금속 배선(18)의 상부에는 디싱(Dishing)에 의한 손실(A)이나 침식(B)이 발생되며, 또한 제 2 절연막(14)의 상부가 식각되어 얇아지고(Thining), 스크래치(Scratch) 등과 같은 결함(Defect)이 발생된다.Referring to FIG. 2, when the metal wires are formed in the process sequence shown in FIGS. 1A and 1B, the upper portion of the metal wires 18 may be subjected to dishing during the chemical mechanical polishing of the metal plating layer 17. Loss A or erosion B is caused, and the upper portion of the second insulating film 14 is etched to cause thinning, defects such as scratches, and the like.
디싱(A)은 금속과 절연 물질간의 연마 속도 차이에 의해 발생되며, 디싱(A)이 발생될 경우 금속 배선 가운데 부분의 두께가 낮아져 일정한 두께의 금속 배선을 형성할 수 없다. 침식(B) 금속과 절연 물질의 연마속도 차이와 패턴밀도(Pattern density)의 영향으로 인하여 발생되며, 패턴 밀도가 높은 지역의 금속 패턴과 실리콘 절연막 연마 속도가 타지역보다 높아서 발생된다. 실리콘 절연막이 얇아지는 것은 절연막의 목표 두께(Target oxide thickness)보다 많은 양의 절연막이 연마되어 발생된다. 스크래치는 슬러리 내의 연마재 제어(Abrasive control)에 문제가 있을 때 발생되며, 연마재의 사이즈를 일정하게 유지하지 못할 때 발생된다.The dishing (A) is generated by the difference in polishing rate between the metal and the insulating material, and when dishing (A) occurs, the thickness of the center portion of the metal wiring is lowered to form a metal wiring having a constant thickness. Erosion (B) This is caused by the difference in the polishing rate and pattern density of the metal and the insulating material, and is caused by the polishing rate of the metal pattern and the silicon insulating film in the region where the pattern density is high. The thinning of the silicon insulating film is caused by the polishing of the insulating film in an amount larger than the target oxide thickness of the insulating film. Scratch occurs when there is a problem with abrasive control in the slurry and occurs when the size of the abrasive is not kept constant.
이러한, 금속 CMP 공정의 결함들은 금속 배선 두께를 일정하게 제어(Control)할 수 없고, 배선간의 단락도 유발하여 전기적 특성을 저하시키는 문제점이 있다.Such defects of the metal CMP process may not control the thickness of the metal wires uniformly, and may cause short circuits between wires, thereby degrading electrical characteristics.
따라서, 본 발명은 상기의 문제점을 해결하기 위하여 듀얼 다마신 패턴의 측벽 및 저면에만 금속 시드층을 형성한 후 금속 도금을 실시하여 듀얼 다마신 패턴 내부에 금속 배선을 형성하므로써 단시간 내에 화학적 기계적 연마 공정을 완료할 수 있도록 화학적 기계적 연마로 제거해야 할 금속 도금층을 포함한 전체 막의 두께를 최소화하여 디싱이나, 침식 또는 스크래치 현상이 발생되는 것을 방지하고 공정의 신뢰성 및 소자의 전기적 특성을 향상시킬 수 있는 반도체 소자의 금속 배선 형성 방법을 제공하는데 그 목적이 있다.Therefore, in order to solve the above problems, the chemical seeding process is performed in a short time by forming a metal seed layer in the dual damascene pattern after forming a metal seed layer only on the sidewall and the bottom of the dual damascene pattern. A semiconductor device capable of preventing the occurrence of dishing, erosion or scratching, and improving process reliability and device electrical properties by minimizing the thickness of the entire film including the metal plating layer to be removed by chemical mechanical polishing to complete the process. Its purpose is to provide a method for forming metal wirings.
도 1a 내지 도 1c는 종래 기술에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 소자의 단면도.1A to 1C are cross-sectional views of a device for explaining a metal wiring formation method of a semiconductor device according to the prior art.
도 2a는 도 1d에서 CMP 공정을 통해 형성된 금속 배선 패턴에 발생되는 문제점을 설명하기 위한 소자의 단면도.FIG. 2A is a cross-sectional view of a device for describing a problem occurring in a metal wiring pattern formed through the CMP process in FIG. 1D. FIG.
도 3a 내지 도 3d는 본 발명에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 소자의 단면도.3A to 3D are cross-sectional views of a device for explaining a method for forming metal wirings of a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
11, 31 : 반도체 기판12, 32 : 제 1 절연막11, 31: semiconductor substrate 12, 32: first insulating film
12a, 32a : 콘택홀13, 33 : 식각 정지층12a, 32a: contact hole 13, 33: etch stop layer
14, 34 : 제 2 절연막14a, 34a : 트랜치14, 34: second insulating film 14a, 34a: trench
15, 35 : 확산 방지막16, 36 : 금속 시드층15, 35: diffusion barrier film 16, 36: metal seed layer
17, 37 : 금속 도금층18, 38 : 금속 배선17, 37: metal plating layer 18, 38: metal wiring
A : 디싱에 의한 손상B : 침식에 의한 손상A: Damage due to dishing B: Damage due to erosion
본 발명에 따른 반도체 소자의 금속 배선 형성 방법은 층간 절연막에 듀얼 다마신 패턴이 형성된 반도체 기판이 제공되는 제 1 단계, 듀얼 다마신 패턴을 포함한 층간 절연막 상에 확산 방지막을 형성하는 제 2 단계, 듀얼 다마신 패턴의 저면 및 측벽에 금속 시드층을 형성하는 제 3 단계, 전기 도금법으로 듀얼 다마신 패턴 내부에 금속 도금층을 형성하는 제 4 단계 및 화학적 기계적 연마로 층간 절연막 상부의 금속 도금층 및 확산 방지막을 제거하는 제 5 단계로 이루어지는 것을 특징으로 한다.The method for forming a metal wiring of a semiconductor device according to the present invention is a first step of providing a semiconductor substrate having a dual damascene pattern formed on the interlayer insulating film, a second step of forming a diffusion barrier on the interlayer insulating film including a dual damascene pattern, dual The third step of forming a metal seed layer on the bottom and sidewalls of the damascene pattern, the fourth step of forming a metal plating layer inside the dual damascene pattern by the electroplating method, and the metal plating layer and the diffusion barrier layer on the interlayer insulating film by chemical mechanical polishing And a fifth step of removing.
확산 방지막은 Ta 또는 TaN으로 형성하며, 500Å이하의 두께로 형성한다.The diffusion barrier is formed of Ta or TaN, and is formed to a thickness of 500 GPa or less.
금속 시드층은 구리를 이용하여 약 2000Å의 두께로 형성하며, CVD법으로 증착한다.The metal seed layer is formed to a thickness of about 2000 mm 3 using copper, and is deposited by CVD.
제 3 단계는 전체 상부에 금속 시드층을 형성하는 단계 및 산화재만을 이용한 화학적 기계적 연마로 층간 절연막 상의 금속 시드층을 제거하여 듀얼 다마신 패턴의 측벽 및 저면에만 금속 시드층을 형성하는 단계로 이루어진다.The third step includes forming a metal seed layer over the entire top and removing the metal seed layer on the interlayer insulating layer by chemical mechanical polishing using only an oxidizing material to form the metal seed layer only on the sidewalls and the bottom of the dual damascene pattern. .
화학적 기계적 연마는 산화재만으로 실시하며, 산화재로는 H2O2또는 NH4OH을 사용한다.Chemical mechanical polishing is performed only with an oxidizing material, and H 2 O 2 or NH 4 OH is used as the oxidizing material.
구리 도금층은 전기 도금법으로 구리를 도금하여 형성한다.The copper plating layer is formed by plating copper by electroplating.
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 더욱 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail.
도 3a 내지 도 3d는 종래 기술에 따른 CMP 공정을 통한 금속 배선 형성 방법을 설명하기 위한 소자의 단면도이다.3A to 3D are cross-sectional views of devices for describing a metal wiring forming method through a CMP process according to the prior art.
도 3a를 참조하면, 소정의 공정을 통해 반도체 소자를 형성하기 위한 여러 요소가 형성된 반도체 기판(31) 상에 제 1 절연막(32), 식각 정지층(33), 제 2 절연(34)을 순차적으로 형성한 후 포토 리소그라피/식각 공정으로 제 2 절연막(34)의 소정 영역을 식각하여 트랜치(34a)를 형성한다. 이로써, 트랜치(34a) 하부에는 식각 정지층(33)이 노출되며, 제 1 절연막(32)은 식각 정지층(33)에 의해 식각되지 않는다. 이후 콘택홀 마스크를 식각 마스크로 하는 식각 공정으로 식각 정지층(33)의 소정 영역을 식각하여 제 1 절연막(32)을 노출시킨 후 제 1 절연막(32)의 노출된 영역을 제거하여 콘택홀(32a)을 형성한다. 이로써, 콘택홀(32a)과 트랜치(34a)로 이루어진 듀얼 다마신 패턴이 형성된다.Referring to FIG. 3A, a first insulating layer 32, an etch stop layer 33, and a second insulating 34 are sequentially formed on a semiconductor substrate 31 on which various elements for forming a semiconductor device are formed through a predetermined process. After forming, the trench 34a is formed by etching a predetermined region of the second insulating layer 34 by a photolithography / etching process. As a result, the etch stop layer 33 is exposed under the trench 34a, and the first insulating layer 32 is not etched by the etch stop layer 33. Subsequently, a predetermined region of the etch stop layer 33 is etched to expose the first insulating layer 32 by an etching process using the contact hole mask as an etch mask, and then the exposed region of the first insulating layer 32 is removed to remove the contact hole. 32a). As a result, a dual damascene pattern including the contact hole 32a and the trench 34a is formed.
이후, 금속 이온의 확산 방지와 접착 특성(Adhesion)을 향상시키기 위하여 트랜치(34a)와 콘택홀(32a)로 이루어진 듀얼 다마신 패턴을 포함한 전체 상부에 확산 장벽층(35)을 형성한 후 순차적으로 전체 상부에 금속 시드층(36)을 형성한다.Thereafter, in order to prevent diffusion of metal ions and to improve adhesion properties, the diffusion barrier layer 35 is formed on the whole including the dual damascene pattern formed of the trench 34a and the contact hole 32a. The metal seed layer 36 is formed on the whole.
확산 장벽층(35)은 Ta 또는 TaN으로 형성하며, 500Å이하의 두께로 형성한다. 금속 시드층(36)은 구리로 형성한다. 또한, 금속 시드층(36)은 전기 도금법을 적용하기 위하여 약 2000Å의 두께로 형성하며, CVD법으로 증착한다.The diffusion barrier layer 35 is formed of Ta or TaN, and is formed to a thickness of 500 kPa or less. The metal seed layer 36 is formed of copper. In addition, the metal seed layer 36 is formed to a thickness of about 2000 kPa in order to apply the electroplating method, and is deposited by the CVD method.
도 3b를 참조하면, 화학적 기계적 연마를 실시하여 제 2 절연막(34) 상부의 금속 시드층을 제거하고, 듀얼 다마신 패턴(32a 및 34b)의 측벽 및 저면에만 금속 시드층(36)을 잔류시킨다.Referring to FIG. 3B, the metal seed layer on the second insulating layer 34 is removed by chemical mechanical polishing, and the metal seed layer 36 is left only on the sidewalls and bottom surfaces of the dual damascene patterns 32a and 34b. .
제 2 절연막(34) 상의 금속 시드층(36)을 제거하기 위한 화학적 기계적 연마는 슬러리(Slury) 대신에 H2O2나 NH4OH 등의 산화제(Oxidizer)만을 이용하여 10 내지 100초 동안 실시한다.Chemical mechanical polishing to remove the metal seed layer 36 on the second insulating film 34 is performed for 10 to 100 seconds using only an oxidizer such as H 2 O 2 or NH 4 OH instead of a slurry. do.
도 3c를 참조하면, 전기 도금을 실시하여 금속 시드층(36)의 상부 및 측면 쪽으로 금속 도금층(37)을 형성하여 듀얼 다마신 패턴 내부를 금속 도금층(37)으로 매립한다.Referring to FIG. 3C, the metal plating layer 37 is formed toward the upper and side surfaces of the metal seed layer 36 by electroplating to fill the dual damascene pattern in the metal plating layer 37.
도 3d를 참조하면, 화학적 기계적 연마를 실시하여 제 2 절연막(34) 상의 확산 방지막(35)을 제거함과 동시에 제 2 절연막(34) 상부로 높게 형성된 금속 도금층(37)을 제거하여 전체 상부를 평탄화한다. 이로써, 듀얼 다마신 패턴(32a 및 34a) 내부에 금속 배선(38)이 형성된다.Referring to FIG. 3D, a chemical mechanical polishing is performed to remove the diffusion barrier 35 on the second insulating layer 34 and to remove the metal plating layer 37 formed high on the second insulating layer 34 to planarize the entire upper portion. do. As a result, the metal wiring 38 is formed inside the dual damascene patterns 32a and 34a.
상기의 공정에서, 제 2 절연막(34) 상의 금속 시드층(36)을 화학적 기계적 연마로 제거할 때, 기존의 슬러리(Slury) 대신에 H2O2나 NH4OH 등의 산화제(Oxidizer)만을 이용하여 10 내지 100초 동안 화학적 기계적 연마를 실시하므로써 슬러리 연마재로 인하여 스크래치나 파티클(Particle)이 발생되는 것을 방지하고, 트랜치(34a)에 연마제가 잔류하는 것을 방지할 수 있다. 슬러리 대신에 산화재만으로 화학적 기계적 연마를 실시할 경우 연마율(Remove rate)이 저하되는 단점이 있으나, 금속 시드층(36)의 두께가 약 2000Å 내외이므로 수 십초 이내에 화학적 기계적 연마 공정을 완료할 수 있다. 기존의 금속 연마 시간은 전세정시간(Post cleaning time)을 제외하더라도 4분 가까이 되므로, 본 발명에서 화학적 기계적 연마 공정시 산화재만을 사용함으로 인해 발생되는 연마율 감소는 문제가 되지 않는다.In the above process, when the metal seed layer 36 on the second insulating film 34 is removed by chemical mechanical polishing, instead of the conventional slurry, only an oxidizer such as H 2 O 2 or NH 4 OH is used. By using the chemical mechanical polishing for 10 to 100 seconds using the slurry abrasive to prevent scratches or particles (particles) can be prevented, and to leave the abrasive in the trench 34a. If the mechanical mechanical polishing is carried out by the oxidant instead of the slurry, the removal rate is lowered. However, since the thickness of the metal seed layer 36 is about 2000 kPa, the chemical mechanical polishing process can be completed within a few tens of seconds. have. Existing metal polishing time is close to 4 minutes even after the post-cleaning time (excluding the post-cleaning time), the reduction of the polishing rate caused by using only the oxidant in the chemical mechanical polishing process in the present invention is not a problem.
또한, 제 2 절연막(34) 상의 확산 방지막(35)을 제거함과 동시에 제 2 절연막(34) 상부로 높게 형성된 금속 도금층(37)을 제거하기 위하여 화학적 기계적 연마를 실시하는 과정에서도, 확산 방지막(35)의 두께가 500Å이하이므로 화학적 기계적 연마를 수십초 정도만 실시하여도 확산 방지막(35)을 완전히 제거할 수 있다.In addition, in the process of performing chemical mechanical polishing to remove the diffusion barrier 35 on the second insulating layer 34 and to remove the metal plating layer 37 formed high on the second insulating layer 34, the diffusion barrier 35 ) Is less than or equal to 500 mm 3, so that the diffusion barrier 35 can be completely removed even if the chemical mechanical polishing is performed for several tens of seconds.
상기와 같이, 화학적 기계적 연마 공정 시간을 수십초 정도로 단축시키므로써 디싱, 침식, 스크래치 또는 파티클이 발생되는 것을 최소화할 수 있다.As described above, by shortening the chemical mechanical polishing process time by several tens of seconds, it is possible to minimize the occurrence of dishing, erosion, scratch or particles.
상술한 바와 같이, 본 발명은 듀얼 다마신 패턴의 측벽 및 저면에만 금속 시드층을 형성한 후 금속 도금을 실시하여 듀얼 다마신 패턴 내부에 금속 배선을 형성하므로써 화학적 기계적 연마로 제거 및 연마해야할 양을 최소화하고 연마 시간을 단축하여 디싱이나, 침식 또는 스크래치 현상이 발생되는 것을 방지하고 공정의 신뢰성 및 소자의 전기적 특성을 향상시킨다.As described above, the present invention forms the metal seed layer only on the sidewall and the bottom of the dual damascene pattern and then metal plating to form the metal wiring inside the dual damascene pattern, thereby reducing the amount to be removed and polished by chemical mechanical polishing. Minimize and shorten the polishing time to prevent dishing, erosion or scratching, and improve process reliability and device electrical characteristics.
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| KR19990015599A (en) * | 1997-08-07 | 1999-03-05 | 윤종용 | Method of forming dual damascene metal wiring layer of semiconductor device using electroless plating |
| US6140234A (en) * | 1998-01-20 | 2000-10-31 | International Business Machines Corporation | Method to selectively fill recesses with conductive metal |
| KR100283109B1 (en) * | 1998-12-28 | 2001-04-02 | 김영환 | Metal wiring formation method of semiconductor device |
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| KR100332118B1 (en) * | 1999-06-29 | 2002-04-10 | 박종섭 | Method of forming a metal wiring in a semiconductor device |
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