KR20020094961A - Method for forming contact of semiconductor device - Google Patents
Method for forming contact of semiconductor device Download PDFInfo
- Publication number
- KR20020094961A KR20020094961A KR1020010032883A KR20010032883A KR20020094961A KR 20020094961 A KR20020094961 A KR 20020094961A KR 1020010032883 A KR1020010032883 A KR 1020010032883A KR 20010032883 A KR20010032883 A KR 20010032883A KR 20020094961 A KR20020094961 A KR 20020094961A
- Authority
- KR
- South Korea
- Prior art keywords
- contact
- interlayer insulating
- insulating film
- forming
- contact plug
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 콘택 형성 방법에 관한 것으로, 보다 상세하게는, 임의의 세정액에 대해 상이한 식각 속도를 갖는 층간절연막들간의 식각률 차이를 이용하여 고단차의 콘택을 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact of a semiconductor device, and more particularly, to a method for forming a contact having a high step height by using an etching rate difference between interlayer insulating films having different etching rates for an arbitrary cleaning liquid.
반도체 소자의 고집적화가 진행되면서, 각종 패턴의 선폭 및 콘택홀의 직경이 감소되고 있으며, 이와는 반대로, 임의의 특성 확보를 위해 단차가 증가되고 있음은 주지의 사실이다. 이 때문에, 미세 선폭의 패턴 구현에 어려움을 나타내고 있으며, 특히, 금속배선 공정에서 하부 패턴과 상부 패턴간을 전기적으로 연결시키기 위한 콘택 형성에 어려움을 겪고 있다.As the integration of semiconductor devices proceeds, it is well known that line widths and diameters of contact holes of various patterns are reduced, and on the contrary, steps are increased to secure arbitrary characteristics. For this reason, it has been difficult to implement a pattern having a fine line width, and in particular, it is difficult to form a contact for electrically connecting the lower pattern and the upper pattern in the metallization process.
이에 따라, 고단차의 콘택을 용이하게 형성하기 위한 다양한 기술들이 시도되고 있다. 한 예로, 2회의 콘택 공정을 수행하는 방법이 시도되고 있으며, 부가해서, 하층 콘택과 상층 콘택간의 접촉 저항을 개선하고, 그리고, 오정렬에 기인하는 하층 콘택과 상층 콘택간의 단선 발생을 방지하기 위해 하층 콘택의 형성 후에는 랜딩 패드(Landing Pad)를 형성하고 있다.Accordingly, various techniques have been attempted to easily form a high step contact. For example, a method of performing two contact processes has been attempted, in addition, to improve the contact resistance between the lower contact and the upper contact, and to prevent the occurrence of disconnection between the lower contact and the upper contact due to misalignment. After forming the contact, a landing pad is formed.
자세하게, 도 1a 내지 도 1c는 종래 기술에 따른 고단차의 콘택 형성방법을 설명하기 위한 공정별 단면도로서, 이를 설명하면 다음과 같다.1A to 1C are cross-sectional views for each process for explaining a method for forming a high step contact according to the prior art, which will be described below.
먼저, 도 1a에 도시된 바와 같이, 트랜지스터와 같은 하지층(도시안됨)이 형성된 반도체 기판(1) 상에 제1층간절연막(1)을 형성한다. 그런다음, 상기 제1층간절연막(2)의 일부분을 선택적으로 식각하여 하지층의 일부분을 노출시키는 콘택홀을 형성하고, 이 콘택홀 내에 도전막을 매립시켜 제1콘택 플러그(3)를 형성한다.First, as shown in FIG. 1A, a first interlayer insulating film 1 is formed on a semiconductor substrate 1 on which a base layer (not shown) such as a transistor is formed. Then, a portion of the first interlayer insulating film 2 is selectively etched to form a contact hole exposing a portion of the underlying layer, and a conductive film is embedded in the contact hole to form the first contact plug 3.
그 다음, 도 1b에 도시된 바와 같이, 제1콘택 플러그(3)와 후속에서 형성되는 상층 콘택, 즉, 제2콘택 플러그간의 접촉 저항을 개선하면서 정렬 마진을 확보하기 위해, 제1콘택 플러그(3) 및 제1층간절연막(2) 상에 도전막을 증착한 후, 이를 패터닝하여 상기 제1콘택 플러그(3) 및 이에 인접한 제1층간절연막(2) 부분 상에 랜딩 패드(4)를 형성한다.Next, as shown in FIG. 1B, in order to secure an alignment margin while improving contact resistance between the first contact plug 3 and a subsequent upper contact formed, that is, the second contact plug, the first contact plug ( 3) and depositing a conductive film on the first interlayer insulating film 2 and patterning the conductive film to form a landing pad 4 on the first contact plug 3 and the portion of the first interlayer insulating film 2 adjacent thereto. .
이어, 도 1c에 도시된 바와 같이, 랜딩 패드(4)를 포함한 제1층간절연막(3) 상에 제2층간절연막(5)을 형성한다. 그런다음, 상기 제2층간절연막(5)의 일부분을 선택적으로 식각하여 상기 랜딩 패드(4)를 노출시키는 콘택홀을 형성하고, 이 콘택홀 내에 도전막을 매립시켜 상기 랜딩 패드(4)와 콘택되는 제2콘택 플러그(6)를 형성한다. 그리고나서, 금속막의 증착 및 패터닝을 통해 상기 제2콘택 플러그(6) 및 이에 인접한 제2층간절연막 부분 상에 금속배선(7)을 형성한다.Subsequently, as shown in FIG. 1C, a second interlayer insulating film 5 is formed on the first interlayer insulating film 3 including the landing pad 4. Then, a portion of the second interlayer insulating film 5 is selectively etched to form a contact hole exposing the landing pad 4, and a conductive film is embedded in the contact hole to contact the landing pad 4. The second contact plug 6 is formed. Then, the metal wiring 7 is formed on the second contact plug 6 and the portion of the second interlayer insulating film adjacent thereto through deposition and patterning of the metal film.
그러나, 상기와 같은 종래 기술에 따른 고단차의 콘택 형성방법은 랜딩 패드의 형성으로 인해 전체적인 공정이 복잡하고, 번거롭다는 문제점이 있으며, 이 때문에, 수율 측면에서 바람직하지 못하다.However, the above-described high-step contact forming method according to the prior art has a problem that the overall process is complicated and cumbersome due to the formation of the landing pad, and therefore, it is not preferable in terms of yield.
한편, 랜딩 패드의 형성을 생략하게 되면, 후속에서 접촉 저항의 개선 및 정렬 마진을 확보할 수 없으므로, 이에 대한 생략은 실질적으로 곤란하다.On the other hand, if the formation of the landing pad is omitted, it is difficult to subsequently improve the contact resistance and secure the alignment margin, so that the omission thereof is substantially difficult.
따라서, 본 발명은 상기와 같은 문제점을 해결하기 위하여 안출된 것으로서, 랜딩 패드의 형성을 생략함으로써, 전체적인 공정을 단순화시킬 수 있는 콘택 형성방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a contact that can simplify the overall process by eliminating the formation of the landing pad, which is devised to solve the above problems.
또한, 본 발명은 랜딩 패드의 형성을 생략하면서도 접촉 저항의 개선 및 정렬 마진을 확보할 수 있는 콘택 형성방법을 제공함에 그 다른 목적이 있다.Another object of the present invention is to provide a method for forming a contact that can improve contact resistance and secure alignment margin while omitting the formation of a landing pad.
도 1a 내지 도 1c는 종래 기술에 따른 고단차의 콘택 형성방법을 설명하기 위한 공정별 단면도.1A to 1C are cross-sectional views for each process for explaining a method for forming a high step contact according to the related art.
도 2a 내지 도 2e는 본 발명의 실시예에 따른 고단차의 콘택 형성방법을 설명하기 위한 공정별 단면도.2A to 2E are cross-sectional views of processes for explaining a method for forming a high step contact according to an exemplary embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
11 : 반도체 기판 12 : 제1층간절연막11 semiconductor substrate 12 first interlayer insulating film
13 : 제1콘택 플러그 14 : 제2층간절연막13: 1st contact plug 14: 2nd interlayer insulation film
15 : 제3층간절연막 16 : 콘택홀15: third interlayer insulating film 16: contact hole
17 : 제2콘택 플러그 18 : 금속배선17: second contact plug 18: metal wiring
상기와 같은 목적을 달성하기 위한 본 발명의 콘택 형성방법은, 상부에 하지층이 형성된 반도체 기판을 제공하는 단계; 상기 하지층을 포함한 반도체 기판 상에 상기 하지층의 일부분과 콘택되는 제1콘택 플러그를 갖는 제1층간절연막을 형성하는 단계; 상기 제1콘택 플러그 및 제1층간절연막 상에 임의의 세정액에 대해 제1식각속도를 갖는 제2층간절연막과 제1식각속도 보다 느린 제2식각속도를 갖는 제3층간절연막을 차례로 형성하는 단계; 상기 제3 및 제2층간절연막의 일부분을 선택적으로 식각하여 상기 제1콘택 플러그를 노출시키는 콘택홀을 형성하는 단계; 상기 콘택홀의 바텀 폭이 탑의 폭 보다 크게 되도록, 상기 콘택홀의 내벽을 임의의 세정액으로 세정 처리하는 단계; 및 상기 콘택홀 내에 도전막을 매립시켜, 상기 제1콘택 플러그와 콘택되는 제2콘택 플러그를 형성하는 단계를 포함한다.Contact forming method of the present invention for achieving the above object, the step of providing a semiconductor substrate having a base layer formed thereon; Forming a first interlayer insulating film having a first contact plug in contact with a portion of the underlayer on the semiconductor substrate including the underlayer; Sequentially forming a second interlayer insulating film having a first etching rate and a third interlayer insulating film having a second etching rate slower than the first etching rate with respect to any cleaning liquid on the first contact plug and the first interlayer insulating film; Selectively etching portions of the third and second interlayer dielectric layers to form contact holes exposing the first contact plugs; Cleaning the inner wall of the contact hole with an arbitrary cleaning liquid such that the bottom width of the contact hole is larger than the width of the tower; And embedding a conductive layer in the contact hole to form a second contact plug in contact with the first contact plug.
여기서, 본 발명의 방법은 임의의 세정액에 대한 제2층간절연막과 제3층간절연막의 식각 속도를 상기 제2층간절연막과 제3층간절연막을 형성하기 위한 퍼니스에서의 저온 증착시에 증착 온도 또는 소스를 변경시켜 조절하거나, 또는, 플라즈마 화학기상증착시에 플라즈마 파워, 증착 온도 및 소스를 변경시켜 조절하며, 상기 제2층간절연막과 제3층간절연막을 인-시튜(In-Situ)로 형성한다. 또한, 본 발명의 방법은 세정액으로서 HF 또는 NH4F를 포함하는 용액을 사용한다.Here, the method of the present invention is a method of etching temperature or source during low temperature deposition in a furnace for forming the second interlayer insulating film and the third interlayer insulating film with respect to the etching rate of the second interlayer insulating film and the third interlayer insulating film with respect to an arbitrary cleaning liquid. The second interlayer insulating film and the third interlayer insulating film are formed in-situ, or by controlling the plasma power, the deposition temperature and the source during plasma chemical vapor deposition. In addition, the method of the present invention uses a solution containing HF or NH 4 F as the cleaning liquid.
본 발명에 따르면, 임의의 세정액에 대해 상이한 식각 속도를 갖는 물질들의 적층으로 층간절연막을 형성한 후, 이 적층 구조의 층간절연막에 콘택홀을 형성하고, 이 상태에서 콘택홀에 대한 세정을 수행하여 콘택홀의 바텀이 탑 보다 큰 폭을 갖도록 함으로써, 랜딩 패드의 형성을 생략시킬 수 있다.According to the present invention, after forming an interlayer insulating film with a stack of materials having different etching rates with respect to an arbitrary cleaning solution, a contact hole is formed in the interlayer insulating film of the laminated structure, and in this state, the contact hole is cleaned. By making the bottom of the contact hole have a larger width than the top, the formation of the landing pad can be omitted.
(실시예)(Example)
이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2e는 본 발명의 실시에에 따른 콘택 형성방법을 설명하기 위한 공정별 단면도로서, 이를 설명하면 다음과 같다.2A to 2E are cross-sectional views for each process for explaining a method for forming a contact according to an embodiment of the present invention.
먼저, 도 2a에 도시된 바와 같이, 반도체 기판(11) 상에 트랜지스터를 포함하는 하지층(도시안됨)을 형성하고, 이 하지층을 덮도록 반도체 기판(11)의 전면 상에 제1층간절연막(12)을 형성한다. 그런다음, 상기 제1층간절연막(12)의 일부분을 선택적으로 식각하여 하지층의 소정 부분을 노출시키는 콘택홀을 형성하고, 이 콘택홀 내에 도전막을 매립시켜 제1콘택 플러그(13)를 형성한다.First, as shown in FIG. 2A, a base layer (not shown) including a transistor is formed on the semiconductor substrate 11, and a first interlayer insulating film is formed on the entire surface of the semiconductor substrate 11 to cover the base layer. (12) is formed. Thereafter, a portion of the first interlayer insulating film 12 is selectively etched to form a contact hole exposing a predetermined portion of the underlying layer, and a conductive film is embedded in the contact hole to form a first contact plug 13. .
다음으로, 도 2b에 도시된 바와 같이, 제1콘택 플러그(13)를 포함한 제1층간절연막(12) 상에 제2층간절연막(14)과 제3층간절연막(15)을 차례로 형성하고, 그런다음, 상기 제3 및 제2층간절연막(15, 14)의 일부분을 선택적으로 식각하여 상기 제1콘택 플러그(13)를 노출시키는 콘택홀(16)을 형성한다.Next, as shown in FIG. 2B, the second interlayer insulating film 14 and the third interlayer insulating film 15 are sequentially formed on the first interlayer insulating film 12 including the first contact plug 13. Next, portions of the third and second interlayer insulating layers 15 and 14 are selectively etched to form contact holes 16 exposing the first contact plugs 13.
여기서, 상기 제2층간절연막(14)과 제3층간절연막(15)은 임의의 세정액에 대해서 서로 다른 식각 속도를 갖는 물질막, 즉, 제2층간절연막(14)의 식각 속도가 제3층간절연막(15)의 식각 속도 보다 빠르게 되는 물질막으로 형성한다. 예컨데, 상기 제2층간절연막(14)은 통상의 산화막 또는 저유전율 절연막으로 형성하며, 제3층간절연막(15)은 통상의 산화막, 바람직하게 식각률이 낮은 실리콘질산화막(SiON) 또는 실리콘질화막(SiN)으로 형성한다.Here, the second interlayer insulating film 14 and the third interlayer insulating film 15 may be formed of a material film having a different etching rate with respect to an arbitrary cleaning liquid, that is, the etching rate of the second interlayer insulating film 14 is the third interlayer insulating film. It is formed of a material film that is faster than the etching rate of (15). For example, the second interlayer insulating film 14 is formed of a conventional oxide film or a low dielectric constant insulating film, and the third interlayer insulating film 15 is a conventional oxide film, preferably a silicon nitride oxide film (SiON) or a silicon nitride film (SiN) having a low etching rate. To form).
또한, 상기 제2층간절연막(14)은 스핀 코팅, 퍼니스(furnace)에서의 저온 증착, 또는, 플라즈마 화학기상증착(Plasma Chemical Vapor Deposition)으로 형성하며, 제3층간절연막(15)은 퍼니스에서의 저온 증착, 또는, 플라즈마 화학기상증착으로 형성한다.In addition, the second interlayer insulating film 14 is formed by spin coating, low temperature deposition in a furnace, or plasma chemical vapor deposition, and the third interlayer insulating film 15 is formed in a furnace. It is formed by low temperature deposition or plasma chemical vapor deposition.
게다가, 본 발명은 상기 제2 및 제3층간절연막(14, 15)을 인-시튜(In-Situ)로 형성하며, 그 증착시, 예컨데, 퍼니스에서의 저온 증착시에는 증착 온도, 또는, 소스(source)를 변경시키고, 그리고, 플라즈마 화학기상증착시에는 플라즈마 파워, 증착 온도 및 소스를 변경시킴으로써, 임의의 세정액에 대한 제2층간절연막(14)과 제3층간절연막(15)간의 식각 속도의 차이가 얻어지도록 한다.In addition, the present invention forms the second and third interlayer insulating films 14 and 15 in-situ, and at the time of deposition thereof, for example, at low temperature deposition in a furnace, the deposition temperature, or the source. By changing the source and changing the plasma power, the deposition temperature and the source during the plasma chemical vapor deposition, the etching rate between the second interlayer insulating film 14 and the third interlayer insulating film 15 for any cleaning liquid is changed. Make a difference.
계속해서, 도 2c에 도시된 바와 같이, HF 또는 NH4F/EG를 포함하는 용액을 사용하여 상기 콘택홀(16)에 대한 세정을 행한다. 이때, 상기 제2층간절연막(14)이 제3층간절연막(15) 보다 상기한 세정액에 대해서 더 빠른 속도로 식각되며, 이에 따라, 콘택홀(16)의 바텀 부분은 탑 부분 보다 더 큰 폭을 갖게 된다.Subsequently, as shown in Fig. 2C, the contact hole 16 is cleaned using a solution containing HF or NH 4 F / EG. At this time, the second interlayer insulating film 14 is etched at a faster rate than the third interlayer insulating film 15 with respect to the cleaning liquid, and thus, the bottom portion of the contact hole 16 has a larger width than the top portion. Will have
다음으로, 도 2d에 도시된 바와 같이, 바텀과 탑 부분이 상이한 폭을 갖는 콘택홀(16) 내에 매립 특성이 우수한 도전막, 예컨데, 텅스텐(W)을 매립시켜 상기 제1콘택 플러그(13)과 콘택되는 제2콘택 플러그(17)를 형성하고, 이 결과로서, 본 발명에 따른 고단차의 콘택을 완성한다.Next, as illustrated in FIG. 2D, the first contact plug 13 may be embedded by filling a conductive film having excellent embedding characteristics, for example, tungsten (W), in a contact hole 16 having a different width from a bottom portion and a top portion. A second contact plug 17 in contact with is formed, and as a result, a high step contact according to the present invention is completed.
이후, 도 2e에 도시된 바와 같이, 제3층간절연막(15) 상에 형성된 제2콘택 플러그 부분을 제거한 후, 잔류된 제2콘택 플러그(17) 및 제3층간절연막(15) 상에배선용 금속막의 증착 및 패터닝을 통해서 금속배선(18)을 형성한다.Subsequently, as shown in FIG. 2E, after removing the second contact plug portion formed on the third interlayer insulating layer 15, the metal for wiring on the remaining second contact plug 17 and the third interlayer insulating layer 15 is removed. The metallization 18 is formed through deposition and patterning of the film.
상기한 바와 같이, 2회의 콘택 공정으로 형성되는 본 발명에 따른 고단차의 콘택은 상층 콘택의 형성시에 콘택홀(16)의 바텀 폭이 그 이외 부분 보다 상대적으로 넓은 폭을 갖도록 만든 것으로 인해, 상층 콘택, 즉, 제2콘택 플러그(17)의 형성시, 오정렬에 기인하는 제1콘택 플러그(13)와의 콘택 불량이 발생되지 않으며, 또한, 제1콘택 플러그(13)와 제2콘택 플러그(17)간의 접촉 면적이 넓은 것으로 인해 그들간의 접촉 저항의 증가도 억제된다.As described above, the high step contact according to the present invention formed by two contact processes is made so that the bottom width of the contact hole 16 has a relatively wider width than the other portions at the time of forming the upper contact, In the formation of the upper contact, that is, the second contact plug 17, contact failure with the first contact plug 13 due to misalignment does not occur, and the first contact plug 13 and the second contact plug ( 17) The large contact area between them also suppresses the increase in contact resistance between them.
따라서, 본 발명의 경우에는 랜딩 패드없이도 접촉 저항의 개선 및 정렬 마진을 확보할 수 있기 때문에 제1콘택 플러그(13)의 형성 후에 랜딩 패드를 형성하기 위한 별도의 공정이 필요치 않으며, 그래서, 랜딩 패드의 형성에 기인하는 공정 수의 증가를 방지할 수 있게 된다.Therefore, in the case of the present invention, since the contact resistance can be improved and the alignment margin can be secured without the landing pad, a separate process for forming the landing pad after the formation of the first contact plug 13 is not necessary. It is possible to prevent an increase in the number of processes due to the formation of.
한편, 금속배선(18)의 형성시에는 통상의 금속배선 공정에서와 같이 배선용 금속막의 하부 및 상부 각각에 Ti/TiN으로된 베리어막 및 난반사막을 형성하며, 배선용 금속막으로서는 텅스텐, 알루미늄, 또는, 구리를 이용한다.On the other hand, in the formation of the metal wiring 18, barrier films and diffuse reflection films made of Ti / TiN are formed on the lower and upper portions of the wiring metal film, respectively, as in the usual metal wiring process, and tungsten, aluminum, or, as the wiring metal film, Copper is used.
이상에서와 같이, 본 발명은 임의의 세정액에 대한 식각 속도 차이를 이용함으로써, 랜딩 패드의 형성없이도 하층 콘택과 상층 콘택간의 접촉 저항 및 정렬 마진을 확보할 수 있으며, 이에 따라, 전체적인 콘택 형성 공정을 단순화시킬 수 있으며, 그래서, 제조 수율을 향상시킬 수 있다.As described above, the present invention can secure the contact resistance and alignment margin between the lower layer contact and the upper layer contact without forming the landing pad by using the difference in etching rate for any cleaning solution, thereby making the overall contact formation process possible. It can simplify, so that the production yield can be improved.
또한, 본 발명은 콘택 플러그들간의 접촉 저항을 낮출 수 있기 때문에, 소자의 신뢰성 확보는 물론, 동작 속도를 향상시킬 수 있다.In addition, the present invention can lower the contact resistance between the contact plugs, it is possible to ensure the reliability of the device, as well as to improve the operating speed.
기타, 본 발명은 그 요지가 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes in the range which does not deviate from the summary.
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2001-0032883A KR100408683B1 (en) | 2001-06-12 | 2001-06-12 | Method for forming contact of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2001-0032883A KR100408683B1 (en) | 2001-06-12 | 2001-06-12 | Method for forming contact of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20020094961A true KR20020094961A (en) | 2002-12-20 |
| KR100408683B1 KR100408683B1 (en) | 2003-12-06 |
Family
ID=27708797
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR10-2001-0032883A KR100408683B1 (en) | 2001-06-12 | 2001-06-12 | Method for forming contact of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100408683B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100949880B1 (en) * | 2007-10-31 | 2010-03-26 | 주식회사 하이닉스반도체 | Semicoductor device and Method of fabricating the same |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR950021093A (en) * | 1993-12-27 | 1995-07-26 | 김주용 | Metal contact formation method of semiconductor device |
| KR100195250B1 (en) * | 1996-10-10 | 1999-06-15 | 윤종용 | Method for forming a contact hole of a semiconductor device |
| KR100245091B1 (en) * | 1996-12-18 | 2000-03-02 | 김영환 | Process for forming interconnector of semiconductor device |
| TW379418B (en) * | 1998-06-12 | 2000-01-11 | United Microelectronics Corp | Damascence involving borderless via technologies |
| KR20000020016A (en) * | 1998-09-17 | 2000-04-15 | 윤종용 | Contact plug of semiconductor device with projection and method for forming thereof |
-
2001
- 2001-06-12 KR KR10-2001-0032883A patent/KR100408683B1/en not_active IP Right Cessation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100949880B1 (en) * | 2007-10-31 | 2010-03-26 | 주식회사 하이닉스반도체 | Semicoductor device and Method of fabricating the same |
| US7964501B2 (en) | 2007-10-31 | 2011-06-21 | Hynix Semiconductor Inc. | Semiconductor device and method of fabricating the same |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100408683B1 (en) | 2003-12-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR20020018025A (en) | Semiconductor device and method of manufacturing the same | |
| JP2023553604A (en) | Self-aligned top via | |
| KR100408683B1 (en) | Method for forming contact of semiconductor device | |
| KR20040093565A (en) | Method of manufacturing semiconductor device | |
| KR100578223B1 (en) | Method of fabricating of dual damascene of semiconductor device | |
| US6284645B1 (en) | Controlling improvement of critical dimension of dual damasceue process using spin-on-glass process | |
| KR100439477B1 (en) | Fabricating method of Tungsten plug in semiconductor device | |
| KR20060079376A (en) | Metal line formation method of semiconductor device | |
| KR100395907B1 (en) | Method for forming the line of semiconductor device | |
| KR0161458B1 (en) | Planerizing method of semiconductor device | |
| KR100579856B1 (en) | Metal line formation method of semiconductor device | |
| KR19990057892A (en) | Contact formation method of semiconductor device | |
| KR100269662B1 (en) | Method for manufacturing conductor plug of semiconductor device | |
| KR20010004008A (en) | Method for forming metal wiring of semiconductor device having Air-gap | |
| KR100252873B1 (en) | Multilayer metal line of semiconductor device and method for forming the same | |
| KR100395905B1 (en) | Deposition method for bitline and dielectric layer of semiconductor device | |
| KR100641488B1 (en) | Method for manufacturing contact of the semiconductor device | |
| KR101161665B1 (en) | Method for forming multi layer metal wiring of semiconductor device | |
| KR100372817B1 (en) | method of contacting metal lines of semiconductor device | |
| KR100502670B1 (en) | Semiconductor device formation method for preventing pattern shift caused by BPSG reflow | |
| KR20020058429A (en) | A wire in semiconductor device and method for fabricating the same | |
| KR20040042060A (en) | Method for forming the metal line in semiconductor device | |
| KR20010088091A (en) | Method for Planarization Device of Semiconductor | |
| KR20020085398A (en) | manufacturing method of semiconductor device | |
| KR19990055175A (en) | Metal wiring formation method of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20101025 Year of fee payment: 8 |
|
| LAPS | Lapse due to unpaid annual fee |