KR100372817B1 - method of contacting metal lines of semiconductor device - Google Patents

method of contacting metal lines of semiconductor device Download PDF

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Publication number
KR100372817B1
KR100372817B1 KR10-1999-0024049A KR19990024049A KR100372817B1 KR 100372817 B1 KR100372817 B1 KR 100372817B1 KR 19990024049 A KR19990024049 A KR 19990024049A KR 100372817 B1 KR100372817 B1 KR 100372817B1
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South Korea
Prior art keywords
layer
pad metal
metal
forming
photoresist pattern
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KR10-1999-0024049A
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Korean (ko)
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KR20010003674A (en
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이태국
길명군
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure

Abstract

본 발명은 반도체 소자의 금속 배선 콘택 방법을 개시한다. 개시된 본 발명은, 하부 금속 배선상에 접착층을 접착하고, 접착층상에 패드 금속막을 증착한다. 포토레지스트 패턴을 식각 마스크로 하여 패드 금속막과 접착층 및 하부 금속 배선을 식각하여 각각을 수 개의 라인으로 배열한다. 어느 한 라인에만 포토레지스트 패턴을 형성하고, 이 포토레지스트 패턴을 식각 마스크로 하여 나머지 패드 금속막을 식각한 후, 포토레지스트 패턴을 제거한다. 전체 결과물상에 절연층을 증착한 후, 잔존된 패드 금속막 표면을 기준으로 절연층을 연마하여 평탄화시킨다. 그런 다음, 전체 결과물 표면에 상부 금속 배선을 형성하여, 절연층에서 노출된 패드 금속막과 상부 금속 배선을 콘택시킨다.The present invention discloses a metal wiring contact method of a semiconductor device. The disclosed invention adheres an adhesive layer on a lower metal wiring, and deposits a pad metal film on the adhesive layer. Using the photoresist pattern as an etching mask, the pad metal film, the adhesive layer, and the lower metal wiring are etched, and each is arranged in several lines. A photoresist pattern is formed on only one line, and the remaining pad metal film is etched using this photoresist pattern as an etching mask, and then the photoresist pattern is removed. After depositing an insulating layer on the entire resultant, the insulating layer is polished and planarized based on the remaining pad metal film surface. Then, the upper metal wiring is formed on the entire resultant surface to contact the pad metal film and the upper metal wiring exposed in the insulating layer.

Description

반도체 소자의 금속 배선 콘택 방법{method of contacting metal lines of semiconductor device}Method of contacting metal lines of semiconductor device

본 발명은 반도체 소자의 금속 배선 콘택 방법에 관한 것으로서, 보다 구체적으로는 콘택홀을 이용하지 않고 상하 금속 배선을 콘택하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a metal wiring contact method of a semiconductor device, and more particularly, to a method of contacting upper and lower metal wirings without using a contact hole.

반도체 소자에서 상하 금속 배선간을 전기적으로 연결시키기 위해서, 기존에는 주로 콘택홀을 이용하였다. 상하 금속 배선간에 형성된 층간 절연막에 콘택홀을 형성하고, 이 콘택홀에 상부 금속 배선을 매립하여 하부 금속 배선과 전기적으로 연결시켰다.In order to electrically connect the upper and lower metal wires in the semiconductor device, a contact hole is mainly used. A contact hole was formed in the interlayer insulating film formed between the upper and lower metal wirings, and the upper metal wiring was buried in this contact hole to be electrically connected to the lower metal wiring.

반도체 디바이스의 고집적화에 따라, 콘택홀의 크기가 작아지게 되므로써 콘택 저항이 커지는 문제가 있다. 특히, 크기가 작은 콘택홀에 상부 금속 배선이 완전히 매립되지 못하여, 상하 금속 배선이 오픈되는 되는 심각한 문제가 있다.With high integration of semiconductor devices, there is a problem that the contact resistance becomes large due to the decrease in the size of the contact hole. In particular, there is a serious problem that the upper and lower metal wires are not completely filled in the small contact hole, and the upper and lower metal wires are opened.

이러한 고집적화에 따라 발생되는 문제점을 해소하기 위해, 배선을 층간절연막내에 완전히 매립된 형태로 형성하는 데머신(damascene) 공정이 제시되었다. 데머신 공정을 이용한 금속 배선 콘택 방법을 개략적으로 설명하면 다음과 같다.In order to solve the problems caused by such high integration, a damascene process has been proposed in which the wirings are completely embedded in the interlayer insulating film. A metal wiring contact method using the demachine process will be described as follows.

접합영역 또는 하부 도전층을 구비한 반도체 기판 상에 제 1 산화막을 형성하고, 제 1 산화막 상에 식각정지막으로서 질화막을 형성한다. 그런 다음, 질화막 상부에 제 2 산화막을 형성하고, 제 2 산화막 상부에 포토레지스트막을 도포한다. 콘택홀용 레티클을 이용하여 포토레지스트를 노광한 후 현상하여, 제 1 마스크 패턴을 형성한다. 제 1 마스크 패턴을 식각 마스크로 하여 제 2 산화막, 질화막 및 제 1 산화막을 식각하여 콘택홀을 형성한다.A first oxide film is formed on a semiconductor substrate having a junction region or a lower conductive layer, and a nitride film is formed on the first oxide film as an etch stop film. Then, a second oxide film is formed over the nitride film, and a photoresist film is applied over the second oxide film. The photoresist is exposed and developed using a contact hole reticle to form a first mask pattern. The second oxide film, the nitride film, and the first oxide film are etched using the first mask pattern as an etching mask to form contact holes.

공지된 방법으로 제 1 마스크 패턴을 제거하고, 제 2 산화막 상에 포토레지스트막을 도포한다. 이 포토레지스트를 배선용 레티클을 이용하여 노광한 후 현상하여 콘택홀 및 콘택홀 근방의 제 2 산화막을 일부 노출시키는 제 2 마스크 패턴을 형성한다. 제 2 마스크 패턴을 식각 마스크로 하여 질화막이 노출될 때까지 제 2 산화막을 식각하여 배선 형태의 콘택홀을 형성한다.The first mask pattern is removed by a known method, and a photoresist film is applied on the second oxide film. The photoresist is exposed using a wiring reticle and then developed to form a second mask pattern that partially exposes the contact hole and the second oxide film in the vicinity of the contact hole. Using the second mask pattern as an etching mask, the second oxide film is etched until the nitride film is exposed to form a contact hole in the form of a wiring.

공지된 방법으로 제 2 마스크 패턴을 제거하고, 콘택홀에 매립되도록 제 2 산화막 상에 배선용 금속막을 증착한다. 그런 다음, 제 2 산화막이 노출될 때까지 화학기계연마(Chemical Mechanical Polishing; CMP)로 금속막을 전면식각하여, 배선을 형성한다.The second mask pattern is removed by a known method, and a wiring metal film is deposited on the second oxide film so as to be filled in the contact hole. Then, the metal film is completely etched by chemical mechanical polishing (CMP) until the second oxide film is exposed to form wiring.

그러나, 상기한 바와 같은 종래의 데머신 공정을 이용한 금속 배선 콘택 방법은 공정수가 많고 공정 난이도가 매우 높다는 문제점이 있어서, 아직은 양산에 적용하기에는 곤란한 문제점이 있었다.However, the conventional metal wire contact method using the conventional demachine process has a problem in that the number of processes and the process difficulty are very high, and there is a problem that it is difficult to apply to mass production.

본 발명은 공정 난이도를 낮추고 공정수를 줄여서, 실제 양산에 적용하기가 유리한 반도체 소자의 금속 배선 콘택 방법을 제공하는데 목적이 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method for contacting metal wirings of a semiconductor device, which is advantageous to be applied to actual mass production by lowering process difficulty and reducing the number of processes.

도 1 내지 도 7은 본 발명의 실시예 1에 따른 금속 배선 콘택 방법을 순차적으로 나타낸 도면.1 to 7 are views sequentially showing a metal wiring contact method according to a first embodiment of the present invention.

도 8은 본 발명의 실시예 2에 따른 콘택 방법으로 형성된 반도체 소자를 나타낸 단면도.8 is a cross-sectional view illustrating a semiconductor device formed by a contact method according to Embodiment 2 of the present invention.

- 도면의 주요 부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawing-

1 ; 하부층 2 ; 하부 금속 배선One ; Lower layer 2; Bottom metal wiring

3 ; 접착층 4 ; 패드 금속막3; Adhesive layer 4; Pad metal film

5a ; 제 1 포토레지스트 패턴 5b ; 제 2 포토레지스트 패턴5a; First photoresist pattern 5b; Second photoresist pattern

6 ; 절연층 7 ; 상부 금속 배선6; Insulating layer 7; Upper metal wiring

상기한 본 발명의 목적을 달성하기 위하여, 본 발명에 따른 금속 배선 콘택 방법은 다음과 같다.In order to achieve the above object of the present invention, the metal wiring contact method according to the present invention is as follows.

하부 금속 배선상에 접착층을 접착하고, 접착층상에 패드 금속막을 증착한다. 포토레지스트 패턴을 식각 마스크로 하여 패드 금속막과 접착층 및 하부 금속 배선을 식각하여 각각을 수 개의 라인으로 배열한다. 어느 한 라인에만 포토레지스트 패턴을 형성하고, 이 포토레지스트 패턴을 식각 마스크로 하여 나머지 패드 금속막을 식각한 후, 포토레지스트 패턴을 제거한다. 전체 결과물상에 절연층을 증착한 후, 잔존된 패드 금속막 표면을 기준으로 절연층을 연마하여 평탄화시킨다. 그런 다음, 전체 결과물 표면에 상부 금속 배선을 형성하여, 절연층에서 노출된 패드금속막과 상부 금속 배선을 콘택시킨다.An adhesive layer is adhered on the lower metal wiring, and a pad metal film is deposited on the adhesive layer. Using the photoresist pattern as an etching mask, the pad metal film, the adhesive layer, and the lower metal wiring are etched, and each is arranged in several lines. A photoresist pattern is formed on only one line, and the remaining pad metal film is etched using this photoresist pattern as an etching mask, and then the photoresist pattern is removed. After depositing an insulating layer on the entire resultant, the insulating layer is polished and planarized based on the remaining pad metal film surface. Then, the upper metal wiring is formed on the entire resultant surface to contact the pad metal film and the upper metal wiring exposed in the insulating layer.

상기된 본 발명에 의하면, 패드 금속막을 이용해서 간단한 공정으로 상하 금속 배선을 콘택하는 것이 구현된다. 그러므로, 본 발명에 따른 방법은 양산 공정에 적용하기가 유리하다.According to the present invention described above, contacting the upper and lower metal wirings in a simple process using the pad metal film is implemented. Therefore, the method according to the invention is advantageously applied to mass production processes.

이하, 첨부된 도면을 참조하여 본 발명의 실시예를 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.

[실시예 1]Example 1

도 1 내지 도 7은 본 발명의 실시예 1에 따른 금속 배선 콘택 방법을 순차적으로 나타낸 도면으로서, 첨자 a는 단면도이고, 첨자 b는 평면도이다.1 to 7 are views sequentially showing a metal wiring contact method according to the first embodiment of the present invention, subscript a is a cross-sectional view, subscript b is a plan view.

먼저, 도 1에 도시된 바와 같이, 기저층(1)상에 하부 금속층(2), 접착층(3) 및 패드 금속층(4)을 순차적으로 적층한다. 이때, 접착층(3)으로는 티타늄막과 티타늄 질화막의 적층막이 이용된다. 그런 다음, 패드 금속층(4)상에 포토레지스트를 도포한 후 이를 패터닝하여, 도 2와 같은 제 1 포토레지스트 패턴(5a)을 형성한다.First, as shown in FIG. 1, the lower metal layer 2, the adhesive layer 3, and the pad metal layer 4 are sequentially stacked on the base layer 1. At this time, a laminated film of a titanium film and a titanium nitride film is used as the adhesive layer 3. Then, the photoresist is applied on the pad metal layer 4 and then patterned to form the first photoresist pattern 5a as shown in FIG. 2.

이어서, 제 1 포토레지스트 패턴(5a)을 식각 마스크로 하여 패드 금속층(4), 접착층(3) 및 하부 금속층(2)을 식각한다. 그리하여, 수 개의 라인 형상으로 이루어진 패드 금속층(4), 즉 패드 금속 플러그(4)와 수 개의 라인 형상으로 이루어진 패드 금속층(2), 즉 하부 금속 배선(2)을 형성한다. 그런 다음, 제 1 포토레지스트 패턴(5a)을 제거하면, 도 3과 같은 구조가 된다.Subsequently, the pad metal layer 4, the adhesive layer 3, and the lower metal layer 2 are etched using the first photoresist pattern 5 a as an etching mask. Thus, the pad metal layer 4 having several line shapes, that is, the pad metal plug 4 and the pad metal layer 2 having several line shapes, that is, the lower metal wiring 2 are formed. Then, when the first photoresist pattern 5a is removed, a structure as shown in FIG. 3 is obtained.

이어서, 도 4와 같이 상부 금속 배선과 콘택될 어느 한 패드 금속 플러그(4)와 그 하부에 위치하는 접착층(3) 및 하부 금속 배선(2)에만 제 2 포토레지스트 패턴(5b)을 형성한다. 따라서, 나머지 패드 금속 플러그(4)와 접착층(3) 및 하부 금속 배선(2)은 노출된 상태이다.Subsequently, as shown in FIG. 4, the second photoresist pattern 5b is formed only on one of the pad metal plugs 4 to be contacted with the upper metal wirings, the adhesive layer 3 and the lower metal wirings 2 disposed below the pad metal plugs 4. Therefore, the remaining pad metal plug 4, the adhesive layer 3 and the lower metal wiring 2 are exposed.

그런 다음, 제 2 포토레지스트 패턴(5b)을 식각 마스크로 하여, 각 패드 금속 플러그(4)를 식각하여 제거한다. 따라서, 오직 제 2 포토레지스트 패턴(5b)내에 위치하고 있는 패드 금속 플러그(4)만이 남게 된다. 그런 다음, 제 2 포토레지스트 패턴(5b)을 스트립하여 제거하면 도 5에 도시된 구조가 된다.Then, each pad metal plug 4 is etched and removed using the second photoresist pattern 5b as an etch mask. Thus, only the pad metal plug 4 located in the second photoresist pattern 5b remains. Then, stripping and removing the second photoresist pattern 5b results in the structure shown in FIG.

이어서, 도 6과 같이, 상기 기저층(1) 전면상에 절연층(6)을 도포한 후, 잔존된 패드 금속 플러그(4) 표면을 기준으로 하여 CMP 공정을 이용해서 절연층(6)을 연마한다. 따라서, 패드 금속 플러그(4) 표면만이 절연층(6)으로부터 노출된다.Subsequently, as shown in FIG. 6, after the insulating layer 6 is applied on the entire surface of the base layer 1, the insulating layer 6 is polished by using the CMP process based on the remaining pad metal plug 4 surface. do. Thus, only the pad metal plug 4 surface is exposed from the insulating layer 6.

마지막으로, 전체 결과물상에 상부 금속층을 증착한 후 이를 패터닝하여, 도 7과 같이 패드 금속 플러그(4)에 콘택된 상부 금속 배선(7)을 형성한다.Finally, the upper metal layer is deposited on the entire resultant and then patterned to form the upper metal wiring 7 contacted with the pad metal plug 4 as shown in FIG. 7.

한편, 하부 금속 배선(2)으로는 텅스텐이, 상부 금속 배선(7)으로는 알루미늄이 사용될 수 있고, 식각 가스로는 SF6와 Cl2 가스가 사용되어서 상호 다른 식각 선택비를 갖게 할 수 있다.Meanwhile, tungsten may be used as the lower metal wire 2, and aluminum may be used as the upper metal wire 7, and SF may be used as an etching gas.6And Cl2 Gases can be used to have different etch selectivity.

또한, 상기한 실시예를 이용하여, 에어갭(air gap) 방식으로 금속 배선을 형성할 수 도 있다.In addition, by using the above-described embodiment, it is also possible to form a metal wiring in an air gap (air gap) method.

즉, 도 8에서와 같이, 도 5까지 진행된 결과물 상부에 PECVD(plasma enhanced chemical vapor deposition) 방식으로 제 1 산화막(11)을 증착한다. 이때, 하부 금속 배선(2)간의 거리가 미세하므로, 하부 금속 배선(2) 사이에 에어갭(10)이 발생된다. 이때, 에어갭(10)은 공지된 바와 같이, 하부 금속 배선(2)사이를 절연시키는 역할을 한다.That is, as shown in FIG. 8, the first oxide layer 11 is deposited on the resultant process up to FIG. 5 by plasma enhanced chemical vapor deposition (PECVD). At this time, since the distance between the lower metal lines 2 is minute, an air gap 10 is generated between the lower metal lines 2. At this time, the air gap 10 serves to insulate between the lower metal wires 2 as is known.

그후, 결과물을 평탄화시키기 위하여, 결과물 상부에 HDP(high density plasma) 방식으로 제 2 산화막(12)을 증착한다. 그 다음, 금속 플러그(4)가 오픈되도록 제 2 산화막(12)을 처리한 후, 제 2 산화막(12) 상부에 금속 플러그(4)와 콘택되도록 상부 금속 배선(7)을 형성한다.Then, in order to planarize the resultant, a second oxide film 12 is deposited on the resultant in a high density plasma (HDP) manner. Next, after the second oxide film 12 is processed to open the metal plug 4, the upper metal wire 7 is formed on the second oxide film 12 to be in contact with the metal plug 4.

상기한 본 발명에 의하면, 데머신 공정에 비해 공정수가 대폭 줄어들게 되고, 또한 공정 난이도가 높지는 않다. 따라서, 데머신 공정에 비해 양산에 적용하기가 매우 유리하다.According to the present invention described above, the number of steps is significantly reduced compared to the demachine process, and the process difficulty is not high. Therefore, it is very advantageous to apply to mass production compared to the demachine process.

또한, 본 발명은 상기 실시예에 한정되지 않고, 본 발명의 기술적 요지를 벗어나지 않는 범위내에서 다양하게 변형시켜 실시할 수 있다.In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.

Claims (4)

기저층상에 하부 금속층과 접착층 및 패드 금속층을 순차적으로 적층한 후, 각 층을 제 1 포토레지스 패턴을 식각 마스크로 식각하여, 수 개의 라인 형상으로 이루어진 패드 금속 플러그와 하부 금속 배선을 형성하는 단계;Sequentially laminating a lower metal layer, an adhesive layer, and a pad metal layer on the base layer, and then etching each layer with the etch mask using the first photoresist pattern to form pad metal plugs and lower metal wires having a plurality of line shapes; 상기 패터닝된 각 층들중 어느 한 패드 금속 플러그와 접착층 및 하부 금속 배선에만 제 2 포토레지스트를 형성하는 단계;Forming a second photoresist on only one of the pad metal plugs and the adhesive layer and the lower metal wiring of each of the patterned layers; 상기 제 2 포토레지스트 패턴을 식각 마스크로 하여 나머지 패드 금속 플러그를 제거한 후, 상기 제 2 포토레지스트 패턴을 제거하는 단계;Removing the remaining pad metal plug by using the second photoresist pattern as an etching mask, and then removing the second photoresist pattern; 상기 기저층 전면상에 패드 금속 플러그의 표면이 노출되도록 절연층을 형성하는 단계; 및Forming an insulating layer over the base layer to expose a surface of a pad metal plug; And 상기 노출된 패드 금속 플러그 표면에 상부 금속 배선을 콘택하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 금속 배선 콘택 방법.And contacting an upper metal wiring to the exposed pad metal plug surface. 제 1 항에 있어서, 상기 접착층은 티타늄막과 티타늄질화막의 적층막인 것을 특징으로 하는 반도체 소자의 금속 배선 콘택 방법.The method of claim 1, wherein the adhesive layer is a laminated film of a titanium film and a titanium nitride film. 제 1 항에 있어서, 상기 절연층을 형성하는 단계는, 상기 결과물 상부에 절연층을 형성한 다음, 패드 금속 플러그가 노출되도록 절연층을 연마하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 금속 배선 콘택 방법.The metal line of claim 1, wherein the forming of the insulating layer comprises forming an insulating layer on the resultant, and then polishing the insulating layer to expose the pad metal plug. Contact method. 제 1 항에 있어서, 상기 절연층을 형성하는 단계는, 상기 결과물 상부에 PECVD 방식으로 제 1 산화막을 형성하여 에어갭을 형성하는 단계; 상기 제 1 산화막 상부에 HDP방식으로 제 2 산화막을 형성하는 단계; 및 상기 제 2 산화막을 식각하여 패드 금속 플러그를 노출시키는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 금속 배선 콘택 방법.The method of claim 1, wherein the forming of the insulating layer comprises: forming an air gap by forming a first oxide layer on the resultant by PECVD; Forming a second oxide film on the first oxide film by an HDP method; And etching the second oxide film to expose a pad metal plug.
KR10-1999-0024049A 1999-06-24 1999-06-24 method of contacting metal lines of semiconductor device KR100372817B1 (en)

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