KR20020058486A - Method for fabricating semiconductor device - Google Patents
Method for fabricating semiconductor device Download PDFInfo
- Publication number
- KR20020058486A KR20020058486A KR1020000086593A KR20000086593A KR20020058486A KR 20020058486 A KR20020058486 A KR 20020058486A KR 1020000086593 A KR1020000086593 A KR 1020000086593A KR 20000086593 A KR20000086593 A KR 20000086593A KR 20020058486 A KR20020058486 A KR 20020058486A
- Authority
- KR
- South Korea
- Prior art keywords
- contact
- peripheral region
- mask
- ion implantation
- semiconductor device
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
Abstract
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로서, 특히 주변영역의 PMOS 트랜지스터의 특성을 개선시키도록 한 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device to improve characteristics of a PMOS transistor in a peripheral region.
통상적으로 반도체 소자 제조시, 셀영역과 주변영역이 정의된 반도체 기판상에 워드라인을 형성한 후, 이온주입 공정을 진행하여 소스/드레인 접합을 형성한다. 계속해서, 셀영역 상부에 하부전극/유전막/상부전극으로 이루어진 캐패시터를 형성한 후, 전면에 층간절연막을 형성하고 콘택마스크를 이용하여 층간절연막을 식각하여 상부전극과 주변영역의 소스/드레인 접합이 노출되는 금속배선용 콘택홀을 형성한다. 계속해서, 콘택홀에 배리어메탈, 금속배선을 형성한 후, 금속배선과 배리어메탈을 선택적으로 식각하여 캐패시터의 상부전극 및 주변영역의 소스/드레인 접합에 접속되는 금속배선을 형성한다.Generally, in manufacturing a semiconductor device, after forming a word line on a semiconductor substrate in which a cell region and a peripheral region are defined, an ion implantation process is performed to form a source / drain junction. Subsequently, after forming a capacitor including a lower electrode / dielectric film / upper electrode on the cell region, an interlayer insulating film is formed on the front surface and the interlayer insulating film is etched by using a contact mask to etch the source / drain junction between the upper electrode and the peripheral region. The exposed contact hole for metal wiring is formed. Subsequently, after the barrier metal and the metal wiring are formed in the contact hole, the metal wiring and the barrier metal are selectively etched to form the metal wiring connected to the source / drain junction of the upper electrode of the capacitor and the peripheral region.
그러나, 상술한 종래기술에서는 금속배선용 콘택홀을 형성하는 과정, 특히 주변영역의 PMOS 트랜지스터에서 배리어메탈과 소스/드레인 접합간의 반응으로 인해 배리어메탈과 소스/드레인 접합의 계면에 TiSi 계열의 물질이 형성된다. 이로 인해, 소스/드레인 접합의 도핑 농도가 균일하지 않고 저항이 높아져 트랜지스터의 특성이 저하되는 문제점이 있다.However, in the above-described prior art, a TiSi-based material is formed at the interface between the barrier metal and the source / drain junction due to the process of forming the contact hole for metal wiring, in particular, the reaction between the barrier metal and the source / drain junction in the PMOS transistor in the peripheral region. do. For this reason, there is a problem in that the doping concentration of the source / drain junction is not uniform and the resistance is high, thereby degrading the characteristics of the transistor.
특히, 금속배선용 콘택홀의 깊이가 깊어짐에 따라 셀영역과 주변영역을 동시에 노출시키는 콘택 식각시, 주변영역의 반도체기판의 손실이 커짐으로 인해 도핑농도가 더욱 불균일해지고, 주변영역의 콘택 식각과정에서 셀영역의 하부층이 관통되는 문제점이 있다.In particular, as the depth of the contact hole for metal wiring becomes deeper, the doping concentration becomes more uneven due to the large loss of the semiconductor substrate in the peripheral region when the contact etching exposing the cell region and the peripheral region at the same time, and the cell during the contact etching process of the peripheral region. There is a problem that the lower layer of the region penetrates.
본 발명은 상기 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 반도체기판의 손실 및 접합 도핑 농도의 불균일 현상을 방지하는데 적합한 반도체 소자의 제조 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the problems of the prior art, and an object thereof is to provide a method for manufacturing a semiconductor device suitable for preventing the loss of the semiconductor substrate and the non-uniformity of the junction doping concentration.
도 1a 내지 도 1e는 본 발명의 실시예에 따른 반도체 소자의 제조 방법을 도시한 도면.1A to 1E illustrate a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
11 : 반도체 기판 12 : 필드산화막11 semiconductor substrate 12 field oxide film
13 : 워드라인 14 : 소스/드레인 접합13 word line 14 source / drain junction
15 : 폴리실리콘 플러그 16 : 비트라인15 polysilicon plug 16 bit line
17 : 스토리지노드 콘택 플러그 18a : 하부전극17: storage node contact plug 18a: lower electrode
18b : 유전막 18c : 상부전극18b: dielectric film 18c: upper electrode
18d : 플레이트 19a, 19b, 19c : 층간절연막18d: plate 19a, 19b, 19c: interlayer insulating film
20 : 산화막 21 : 제 1 콘택마스크20: oxide film 21: first contact mask
22 : 제 1 콘택홀 23 : 제 2 콘택마스크22: first contact hole 23: second contact mask
24 : 제 2 콘택홀 25 : 배리어 메탈24: second contact hole 25: barrier metal
26 : 이온주입마스크 27 : 금속배선26: ion implantation mask 27: metal wiring
상기의 목적을 달성하기 위한 본 발명의 반도체 소자의 제조 방법은 셀영역과 주변영역이 정의된 반도체기판상에 트랜지스터, 캐패시터를 순차적으로 형성하는 단계, 상기 반도체 기판의 전면에 층간절연막을 형성하는 단계, 제 1 콘택 마스크를 이용하여 상기 층간절연막을 식각하여 상기 주변영역 트랜지스터의 소정 부분이 노출되는 금속배선용 제 1 콘택홀을 형성하는 단계, 제 2 콘택마스크를 이용하여 상기 층간절연막을 식각하여 셀영역의 소정 부분이 노출되는 금속배선용 제 2 콘택홀을 형성하는 단계, 상기 제 1,2 콘택홀을 포함한 전면에 배리어메탈을 형성하는 단계, 상기 배리어메탈상에 이온주입마스크를 형성하는 단계, 상기 이온주입마스크를 이용하여 상기 주변영역 트랜지스터의 소정 부분에 불순물을 이온주입하는 단계, 및 상기 배리어메탈상에 금속배선용 금속막을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.A semiconductor device manufacturing method of the present invention for achieving the above object is a step of sequentially forming a transistor and a capacitor on a semiconductor substrate defined a cell region and a peripheral region, forming an interlayer insulating film on the front surface of the semiconductor substrate Etching the interlayer insulating layer using a first contact mask to form a first contact hole for metal wiring through which a portion of the peripheral region transistor is exposed; etching the interlayer insulating layer using a second contact mask to etch a cell region Forming a second contact hole for metal wiring to which a predetermined portion of the metal wire is exposed; forming a barrier metal on the entire surface including the first and second contact holes; forming an ion implantation mask on the barrier metal; Implanting impurities into a predetermined portion of the peripheral region transistor using an implantation mask, and dissociation Characterized by yirueojim to the metal phase comprises the step of forming the metal wiring metal film.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 1a 내지 도 1e는 본 발명의 실시예에 따른 반도체 소자의 제조 방법을 도시한 도면이다.1A to 1E are diagrams illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
도 1a에 도시된 바와 같이, 셀영역과 주변영역이 정의된 반도체기판(11)에 소자간 격리를 위한 필드산화막(12)을 형성한 후, 반도체기판(11)상에 다수의 워드라인(13)을 형성한다. 불순물 이온주입을 실시하여 반도체기판(11)에 소스/드레인 접합(14)을 형성하고, 워드라인(13) 사이에 매립되어 소스/드레인접합(14)에 접속되는 다수의 폴리실리콘플러그(15)를 형성한다. 이 때, 주변영역에는 PMOS의 p+ 소스/드레인 접합이 형성된다.As shown in FIG. 1A, after forming a field oxide film 12 for isolation between devices in a semiconductor substrate 11 in which a cell region and a peripheral region are defined, a plurality of word lines 13 are formed on the semiconductor substrate 11. ). A plurality of polysilicon plugs 15 are formed by impurity ion implantation to form source / drain junctions 14 on the semiconductor substrate 11, and are embedded between the word lines 13 and connected to the source / drain junctions 14. To form. At this time, a p + source / drain junction of the PMOS is formed in the peripheral region.
계속해서, 폴리실리콘플러그(15) 중 어느 하나에 접속되는 비트라인(16)을 형성하고, 비트라인(16) 상부에 폴리실리콘 플러그(15) 중 다른 하나의 폴리실리콘플러그(15)에 접속되는 스토리지노드 콘택플러그(17)를 형성하고, 스토리지노드 콘택플러그(17)에 접속되는 하부전극/유전막/상부전극(18a, 18b, 18c)의 적층 구조로 이루어지는 캐패시터를 형성한다.Subsequently, a bit line 16 connected to any one of the polysilicon plugs 15 is formed, and the polysilicon plug 15 connected to the other of the polysilicon plugs 15 is formed on the bit line 16. A storage node contact plug 17 is formed, and a capacitor having a stacked structure of lower electrodes / dielectric films / upper electrodes 18a, 18b, 18c connected to the storage node contact plugs 17 is formed.
여기서, 미설명 도면부호 19a,19b,19c는 층간절연막, 13a는 스페이서이며, 캐패시터는 트렌치(Trench) 구조이다.Herein, reference numerals 19a, 19b, and 19c denote interlayer insulating films, 13a denotes spacers, and capacitors have a trench structure.
이와 같이 셀영역에 트랜지스터 및 캐패시터를 형성한 후, 후속 공정으로 셀영역과 주변영역의 금속배선을 위한 콘택 식각을 실시한다.After forming the transistor and the capacitor in the cell region as described above, the contact etching for metal wiring of the cell region and the peripheral region is performed in a subsequent process.
먼저, 상부전극(18c)을 서로 접속시키는 플레이트(18d)를 형성한 후, 전면에 제 1 산화막(20)을 형성한 다음 에치백이나 화학적기계적연마를 통해 제 1 산화막(20)을 평탄화한다.First, after forming the plate 18d connecting the upper electrodes 18c to each other, the first oxide film 20 is formed on the entire surface, and then the first oxide film 20 is planarized through etch back or chemical mechanical polishing.
도 1b에 도시된 바와 같이, 제 1 산화막(20)상에 감광막을 도포하고 노광 및 현상으로 패터닝하여 금속배선용 제 1 콘택마스크(21)를 형성한다.As shown in FIG. 1B, a photosensitive film is coated on the first oxide film 20 and patterned by exposure and development to form a first contact mask 21 for metal wiring.
계속해서, 제 1 콘택마스크(21)을 이용하여 주변영역의 소스/드레인 접합(14)의 소정부분을 노출시키는 제 1 콘택홀(22)을 형성한다.Subsequently, a first contact hole 22 is formed using the first contact mask 21 to expose a predetermined portion of the source / drain junction 14 in the peripheral region.
도 1c에 도시된 바와 같이, 제 1 콘택마스크(21)을 제거한 후, 전면에 감광막을 도포하고 노광 및 현상으로 패터하여 금속배선용 제 2 콘택마스크(23)을 형성한다. 제 2 콘택마스크(23)을 이용하여 제 1 산화막(20)을 식각하여 플레이트(18d)의 소정 표면이 노출되는 제 2 콘택홀(24)을 형성한다.As shown in FIG. 1C, after removing the first contact mask 21, a photosensitive film is coated on the entire surface and patterned by exposure and development to form a second contact mask 23 for metal wiring. The first oxide film 20 is etched using the second contact mask 23 to form a second contact hole 24 through which a predetermined surface of the plate 18d is exposed.
이와 같이, 한 번의 콘택마스크로 셀영역과 주변영역을 동시에 노출시키는 통상의 기술과는 다르게, 각각 제 1 콘택마스크(21) 및 제 2 콘택마스크(23)를 이용하여 주변영역의 소스/드레인 접합을 노출시키는 제 1 콘택홀(22)과 셀영역을 노출시키는 제 2 콘택홀(24)을 형성하므로, 과도식각으로 인한 주변영역의 반도체기판(11)의 손실을 방지하고 주변영역의 식각 과정에서 셀영역의 플레이트(18d)가 관통되는 현상을 방지할 수 있다.As described above, unlike the conventional technique of simultaneously exposing the cell region and the peripheral region with one contact mask, the source / drain junction of the peripheral region using the first contact mask 21 and the second contact mask 23, respectively. Since the first contact hole 22 to expose the second region and the second contact hole 24 to expose the cell region are formed, it is possible to prevent the loss of the semiconductor substrate 11 in the peripheral region due to the excessive etching and in the etching process of the peripheral region. The phenomenon that the plate 18d of the cell region penetrates can be prevented.
도 1d에 도시된 바와 같이, 제 2 콘택마스크(23)을 제거하고, 노출된 제 1,2 콘택홀을 포함한 전면에 배리어메탈(25)을 증착한 후, 전면에 감광막을 도포하고 노광 및 현상으로 패터닝하여 주변영역의 소스/드레인 접합(14)을 노출시키는 이온주입마스크(26)를 형성한 다음, 이온주입마스크(26)를 이용하여 p+ 불순물을 이온주입 및 열처리한다.As shown in FIG. 1D, the second contact mask 23 is removed, the barrier metal 25 is deposited on the entire surface including the exposed first and second contact holes, and then the photosensitive film is coated on the entire surface to expose and develop. After patterning to form an ion implantation mask 26 exposing the source / drain junction 14 in the peripheral region, the ion implantation mask 26 is used to implant and heat the p + impurities.
이와 같이, 배리어메탈(25) 형성후에 추가의 이온주입마스크(26)를 형성하고, 이를 이용하여 소스/드레인 접합(14) 즉, PMOS의 소스/드레인접합에 불순물을 이온주입하므로, 배리어메탈(25)과 소스/드레인 접합(14)간의 계면에 형성된 물질로 인한 소스/드레인 접합(14)의 도핑 농도의 감소를 보상해준다.In this manner, after the barrier metal 25 is formed, an additional ion implantation mask 26 is formed and impurities are implanted into the source / drain junction 14, that is, the source / drain junction of the PMOS. 25) compensates for the reduction in the doping concentration of the source / drain junction 14 due to the material formed at the interface between the source / drain junction 14.
도 1e에 도시된 바와 같이, 이온주입마스크(26)을 제거한 후, 배리어메탈 (25)을 화학적기계적연마나 에치백하여 콘택홀에만 잔류시키고 전면에 금속배선용 금속막을 증착한 후, 선택적으로 패터닝하여 배리어메탈(25)상에 금속배선(27)을 형성한다.As shown in FIG. 1E, after the ion implantation mask 26 is removed, the barrier metal 25 is chemically polished or etched back to remain only in the contact hole, and a metal film for metal wiring is deposited on the front surface, and then selectively patterned. The metal wiring 27 is formed on the barrier metal 25.
본 발명이 실시예에서는 주변영역의 소스/드레인 접합을 노출시키는 금속배선용 콘택홀 형성에 대해서만 설명하였지만, 주변 영역의 다른 부분, 예컨대, 워드라인, 비트라인, 폴리실리콘 플러그를 노출시키는 금속배선용 콘택홀 형성시에도 적용할 수 있다.In the present embodiment, only the formation of the contact hole for metal wiring exposing the source / drain junction of the peripheral region has been described, but the contact hole for metal wiring exposing other portions of the peripheral region, for example, word lines, bit lines, and polysilicon plugs It can also be applied at the time of formation.
또한, 본 발명의 실시예에서는 제 1 콘택마스크를 이용하여 주변영역을 먼저 식각한 후 제 2 콘택마스크를 이용하여 셀영역을 식각하였으나, 반대로 제 1 콘택마스크를 이용하여 셀영역을 먼저 식각하고, 제 2 콘택마스크를 이용하여 주변영역을 식각하여 동일한 효과를 구현할 수 있다. 이 때, 주변영역의 다른 부분을 노출시키는 콘택홀 형성시에도 적용 가능하며 주변영역 트랜지스터의 소스/드레인 접합을 노출시키는 경우 배리어메탈 형성후 추가로 불순물 이온주입을 실시한다.Further, in the embodiment of the present invention, the peripheral region is first etched using the first contact mask, and then the cell region is etched using the second contact mask. On the contrary, the cell region is first etched using the first contact mask. The same effect may be realized by etching the peripheral area using the second contact mask. In this case, it is also applicable to the formation of a contact hole exposing other portions of the peripheral region. In the case of exposing the source / drain junction of the peripheral region transistor, impurity ion implantation is additionally performed after the barrier metal is formed.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같은 본 발명의 반도체 소자의 제조 방법은 셀영역과 주변영역의 금속배선용 콘택식각을 두 번에 걸쳐 실시하므로 반도체 기판의 손실을 방지할 수 있고, 배리어메탈 형성후에 추가로 이온주입을 실시하므로 소스/드레인 접합의 도핑 농도를 보상해 줄 수 있는 효과가 있다.As described above, in the method of manufacturing a semiconductor device of the present invention, since the contact etching for the metal wiring of the cell region and the peripheral region is performed twice, the loss of the semiconductor substrate can be prevented, and ion implantation is further performed after the barrier metal is formed. Therefore, the doping concentration of the source / drain junction can be compensated for.
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000086593A KR100681203B1 (en) | 2000-12-30 | 2000-12-30 | Method for fabricating semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000086593A KR100681203B1 (en) | 2000-12-30 | 2000-12-30 | Method for fabricating semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20020058486A true KR20020058486A (en) | 2002-07-12 |
| KR100681203B1 KR100681203B1 (en) | 2007-02-09 |
Family
ID=27689583
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020000086593A KR100681203B1 (en) | 2000-12-30 | 2000-12-30 | Method for fabricating semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100681203B1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102546659B1 (en) | 2015-12-11 | 2023-06-23 | 삼성전자주식회사 | Semiconductor device and method of manufacturing the same |
-
2000
- 2000-12-30 KR KR1020000086593A patent/KR100681203B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR100681203B1 (en) | 2007-02-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100249159B1 (en) | Method for manufacturing semiconductor device | |
| KR100348316B1 (en) | Method for Fabricating of Semiconductor Device | |
| KR100309799B1 (en) | method for manufacturing of semiconductor device | |
| KR100460270B1 (en) | Mehod for fabricating of semiconductor device | |
| KR100681203B1 (en) | Method for fabricating semiconductor device | |
| US6001681A (en) | Method to reduce the depth of a buried contact trench by using a thin split polysilicon thickness | |
| KR20010054169A (en) | Method for manufacturing semiconductor device | |
| KR100287543B1 (en) | How to Improve Contact Resistance in Semiconductor Devices | |
| KR100464934B1 (en) | Method for fabricating semiconductor device | |
| KR20020058485A (en) | Method for fabricating semiconductor device | |
| KR20010008589A (en) | Method of forming bit-line of semiconductor device utilized damascene process | |
| KR100689672B1 (en) | Method for fabricating semiconductor device | |
| JP2836530B2 (en) | Method for manufacturing semiconductor device | |
| KR100268939B1 (en) | Method for manufacturing of semiconductor device | |
| KR940009595B1 (en) | Forming method of metal wiring film | |
| KR100340884B1 (en) | Method for forming transistor in semiconductor device | |
| KR100369341B1 (en) | Manufacturing method of semiconductor device for forming plug | |
| KR20000044607A (en) | Method for manufacturing semiconductor element | |
| KR100215884B1 (en) | Semiconductor device and manufacture thereof | |
| KR20020058512A (en) | Method for fabricating semiconductor device | |
| KR100383773B1 (en) | Semiconductor device and method of manufacturing thereof | |
| KR100240272B1 (en) | Method of manufacturing semiconductor device | |
| KR20040059488A (en) | Structure of transistor and manufacturing method of the same | |
| KR20040058942A (en) | Method of manufacturing a semiconductor device | |
| KR20010017213A (en) | Method of manufacturing a semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20110126 Year of fee payment: 5 |
|
| LAPS | Lapse due to unpaid annual fee |