KR20020056292A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
KR20020056292A
KR20020056292A KR1020000085615A KR20000085615A KR20020056292A KR 20020056292 A KR20020056292 A KR 20020056292A KR 1020000085615 A KR1020000085615 A KR 1020000085615A KR 20000085615 A KR20000085615 A KR 20000085615A KR 20020056292 A KR20020056292 A KR 20020056292A
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South Korea
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film
low dielectric
semiconductor device
manufacturing
hard mask
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KR1020000085615A
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Korean (ko)
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송정규
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박종섭
주식회사 하이닉스반도체
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Priority to KR1020000085615A priority Critical patent/KR20020056292A/en
Publication of KR20020056292A publication Critical patent/KR20020056292A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric

Abstract

PURPOSE: A method of fabricating a semiconductor device is provided to prevent via fail. CONSTITUTION: An interlayer dielectric(22) is deposited on a semiconductor substrate(20) having a transistor. A metal interconnection(24) is formed on the interlayer dielectric. A low dielectric layer(30) is deposited on the entire structure including the metal interconnection and then a part of the low dielectric layer is eliminated and planarized in order to expose the metal interconnection. A hardmask(40) is deposited on the resultant structure. A via hole(100) is formed on thc hard mask to contact with the metal interconnection.

Description

반도체 소자의 제조방법{METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}Manufacturing method of semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

본 발명은 반도체 소자의 제조방법에 관한 것으로, 보다 구체적으로는 반도체 소자의 비아홀 형성방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming via holes in a semiconductor device.

일반적으로, 저유전율막은 반도체 소자의 속도를 증가하기 위하여 필요하며 논리(LOGIC) 소자에서부터 필요성이 대두되었지만, 메모리 소자에서도 집적도 증가에 따라 금속배선사이의 간격이 좁아지며 이에 따라 금속배선사이의 기생 캐패시턴스가 증가하여 점차 적용이 검토되고 있는 추세이다.In general, a low dielectric constant film is required to increase the speed of semiconductor devices, and the need arises from logic devices, but in memory devices, the spacing between metal wirings is narrowed according to the increase in the degree of integration, and thus the parasitic capacitance between metal wirings. Is increasing and application is gradually being considered.

저유전율막의 경우는 폴리머막(유전율:2.7)을 비롯하여 플라즈마 기상 화학증착법에 의한 실리콘산화막(유전율:2.7)이 현재 적용 가능성등에 관해 평가되고 있다.In the case of a low dielectric constant film, a silicon oxide film (dielectric constant: 2.7) by plasma vapor phase chemical vapor deposition, including a polymer film (dielectric constant: 2.7), is currently evaluated for applicability.

도 1은 이온 빔 집속장치(Focused Ion Beam, FIB)에 의한 분석결과를 나타낸 것이다. 도시된 바와같이, 기존의 Al-RIE구조에서 금속배선간 절연막으로 폴리머막만을 사용할 경우, 비아의 횡방향으로 에칭 및 금속배선등의 후속공정에 의해 비이상적인 비아불량이 발생되는 문제점이 있다. 이러한 문제점의 예상원인으로는 비아에칭 후속 세정공정에 의해 제거되지 않는 잔류물과 텅스텐막 증착전에 사용되는 확산방지금속공정에서의 단차피복성 및 연속적증착특성(continuous film 형성) 이 좋지 못한 문제와의 복합적인 요소에 의한 것으로 여겨진다.Figure 1 shows the analysis results by the ion beam focusing apparatus (Focused Ion Beam, FIB). As shown in the drawing, when only the polymer film is used as the insulating film between the metal lines in the existing Al-RIE structure, there is a problem that non-ideal via defects are generated by subsequent processes such as etching and metal wiring in the transverse direction of the vias. The probable cause of this problem is that residues which are not removed by the post-etching subsequent cleaning process and the problem that the step coverage and the continuous film formation are poor in the diffusion preventing metal process used before the tungsten film deposition. It is believed to be due to a combination of factors.

한편, 플라즈마 기상 화학 증착법에 의한 저유전율막의 경우는 공극매립성이 매우 열악하여 단독으로는 AI-RIE구조에서 적용하는 것은 불가능한 문제점이 있다. 실제 소자에서의 비아불량은 매우 치명적이며 하나의 비아에 수십 개의 셀이 연결되어 있기 때문에 비아 수율은 100% 를 확보해야 한다.On the other hand, in the case of the low dielectric constant film by the plasma vapor deposition method is very poor pore buried property there is a problem that can not be applied alone in the AI-RIE structure. Via defects in real devices are very fatal and via yield is 100% because dozens of cells are connected to one via.

따라서, 상기와 같은 문제점을 해결하기 위한 본 발명의 목적은, 비아불량을 억제할 수 있는 반도체 소자의 제조방법을 제공하는 것이다.Accordingly, an object of the present invention for solving the above problems is to provide a method for manufacturing a semiconductor device capable of suppressing via defects.

도 1은 종래 기술에 따른 반도체 소자의 제조방법에 대한 문제점을 설명하기 위한 도면.1 is a view for explaining a problem with the manufacturing method of a semiconductor device according to the prior art.

도 2a 내지 도 2d는 본 발명에 따른 반도체 소자의 제조방법을 설명하기 위한 제조공정도.2A to 2D are manufacturing process diagrams for explaining a method for manufacturing a semiconductor device according to the present invention.

* 도면의 주요 부분에 대한 부호설명 ** Explanation of Signs of Major Parts of Drawings *

20 : 반도체 기판 22 : 층간절연막20 semiconductor substrate 22 interlayer insulating film

24 : 금속배선 30 : 저유전막24 metal wiring 30 low dielectric film

40 : 하드마스크막 100 : 비아홀40: hard mask 100: via hole

상기 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 제조방법은 트랜지스터가 형성된 반도체 기판상에 층간절연막을 증착하는 단계; 상기 층간절연막상에 금속배선을 형성하는 단계; 상기 금속배선이 형성된 전체구조상에 저유전막을 증착하는 단계; 상기 금속배선이 노출되도록 저유전막을 소정부분 제거하여 평탄화하는 단계; 상기 단계까지의 결과물상에 하드마스크막을 증착하는 단계; 상기 금속배선과 콘택되도록 상기 하드마스크막상에 비아홀을 형성하는 단계를 포함하여 구성하는 것을 특징으로 한다.A method of manufacturing a semiconductor device according to the present invention for achieving the above object comprises the steps of depositing an interlayer insulating film on a semiconductor substrate on which a transistor is formed; Forming a metal wiring on the interlayer insulating film; Depositing a low dielectric film on the entire structure where the metal wiring is formed; Removing the planarized portion of the low dielectric film to expose the metal wiring; Depositing a hard mask film on the resultant material up to this step; And forming a via hole on the hard mask layer to be in contact with the metal wiring.

이하, 본 발명의 바람직한 실시예를 첨부한 도면에 의거하여 상세히 설명한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2d는 본 발명에 따른 반도체 소자의 제조방법을 설명하기 위한 제조공정도이다.2A to 2D are manufacturing process diagrams for explaining a method of manufacturing a semiconductor device according to the present invention.

먼저, 도 2a에 도시된 바와같이, 트랜지스터(도시되지 않음)가 형성되어 있는 반도체 기판(20)상에 트랜지스터의 접합 영역(도시되지 않음)중 어느 한 영역을 노출시키는 콘택홀(미도시)이 구비된 층간 절연막(22)을 형성한다. 그런다음, 노출된 접합 영역(도시되지 않음)과 콘택되도록 플러그 콘택막(미도시), 예컨대, 플러그 폴리실리콘막을 형성한다. 이어서, 상기 플러그 콘택막과 접촉하는 금속배선(24)을 형성한다.First, as shown in FIG. 2A, a contact hole (not shown) exposing any region of a junction region (not shown) of a transistor is formed on a semiconductor substrate 20 on which a transistor (not shown) is formed. The interlayer insulating film 22 provided is formed. Then, a plug contact film (not shown), for example, a plug polysilicon film, is formed to be in contact with the exposed junction region (not shown). Subsequently, a metal wiring 24 in contact with the plug contact film is formed.

그 다음, 도 2b에 도시된 바와같이, 상기 금속배선(24)이 형성된 전체구조상에 저유전막(30)을 증착한다. 이러한 저유전막(30)은 바람직하게는 폴리머막으로 형성된다. 또한, 상기 저유전막(30)은 스핀 코팅방식으로 폴리에릴렌에테르막, 벤조 사이클론 부텐막 또는 폴리이미드막으로 형성할 수 있다. 이 때, 상기 폴리머막, 폴리에릴렌에테르막 및 벤조 사이클론 부텐막은 유전율이 2.7이고, 상기 폴리아미드막은 유전율이 3.0 ~ 3.5 정도이며 바람직하게 두께 500 ~ 15000Å으로 형성된다.Next, as shown in FIG. 2B, the low dielectric film 30 is deposited on the entire structure in which the metal wiring 24 is formed. This low dielectric film 30 is preferably formed of a polymer film. In addition, the low dielectric film 30 may be formed of a polyylene ether film, a benzo cyclone butene film or a polyimide film by spin coating. In this case, the polymer film, the polyylene ether film and the benzo cyclone butene film have a dielectric constant of 2.7, and the polyamide film has a dielectric constant of about 3.0 to 3.5 and preferably has a thickness of 500 to 15000 kPa.

그 다음, 도 2c에 도시된 바와같이, 상기 저유전막(30)을 형성한 후, 저유전막(30)에 의해 기인된 비아 불량제거 및 평탄화 특성을 향상시키기 위해, 금속배선(24)이 노출되도록 상기 저유전막(30)을 소정부분 제거한 다음, 상기 단계까지의 결과물 상에 하드마스크막(40)을 증착한다. 이 때, 상기 소정부분의 저유전막(30) 제거공정은 에치백 공정 및 화학기계연마 공정 중 어느 하나에 의해 실행되며, 상기 에치백 공정은 에칭 가스로 산소 및 질소 가스를 사용하여 실행한다.Next, as shown in FIG. 2C, after the low dielectric film 30 is formed, the metal wiring 24 is exposed to improve via defect removal and planarization characteristics caused by the low dielectric film 30. After removing the predetermined portion of the low dielectric film 30, the hard mask film 40 is deposited on the resultant up to the step. At this time, the process of removing the low dielectric film 30 of the predetermined portion is performed by either an etch back process or a chemical mechanical polishing process, and the etch back process is performed using oxygen and nitrogen gas as etching gases.

상기 하드마스크막(40)은 플라즈마 기상 화학 증착법 및 스핀 코팅중 어느하나에 의해 형성되며, 실리콘 산화막 또는 저유전 SiOC막으로 형성된다. 이 때, 상기 하드마스크막은 바람직하게 두께 500 ~ 10000Å으로 형성된다.The hard mask film 40 is formed by one of plasma vapor deposition and spin coating, and is formed of a silicon oxide film or a low dielectric SiOC film. At this time, the hard mask film is preferably formed with a thickness of 500 ~ 10000Å.

그 다음, 도 2d에 도시된 바와같이, 상기 하드마스크막(40) 상부에 금속배선(24)의 콘택영역을 한정하는 감광막 패턴(미도시)을 형성한다. 이어서, 상기 감광막패턴을 식각장벽으로 상기 하드마스크막(40)을 식각하여 상기 금속배선의 소정부분을 노출시키는 비아홀(100)을 형성한다.Next, as shown in FIG. 2D, a photoresist pattern (not shown) defining a contact region of the metal line 24 is formed on the hard mask layer 40. Subsequently, the hard mask layer 40 is etched using the photoresist pattern as an etch barrier to form a via hole 100 exposing a predetermined portion of the metal wiring.

이어서, 도면에는 도시하지 않았지만, 상기 비아홀(100)상에 금속막을 매립하여 반도체 소자를 제조하는 후속공정을 실시한다.Subsequently, although not shown in the drawing, a subsequent process of manufacturing a semiconductor device by embedding a metal film on the via hole 100 is performed.

상기한 바와같은 본 발명에 따른 반도체 소자의 제조방법은 다음과 같은 효과가 있다.The method of manufacturing a semiconductor device according to the present invention as described above has the following effects.

상기 저유전막(30)을 형성한 후, 저유전막(30)에 의해 기인된 비아 불량제거 및 평탄화 특성을 향상시키기 위해, 금속배선(24)이 노출되도록 상기 저유전막(30)을 소정부분 제거한 다음, 상기 단계까지의 결과물 상에 하드마스크막(40)을 증착한다. 이에, 비아불량 방지에 의해 수율 향상과 평탄화 특성을 향상시킬 수 있다.After the low dielectric film 30 is formed, a portion of the low dielectric film 30 is removed to expose the metal wiring 24 to improve via defect removal and planarization characteristics caused by the low dielectric film 30. Then, the hard mask film 40 is deposited on the resultant up to this step. As a result, the yield improvement and the planarization characteristic can be improved by preventing the via defect.

또한, 상기 저유전막의 적용으로 유기물인 폴리머막의 소자집적을 안정적으로 구현할 수 있으며, 기존의 방법보다 소자의 구동속도를 증가시킬 수 있다.In addition, the application of the low-k dielectric film can stably implement the device integration of the organic polymer film, it is possible to increase the driving speed of the device than the conventional method.

기타, 본 발명의 요지를 벗어나지 않는 범위내에서 다양하게 변경하여 실시할 수 있다.In addition, it can implement in various changes within the range which does not deviate from the summary of this invention.

Claims (11)

트랜지스터가 형성된 반도체 기판상에 층간절연막을 증착하는 단계;Depositing an interlayer insulating film on the semiconductor substrate on which the transistor is formed; 상기 층간절연막상에 금속배선을 형성하는 단계;Forming a metal wiring on the interlayer insulating film; 상기 금속배선이 형성된 전체구조상에 저유전막을 증착하는 단계;Depositing a low dielectric film on the entire structure where the metal wiring is formed; 상기 금속배선이 노출되도록 저유전막을 소정부분 제거하여 평탄화하는 단계;Removing the planarized portion of the low dielectric film to expose the metal wiring; 상기 단계까지의 결과물상에 하드마스크막을 증착하는 단계;Depositing a hard mask film on the resultant material up to this step; 상기 금속배선과 콘택되도록 상기 하드마스크막상에 비아홀을 형성하는 단계를 포함하여 구성하는 것을 특징으로 하는 반도체 소자의 제조방법.And forming a via hole on the hard mask layer to be in contact with the metal wiring. 제 1항에 있어서,The method of claim 1, 상기 저유전막은 스핀코팅에 의해 형성되는 것을 특징으로 하는 반도체 소자의 제조방법.The low dielectric film is a semiconductor device manufacturing method, characterized in that formed by spin coating. 제 1항에 있어서,The method of claim 1, 상기 저유전막은 두께 500 ~ 15000Å으로 형성되는 것을 특징으로 하는 반도체 소자의 제조방법.The low dielectric film is a semiconductor device manufacturing method, characterized in that formed in a thickness of 500 ~ 15000 1. 제 2항에 있어서,The method of claim 2, 상기 저유전막은 폴리에릴렌에테르막, 벤조 사이클론 부텐막 및 폴리이미드막 중 어느 하나인 것을 특징으로 하는 반도체 소자의 제조방법.The low dielectric film is any one of a polyylene ether film, a benzo cyclone butene film and a polyimide film. 제 2항에 있어서.The method of claim 2. 상기 저유전막은 온도 200 ~ 500℃에서 형성되는 것을 특징으로 하는 반도체 소자의 제조방법.The low dielectric film is a method of manufacturing a semiconductor device, characterized in that formed at a temperature of 200 ~ 500 ℃. 제 1항에 있어서,The method of claim 1, 상기 저유전막은 폴리머막인 것을 특징으로 하는 반도체 소자의 제조방법.The low dielectric film is a method of manufacturing a semiconductor device, characterized in that the polymer film. 제 1항에 있어서,The method of claim 1, 상기 소정부분의 저유전막 제거공정은 에치백 공정 및 화학기계연마 공정 중 어느하나에 의해 실행되는 것을 특징으로 하는 반도체 소자의 제조방법.And the low dielectric film removing step of the predetermined portion is performed by one of an etch back step and a chemical mechanical polishing step. 제 7항에 있어서,The method of claim 7, wherein 상기 에치백 공정은 에칭 가스로 산소 및 질소 가스를 사용하는 것을 특징으로 하는 반도체 소자의 제조방법.The etch back process is a method of manufacturing a semiconductor device, characterized in that the use of oxygen and nitrogen gas as the etching gas. 제 1항에 있어서,The method of claim 1, 상기 하드마스크막은 플라즈마 기상 화학 증착법 및 스핀 코팅중 어느하나에의해 형성되는 것을 특징으로 하는 반도체 소자의 제조방법.The hard mask film is a semiconductor device manufacturing method, characterized in that formed by any one of a plasma vapor deposition method and spin coating. 제 9항에 있어서,The method of claim 9, 상기 하드마스크막은 실리콘 산화막 및 저유전 SiOC막 중 하나인 것을 특징으로 하는 반도체 소자의 제조방법.The hard mask film is a semiconductor device manufacturing method, characterized in that one of a silicon oxide film and a low dielectric SiOC film. 제 9항에 있어서,The method of claim 9, 상기 하드마스크막은 두께 500 ~ 10000Å으로 형성되는 것을 특징으로 하는 반도체 소자의 제조방법.The hard mask film is a manufacturing method of a semiconductor device, characterized in that formed in a thickness of 500 ~ 10000Å.
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